Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7225704 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
974 |
| auto[1] |
4995137 |
1 |
|
|
T25 |
878 |
|
T28 |
389 |
|
T32 |
1001 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11596097 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1822 |
| auto[1] |
624744 |
1 |
|
|
T25 |
30 |
|
T28 |
16 |
|
T32 |
125 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7230757 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
845 |
| auto[1] |
4990084 |
1 |
|
|
T25 |
1007 |
|
T28 |
394 |
|
T29 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2174886 |
1 |
|
|
T25 |
542 |
|
T28 |
158 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
310772 |
1 |
|
|
T25 |
17 |
|
T28 |
5 |
|
T32 |
36 |
| auto[1] |
auto[1] |
auto[0] |
2190454 |
1 |
|
|
T25 |
435 |
|
T28 |
220 |
|
T32 |
396 |
| auto[1] |
auto[1] |
auto[1] |
313972 |
1 |
|
|
T25 |
13 |
|
T28 |
11 |
|
T32 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |