Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7237847 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
896 |
| auto[1] |
4982994 |
1 |
|
|
T25 |
956 |
|
T28 |
385 |
|
T32 |
836 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11594410 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
1816 |
| auto[1] |
626431 |
1 |
|
|
T25 |
36 |
|
T28 |
20 |
|
T32 |
145 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7225487 |
1 |
|
|
T23 |
95 |
|
T24 |
175 |
|
T25 |
915 |
| auto[1] |
4995354 |
1 |
|
|
T25 |
937 |
|
T28 |
440 |
|
T29 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2196131 |
1 |
|
|
T25 |
459 |
|
T28 |
199 |
|
T29 |
8 |
| auto[1] |
auto[0] |
auto[1] |
315085 |
1 |
|
|
T25 |
21 |
|
T28 |
5 |
|
T32 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2172792 |
1 |
|
|
T25 |
442 |
|
T28 |
221 |
|
T32 |
339 |
| auto[1] |
auto[1] |
auto[1] |
311346 |
1 |
|
|
T25 |
15 |
|
T28 |
15 |
|
T32 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |