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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 937
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T758 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.329481004 Apr 02 12:26:58 PM PDT 24 Apr 02 12:26:58 PM PDT 24 69510434 ps
T759 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.749124985 Apr 02 12:26:58 PM PDT 24 Apr 02 12:26:59 PM PDT 24 23702062 ps
T760 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.675745101 Apr 02 12:27:29 PM PDT 24 Apr 02 12:27:30 PM PDT 24 171014513 ps
T761 /workspace/coverage/cover_reg_top/25.gpio_intr_test.746409136 Apr 02 12:26:58 PM PDT 24 Apr 02 12:26:59 PM PDT 24 59014400 ps
T762 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1921385584 Apr 02 12:26:57 PM PDT 24 Apr 02 12:26:58 PM PDT 24 54529198 ps
T763 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.856143580 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 18715640 ps
T764 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2157290501 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:00 PM PDT 24 56062532 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1780486921 Apr 02 12:26:54 PM PDT 24 Apr 02 12:26:56 PM PDT 24 359721535 ps
T766 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1975736887 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 16104624 ps
T767 /workspace/coverage/cover_reg_top/8.gpio_intr_test.651134213 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 12496174 ps
T768 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1845946182 Apr 02 12:26:48 PM PDT 24 Apr 02 12:26:49 PM PDT 24 27972468 ps
T769 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1534276017 Apr 02 12:26:58 PM PDT 24 Apr 02 12:27:00 PM PDT 24 141442953 ps
T770 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3203888907 Apr 02 12:26:59 PM PDT 24 Apr 02 12:27:00 PM PDT 24 34487547 ps
T771 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.671779073 Apr 02 12:27:07 PM PDT 24 Apr 02 12:27:09 PM PDT 24 40969180 ps
T772 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1326903464 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:01 PM PDT 24 45108648 ps
T773 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1738753655 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 265173222 ps
T774 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.861265301 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 13434714 ps
T775 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2379603076 Apr 02 12:27:03 PM PDT 24 Apr 02 12:27:04 PM PDT 24 50041868 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.282185569 Apr 02 12:27:08 PM PDT 24 Apr 02 12:27:11 PM PDT 24 53360812 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.408252497 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 95975926 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1096475629 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 40168713 ps
T779 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.202569302 Apr 02 12:26:59 PM PDT 24 Apr 02 12:27:00 PM PDT 24 23036289 ps
T780 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2509765611 Apr 02 12:27:04 PM PDT 24 Apr 02 12:27:05 PM PDT 24 15390359 ps
T781 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2997330416 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 16675505 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2371250681 Apr 02 12:26:54 PM PDT 24 Apr 02 12:26:56 PM PDT 24 15650005 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3892659866 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:02 PM PDT 24 156387541 ps
T76 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1901284645 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 173135410 ps
T784 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1813274425 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 70583565 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1491620608 Apr 02 12:26:54 PM PDT 24 Apr 02 12:26:55 PM PDT 24 15733864 ps
T786 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1687419646 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:05 PM PDT 24 139920391 ps
T787 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4086194059 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 35333923 ps
T788 /workspace/coverage/cover_reg_top/26.gpio_intr_test.4003594110 Apr 02 12:27:12 PM PDT 24 Apr 02 12:27:14 PM PDT 24 22553875 ps
T789 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4213535265 Apr 02 12:27:04 PM PDT 24 Apr 02 12:27:05 PM PDT 24 17223341 ps
T790 /workspace/coverage/cover_reg_top/46.gpio_intr_test.165416144 Apr 02 12:28:22 PM PDT 24 Apr 02 12:28:23 PM PDT 24 46203251 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.309821621 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:03 PM PDT 24 52710631 ps
T77 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1496816403 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 15799939 ps
T792 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.26559522 Apr 02 12:27:06 PM PDT 24 Apr 02 12:27:13 PM PDT 24 38453406 ps
T793 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2735091252 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 52289404 ps
T794 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1564333923 Apr 02 12:26:51 PM PDT 24 Apr 02 12:26:53 PM PDT 24 94806597 ps
T795 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1295481019 Apr 02 12:26:59 PM PDT 24 Apr 02 12:26:59 PM PDT 24 28217969 ps
T796 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1180729155 Apr 02 12:26:43 PM PDT 24 Apr 02 12:26:45 PM PDT 24 471615881 ps
T797 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2087740539 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 14096864 ps
T798 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2070098491 Apr 02 12:27:17 PM PDT 24 Apr 02 12:27:18 PM PDT 24 335013844 ps
T799 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4158956560 Apr 02 12:26:55 PM PDT 24 Apr 02 12:26:56 PM PDT 24 16941621 ps
T800 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4171750759 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:03 PM PDT 24 508140056 ps
T78 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1610391485 Apr 02 12:26:55 PM PDT 24 Apr 02 12:26:56 PM PDT 24 17248728 ps
T79 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3368875869 Apr 02 12:27:22 PM PDT 24 Apr 02 12:27:22 PM PDT 24 20452014 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1997158028 Apr 02 12:26:51 PM PDT 24 Apr 02 12:26:52 PM PDT 24 84988307 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4130669713 Apr 02 12:26:53 PM PDT 24 Apr 02 12:26:56 PM PDT 24 157102997 ps
T803 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1190791091 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 33498171 ps
T804 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2437732054 Apr 02 12:26:57 PM PDT 24 Apr 02 12:26:58 PM PDT 24 41675121 ps
T805 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.878105794 Apr 02 12:27:06 PM PDT 24 Apr 02 12:27:07 PM PDT 24 29811188 ps
T806 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2743317130 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 173431821 ps
T807 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2599929676 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 102548135 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3798822405 Apr 02 12:26:59 PM PDT 24 Apr 02 12:27:01 PM PDT 24 500830964 ps
T809 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3813525809 Apr 02 12:27:14 PM PDT 24 Apr 02 12:27:15 PM PDT 24 17608861 ps
T80 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4023215584 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:03 PM PDT 24 48829221 ps
T810 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3852396023 Apr 02 12:26:54 PM PDT 24 Apr 02 12:26:55 PM PDT 24 16021050 ps
T811 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3001290884 Apr 02 12:27:54 PM PDT 24 Apr 02 12:27:55 PM PDT 24 99009873 ps
T812 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.100424102 Apr 02 12:27:08 PM PDT 24 Apr 02 12:27:10 PM PDT 24 60092580 ps
T813 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3776413662 Apr 02 12:26:51 PM PDT 24 Apr 02 12:26:52 PM PDT 24 46114020 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3631188075 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 113359757 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.597184821 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:04 PM PDT 24 473316220 ps
T816 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3681953822 Apr 02 12:26:56 PM PDT 24 Apr 02 12:26:57 PM PDT 24 91216337 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_intr_test.472544298 Apr 02 12:27:25 PM PDT 24 Apr 02 12:27:30 PM PDT 24 44460335 ps
T818 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1494004144 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 55949033 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.366142819 Apr 02 12:27:19 PM PDT 24 Apr 02 12:27:20 PM PDT 24 94657809 ps
T820 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.367091929 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 32573234 ps
T821 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1892940384 Apr 02 12:26:54 PM PDT 24 Apr 02 12:26:55 PM PDT 24 72890018 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1639893337 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 56851479 ps
T823 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.919321252 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 79761482 ps
T824 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3753219938 Apr 02 12:27:05 PM PDT 24 Apr 02 12:27:07 PM PDT 24 27766412 ps
T825 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1424348367 Apr 02 12:26:56 PM PDT 24 Apr 02 12:26:58 PM PDT 24 128001784 ps
T826 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1175353067 Apr 02 12:26:58 PM PDT 24 Apr 02 12:27:00 PM PDT 24 23456775 ps
T827 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1508423856 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 30992646 ps
T828 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1894709827 Apr 02 12:26:58 PM PDT 24 Apr 02 12:26:59 PM PDT 24 35439432 ps
T829 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3021044772 Apr 02 12:27:02 PM PDT 24 Apr 02 12:27:04 PM PDT 24 27329692 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_intr_test.111413800 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 21021857 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1892629769 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 122425515 ps
T831 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1026507180 Apr 02 12:27:03 PM PDT 24 Apr 02 12:27:04 PM PDT 24 16482908 ps
T832 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2225669518 Apr 02 12:26:55 PM PDT 24 Apr 02 12:26:56 PM PDT 24 47521715 ps
T833 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4255705148 Apr 02 12:27:09 PM PDT 24 Apr 02 12:27:11 PM PDT 24 19616059 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3603506852 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 65318539 ps
T835 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2261359962 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 56492962 ps
T836 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2892150680 Apr 02 12:27:04 PM PDT 24 Apr 02 12:27:07 PM PDT 24 14469935 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1260278857 Apr 02 12:26:52 PM PDT 24 Apr 02 12:26:53 PM PDT 24 28930886 ps
T82 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3176887281 Apr 02 12:26:55 PM PDT 24 Apr 02 12:26:56 PM PDT 24 41387773 ps
T838 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3272818722 Apr 02 12:25:58 PM PDT 24 Apr 02 12:25:59 PM PDT 24 55897119 ps
T839 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2509789991 Apr 02 12:26:44 PM PDT 24 Apr 02 12:26:46 PM PDT 24 202115842 ps
T840 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1584650139 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:08 PM PDT 24 508698920 ps
T841 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.357314804 Apr 02 12:26:34 PM PDT 24 Apr 02 12:26:35 PM PDT 24 39344269 ps
T842 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2570137129 Apr 02 12:25:51 PM PDT 24 Apr 02 12:25:52 PM PDT 24 192133149 ps
T843 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735898487 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:14 PM PDT 24 136343912 ps
T844 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2445348654 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:11 PM PDT 24 102467212 ps
T845 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.804708304 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 44536414 ps
T846 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2612924936 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:08 PM PDT 24 369234090 ps
T847 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2165966087 Apr 02 12:25:57 PM PDT 24 Apr 02 12:25:58 PM PDT 24 958979387 ps
T848 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.740072474 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:13 PM PDT 24 68819575 ps
T849 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.631087899 Apr 02 12:25:57 PM PDT 24 Apr 02 12:25:59 PM PDT 24 304904959 ps
T850 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1190086871 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:05 PM PDT 24 84816433 ps
T851 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.343266126 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:08 PM PDT 24 214495061 ps
T852 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3442345643 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:03 PM PDT 24 78176897 ps
T853 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.836798165 Apr 02 12:25:53 PM PDT 24 Apr 02 12:25:55 PM PDT 24 243555838 ps
T854 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1928360994 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 164385217 ps
T855 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3004424304 Apr 02 12:25:55 PM PDT 24 Apr 02 12:25:57 PM PDT 24 116444744 ps
T856 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1059911328 Apr 02 12:25:51 PM PDT 24 Apr 02 12:25:52 PM PDT 24 41739887 ps
T857 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.967821819 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 202897007 ps
T858 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2810155338 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 134752075 ps
T859 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945845651 Apr 02 12:25:51 PM PDT 24 Apr 02 12:25:52 PM PDT 24 78389996 ps
T860 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3790877481 Apr 02 12:25:46 PM PDT 24 Apr 02 12:25:47 PM PDT 24 150945326 ps
T861 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1792664906 Apr 02 12:25:58 PM PDT 24 Apr 02 12:26:00 PM PDT 24 138924956 ps
T862 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2708275698 Apr 02 12:25:57 PM PDT 24 Apr 02 12:25:58 PM PDT 24 117865396 ps
T863 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625119976 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:08 PM PDT 24 44823715 ps
T864 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1233303463 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 84127068 ps
T865 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.553884117 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:03 PM PDT 24 82490359 ps
T866 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.920844569 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:03 PM PDT 24 89415191 ps
T867 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3691781743 Apr 02 12:25:59 PM PDT 24 Apr 02 12:26:00 PM PDT 24 58711797 ps
T868 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.252733284 Apr 02 12:25:58 PM PDT 24 Apr 02 12:26:00 PM PDT 24 163782736 ps
T869 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.775993546 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:02 PM PDT 24 42813362 ps
T870 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1726855491 Apr 02 12:25:51 PM PDT 24 Apr 02 12:25:53 PM PDT 24 54869060 ps
T871 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.433945068 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:04 PM PDT 24 66802234 ps
T872 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.166398863 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:03 PM PDT 24 41905831 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1042060542 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 56205687 ps
T874 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4052801314 Apr 02 12:25:51 PM PDT 24 Apr 02 12:25:52 PM PDT 24 158644211 ps
T875 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2030119289 Apr 02 12:25:54 PM PDT 24 Apr 02 12:25:56 PM PDT 24 96802683 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807703009 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:13 PM PDT 24 211429266 ps
T877 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006312174 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:07 PM PDT 24 46055543 ps
T878 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3810020428 Apr 02 12:25:55 PM PDT 24 Apr 02 12:25:56 PM PDT 24 554152471 ps
T879 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545159837 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:14 PM PDT 24 83009371 ps
T880 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.589390122 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:13 PM PDT 24 62361563 ps
T881 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511664175 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:13 PM PDT 24 139341128 ps
T882 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923001223 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:04 PM PDT 24 135317444 ps
T883 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1187302106 Apr 02 12:26:20 PM PDT 24 Apr 02 12:26:21 PM PDT 24 26733554 ps
T884 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1177347611 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 135172263 ps
T885 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2424169998 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:06 PM PDT 24 37854591 ps
T886 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3794625743 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 46423015 ps
T887 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2212541534 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:09 PM PDT 24 101739264 ps
T888 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330195489 Apr 02 12:25:55 PM PDT 24 Apr 02 12:25:56 PM PDT 24 90646138 ps
T889 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1482313533 Apr 02 12:25:58 PM PDT 24 Apr 02 12:26:00 PM PDT 24 88268364 ps
T890 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.596618354 Apr 02 12:25:57 PM PDT 24 Apr 02 12:25:58 PM PDT 24 257255712 ps
T891 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.888325320 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:07 PM PDT 24 77876511 ps
T892 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4275175886 Apr 02 12:25:59 PM PDT 24 Apr 02 12:26:00 PM PDT 24 74012350 ps
T893 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4157315495 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:08 PM PDT 24 624917270 ps
T894 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3416340146 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 62333520 ps
T895 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2719188378 Apr 02 12:25:54 PM PDT 24 Apr 02 12:25:56 PM PDT 24 156199095 ps
T896 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929850709 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 38070302 ps
T897 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.646017167 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:14 PM PDT 24 185819329 ps
T898 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3662315702 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:02 PM PDT 24 322410597 ps
T899 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388759395 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 152438048 ps
T900 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.565452899 Apr 02 12:25:53 PM PDT 24 Apr 02 12:25:55 PM PDT 24 396478923 ps
T901 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.567522674 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 48740657 ps
T902 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761725640 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 84715479 ps
T903 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2710320057 Apr 02 12:25:59 PM PDT 24 Apr 02 12:26:00 PM PDT 24 134405744 ps
T904 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527440499 Apr 02 12:26:00 PM PDT 24 Apr 02 12:26:01 PM PDT 24 230613164 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4123202071 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 176247338 ps
T906 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912811401 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 369541305 ps
T907 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.329251912 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 26190923 ps
T908 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.514044367 Apr 02 12:25:56 PM PDT 24 Apr 02 12:25:58 PM PDT 24 112071410 ps
T909 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60791811 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:04 PM PDT 24 55735907 ps
T910 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3978614809 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 54613947 ps
T911 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4275140772 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:06 PM PDT 24 72556565 ps
T912 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765457000 Apr 02 12:25:43 PM PDT 24 Apr 02 12:25:45 PM PDT 24 75545064 ps
T913 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1491078779 Apr 02 12:26:00 PM PDT 24 Apr 02 12:26:01 PM PDT 24 80093988 ps
T914 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2972631406 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:03 PM PDT 24 52204011 ps
T915 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3550862580 Apr 02 12:26:00 PM PDT 24 Apr 02 12:26:01 PM PDT 24 112587683 ps
T916 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.957323013 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 77763092 ps
T917 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4274605085 Apr 02 12:26:02 PM PDT 24 Apr 02 12:26:03 PM PDT 24 302032562 ps
T918 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946435100 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 93086160 ps
T919 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1747329527 Apr 02 12:25:55 PM PDT 24 Apr 02 12:25:56 PM PDT 24 89003877 ps
T920 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1428609137 Apr 02 12:25:49 PM PDT 24 Apr 02 12:25:51 PM PDT 24 75135809 ps
T921 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1971630612 Apr 02 12:25:59 PM PDT 24 Apr 02 12:26:00 PM PDT 24 177008367 ps
T922 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3272024928 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 269907807 ps
T923 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2559356213 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 46119960 ps
T924 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.270304310 Apr 02 12:25:53 PM PDT 24 Apr 02 12:25:55 PM PDT 24 420683725 ps
T925 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2268458602 Apr 02 12:25:58 PM PDT 24 Apr 02 12:25:59 PM PDT 24 73836306 ps
T926 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652895979 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:07 PM PDT 24 48047431 ps
T927 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3577639590 Apr 02 12:26:03 PM PDT 24 Apr 02 12:26:04 PM PDT 24 218399142 ps
T928 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.679483501 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 123188943 ps
T929 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4076660633 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:02 PM PDT 24 40085809 ps
T930 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2221483922 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:06 PM PDT 24 91208649 ps
T931 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1095459889 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 34437474 ps
T932 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1699097430 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:06 PM PDT 24 93185587 ps
T933 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1544191299 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:03 PM PDT 24 43268153 ps
T934 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3056996779 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:11 PM PDT 24 1051129492 ps
T935 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2443001902 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:05 PM PDT 24 34632751 ps
T936 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1060856571 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 46437845 ps
T937 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2583945577 Apr 02 12:25:54 PM PDT 24 Apr 02 12:25:55 PM PDT 24 334036205 ps

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.349823016
Short name T25
Test name
Test status
Simulation time 198514041 ps
CPU time 4.71 seconds
Started Apr 02 12:51:38 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 197792 kb
Host smart-b3bed336-b4fd-46f1-9d82-30e040939aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349823016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.349823016
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3607383509
Short name T34
Test name
Test status
Simulation time 73272141 ps
CPU time 3.02 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:34 PM PDT 24
Peak memory 198048 kb
Host smart-6542f6c8-b9b4-4f87-bcc1-dd44665dfcd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607383509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3607383509
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2580319086
Short name T11
Test name
Test status
Simulation time 15554009157 ps
CPU time 305.65 seconds
Started Apr 02 12:50:32 PM PDT 24
Finished Apr 02 12:55:37 PM PDT 24
Peak memory 198232 kb
Host smart-ef994e98-4cba-4be5-9e6b-5d688a1ed822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2580319086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2580319086
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2457718369
Short name T27
Test name
Test status
Simulation time 70364129 ps
CPU time 0.82 seconds
Started Apr 02 12:49:59 PM PDT 24
Finished Apr 02 12:50:00 PM PDT 24
Peak memory 213756 kb
Host smart-1bba6cd8-d18b-4578-b005-be3c872682d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457718369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2457718369
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.155701950
Short name T68
Test name
Test status
Simulation time 146589241 ps
CPU time 0.88 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 196284 kb
Host smart-b87de238-dcec-4408-a902-25bb261695c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155701950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.155701950
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2050883309
Short name T1
Test name
Test status
Simulation time 461059652 ps
CPU time 5.72 seconds
Started Apr 02 12:50:54 PM PDT 24
Finished Apr 02 12:51:01 PM PDT 24
Peak memory 196328 kb
Host smart-acdc57e8-5ab7-42db-81b7-22800f96df65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050883309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2050883309
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.903505256
Short name T41
Test name
Test status
Simulation time 355447957 ps
CPU time 1.67 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 197664 kb
Host smart-13c7ed45-7863-4949-a400-06b5b2a99684
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903505256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.903505256
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3839332555
Short name T202
Test name
Test status
Simulation time 17394928 ps
CPU time 0.6 seconds
Started Apr 02 12:50:33 PM PDT 24
Finished Apr 02 12:50:34 PM PDT 24
Peak memory 194652 kb
Host smart-cbf5185c-cef4-4185-bb49-fd218d36c339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839332555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3839332555
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.457764418
Short name T67
Test name
Test status
Simulation time 37494707 ps
CPU time 0.79 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 195756 kb
Host smart-3d24479e-7adb-4dac-ad45-7dda1a8e0b1d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457764418 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.457764418
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2094988612
Short name T48
Test name
Test status
Simulation time 100912542 ps
CPU time 1.32 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197584 kb
Host smart-d228fec9-39ca-4dd4-803d-6125dfd227a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094988612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2094988612
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.699006026
Short name T75
Test name
Test status
Simulation time 58592122 ps
CPU time 0.86 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 195840 kb
Host smart-099b2763-d17f-4e0d-828b-930ba4a52fbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699006026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.699006026
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1564333923
Short name T794
Test name
Test status
Simulation time 94806597 ps
CPU time 1.58 seconds
Started Apr 02 12:26:51 PM PDT 24
Finished Apr 02 12:26:53 PM PDT 24
Peak memory 197564 kb
Host smart-102d9bfe-1f3b-4385-96ee-8ecffcc5ae73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564333923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1564333923
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1496816403
Short name T77
Test name
Test status
Simulation time 15799939 ps
CPU time 0.63 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 195140 kb
Host smart-03c5a41c-9d81-4922-8268-451fa4bab19e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496816403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1496816403
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.157815290
Short name T725
Test name
Test status
Simulation time 54480882 ps
CPU time 0.8 seconds
Started Apr 02 12:26:52 PM PDT 24
Finished Apr 02 12:26:53 PM PDT 24
Peak memory 197536 kb
Host smart-dd426665-6da6-48ed-9105-ce12a5f1a441
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157815290 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.157815290
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1997158028
Short name T801
Test name
Test status
Simulation time 84988307 ps
CPU time 0.58 seconds
Started Apr 02 12:26:51 PM PDT 24
Finished Apr 02 12:26:52 PM PDT 24
Peak memory 193012 kb
Host smart-ec03ed31-f4c4-42e6-b2d5-2fb25bf497f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997158028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1997158028
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1295481019
Short name T795
Test name
Test status
Simulation time 28217969 ps
CPU time 0.6 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 193976 kb
Host smart-53c3b35f-3ed5-484b-81e7-9d2bcd32c3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295481019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1295481019
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.919321252
Short name T823
Test name
Test status
Simulation time 79761482 ps
CPU time 0.89 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 196580 kb
Host smart-5bcd044a-ed40-4306-ba3e-98242507eda4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919321252 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.919321252
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.339301721
Short name T728
Test name
Test status
Simulation time 677221952 ps
CPU time 2.71 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 197728 kb
Host smart-2416d6ba-a866-4474-99f3-3a746bdb73b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339301721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.339301721
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1180729155
Short name T796
Test name
Test status
Simulation time 471615881 ps
CPU time 1.12 seconds
Started Apr 02 12:26:43 PM PDT 24
Finished Apr 02 12:26:45 PM PDT 24
Peak memory 197620 kb
Host smart-ce143f59-3025-4251-8e3d-0e5edd23fcb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180729155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1180729155
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1892629769
Short name T81
Test name
Test status
Simulation time 122425515 ps
CPU time 0.7 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 194124 kb
Host smart-4bd6e9d0-0d59-4181-86bc-c2e6258786df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892629769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1892629769
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.905528280
Short name T64
Test name
Test status
Simulation time 113517149 ps
CPU time 2.04 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 196360 kb
Host smart-f0d31198-09ac-475d-ae16-8da342285766
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905528280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.905528280
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4023215584
Short name T80
Test name
Test status
Simulation time 48829221 ps
CPU time 0.65 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 194516 kb
Host smart-862f5ca3-b67f-4b86-bb88-261feab7d332
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023215584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4023215584
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.629961842
Short name T753
Test name
Test status
Simulation time 21262337 ps
CPU time 0.57 seconds
Started Apr 02 12:26:49 PM PDT 24
Finished Apr 02 12:26:50 PM PDT 24
Peak memory 192936 kb
Host smart-80a14a73-1279-4a47-bcea-7c5f2a4662d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629961842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.629961842
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1841136483
Short name T718
Test name
Test status
Simulation time 51890839 ps
CPU time 0.59 seconds
Started Apr 02 12:26:47 PM PDT 24
Finished Apr 02 12:26:47 PM PDT 24
Peak memory 193928 kb
Host smart-e33b781a-4b4e-41fa-a602-14ed98830ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841136483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1841136483
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4184024526
Short name T730
Test name
Test status
Simulation time 45948447 ps
CPU time 2.32 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:57 PM PDT 24
Peak memory 198020 kb
Host smart-867b132a-4955-4924-a824-e971da146674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184024526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4184024526
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4039218322
Short name T38
Test name
Test status
Simulation time 318541227 ps
CPU time 1.13 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 197588 kb
Host smart-2c0abdb2-ec01-49e6-a9bc-bea739a5c730
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039218322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4039218322
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3753219938
Short name T824
Test name
Test status
Simulation time 27766412 ps
CPU time 1.01 seconds
Started Apr 02 12:27:05 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 197548 kb
Host smart-82d789ad-68a0-4810-93ae-f4aeebdd079c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753219938 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3753219938
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.100424102
Short name T812
Test name
Test status
Simulation time 60092580 ps
CPU time 0.56 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:10 PM PDT 24
Peak memory 194280 kb
Host smart-bc178ab9-4b6a-4fe0-93cb-de588335b0e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100424102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.100424102
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1894709827
Short name T828
Test name
Test status
Simulation time 35439432 ps
CPU time 0.61 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 193384 kb
Host smart-1055e961-ca89-474b-9937-86cdf7d0e3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894709827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1894709827
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1921385584
Short name T762
Test name
Test status
Simulation time 54529198 ps
CPU time 0.77 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 196544 kb
Host smart-6348a2e9-29bd-49cf-bf7f-db32d681c20e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921385584 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1921385584
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.597184821
Short name T815
Test name
Test status
Simulation time 473316220 ps
CPU time 2.34 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197664 kb
Host smart-d585be6d-7091-4662-9d75-c4e09c44e970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597184821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.597184821
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1687419646
Short name T786
Test name
Test status
Simulation time 139920391 ps
CPU time 1.41 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 197672 kb
Host smart-7a379a84-5b4a-4a97-837c-fa2f01a29f74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687419646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1687419646
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3852396023
Short name T810
Test name
Test status
Simulation time 16021050 ps
CPU time 0.68 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:55 PM PDT 24
Peak memory 197456 kb
Host smart-d1546e62-73fe-4894-ac40-84e7f57e1429
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852396023 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3852396023
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3838535543
Short name T88
Test name
Test status
Simulation time 14431983 ps
CPU time 0.59 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 195116 kb
Host smart-1f92b642-2cdf-443e-9694-4ef96a48568c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838535543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3838535543
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.644056042
Short name T748
Test name
Test status
Simulation time 47394398 ps
CPU time 0.6 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 193332 kb
Host smart-9406551b-5160-43f2-a5f4-bbb3147ebc5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644056042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.644056042
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1461119044
Short name T73
Test name
Test status
Simulation time 38475950 ps
CPU time 0.6 seconds
Started Apr 02 12:27:09 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 194328 kb
Host smart-0d5305da-bdba-4e0e-be1a-57c18b3b2ca6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461119044 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1461119044
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1424348367
Short name T825
Test name
Test status
Simulation time 128001784 ps
CPU time 1.76 seconds
Started Apr 02 12:26:56 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 197652 kb
Host smart-4f06019a-d6ee-44a0-89b6-e2957dbe3f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424348367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1424348367
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4086129590
Short name T40
Test name
Test status
Simulation time 95187542 ps
CPU time 0.95 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 196764 kb
Host smart-bb877ebe-98c6-4f32-ad41-84bbb4537dcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086129590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4086129590
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2058940716
Short name T729
Test name
Test status
Simulation time 70239948 ps
CPU time 0.72 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 197172 kb
Host smart-584f319b-712f-42fc-bbdc-b929faf11b12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058940716 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2058940716
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3631188075
Short name T814
Test name
Test status
Simulation time 113359757 ps
CPU time 0.63 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 194412 kb
Host smart-261efb0b-b098-4094-8a19-14964a8356b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631188075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3631188075
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1326903464
Short name T772
Test name
Test status
Simulation time 45108648 ps
CPU time 0.6 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 193980 kb
Host smart-4ef172e8-bcc6-45b2-a9e4-c7f839e22586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326903464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1326903464
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2783412849
Short name T70
Test name
Test status
Simulation time 82745316 ps
CPU time 0.83 seconds
Started Apr 02 12:26:48 PM PDT 24
Finished Apr 02 12:26:49 PM PDT 24
Peak memory 195976 kb
Host smart-6ed7266c-9550-4a70-97ad-a734af8b0988
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783412849 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2783412849
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2308957571
Short name T709
Test name
Test status
Simulation time 265388432 ps
CPU time 1.94 seconds
Started Apr 02 12:26:53 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 197676 kb
Host smart-000515b5-b6c3-467d-b67d-0ff5a25e14f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308957571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2308957571
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2678005596
Short name T731
Test name
Test status
Simulation time 137908590 ps
CPU time 0.9 seconds
Started Apr 02 12:26:53 PM PDT 24
Finished Apr 02 12:26:54 PM PDT 24
Peak memory 196844 kb
Host smart-0b5cce87-2161-47c3-ae88-51b8694b3c8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678005596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2678005596
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.282185569
Short name T776
Test name
Test status
Simulation time 53360812 ps
CPU time 0.88 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 197548 kb
Host smart-5ef50960-5a54-487c-a831-7a76b6aaf6a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282185569 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.282185569
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3021044772
Short name T829
Test name
Test status
Simulation time 27329692 ps
CPU time 0.59 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 194308 kb
Host smart-0c44474b-4de7-470a-94e6-60ff8a54ac72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021044772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3021044772
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2157290501
Short name T764
Test name
Test status
Simulation time 56062532 ps
CPU time 0.6 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 193320 kb
Host smart-dc49dad6-5367-4bf6-b70a-11ab33a91e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157290501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2157290501
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2225669518
Short name T832
Test name
Test status
Simulation time 47521715 ps
CPU time 0.73 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 195656 kb
Host smart-c9e491c3-8126-40ac-afc0-24307567c2e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225669518 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2225669518
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.593229433
Short name T715
Test name
Test status
Simulation time 177641483 ps
CPU time 3 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197656 kb
Host smart-35c56c3b-472d-44d0-a066-ca54db9ad9be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593229433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.593229433
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2661063443
Short name T732
Test name
Test status
Simulation time 55839406 ps
CPU time 0.86 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 196760 kb
Host smart-78c7a2a1-7990-4246-9cbf-a7a92cbc2fd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661063443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2661063443
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1292750718
Short name T738
Test name
Test status
Simulation time 31873248 ps
CPU time 0.8 seconds
Started Apr 02 12:26:56 PM PDT 24
Finished Apr 02 12:26:57 PM PDT 24
Peak memory 197492 kb
Host smart-25daab3e-7eca-4520-9ecb-8a6886c4140b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292750718 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1292750718
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2599929676
Short name T807
Test name
Test status
Simulation time 102548135 ps
CPU time 0.61 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 194536 kb
Host smart-3dc9093b-6d31-40ac-9774-339d06d94f6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599929676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2599929676
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2997330416
Short name T781
Test name
Test status
Simulation time 16675505 ps
CPU time 0.59 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193404 kb
Host smart-01d6dd63-3e4a-48d6-8366-7527c199f223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997330416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2997330416
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.856143580
Short name T763
Test name
Test status
Simulation time 18715640 ps
CPU time 0.79 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 195892 kb
Host smart-174cbc25-be64-463a-80de-eb86b2caf202
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856143580 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.856143580
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1175353067
Short name T826
Test name
Test status
Simulation time 23456775 ps
CPU time 1.2 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197612 kb
Host smart-f92a5667-c2cc-411a-8fc9-7dd8db8f1578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175353067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1175353067
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4086194059
Short name T787
Test name
Test status
Simulation time 35333923 ps
CPU time 0.91 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 197568 kb
Host smart-317402cd-9c38-4ebe-8990-89423edeb9a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086194059 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.4086194059
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4213535265
Short name T789
Test name
Test status
Simulation time 17223341 ps
CPU time 0.65 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 194500 kb
Host smart-736deda1-da35-4093-bb8a-953f270b9dc4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213535265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4213535265
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3203888907
Short name T770
Test name
Test status
Simulation time 34487547 ps
CPU time 0.59 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 193332 kb
Host smart-0d011fc3-30dd-4c58-b2dc-e3f2214ca189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203888907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3203888907
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1593148809
Short name T85
Test name
Test status
Simulation time 95674269 ps
CPU time 0.75 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 195792 kb
Host smart-4c4c80e3-1179-4364-b920-17828aa9edf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593148809 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1593148809
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.309821621
Short name T791
Test name
Test status
Simulation time 52710631 ps
CPU time 2.64 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 197624 kb
Host smart-4d9bfc33-0763-4871-8f25-d82680a13698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309821621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.309821621
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3603506852
Short name T834
Test name
Test status
Simulation time 65318539 ps
CPU time 0.7 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 197492 kb
Host smart-875e575a-6896-4a29-9370-a6c01fe5dc4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603506852 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3603506852
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.305807226
Short name T69
Test name
Test status
Simulation time 13038844 ps
CPU time 0.55 seconds
Started Apr 02 12:27:06 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 192900 kb
Host smart-ed8b271d-ba62-4195-84eb-a5926cc1251d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305807226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.305807226
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3848165825
Short name T723
Test name
Test status
Simulation time 12062052 ps
CPU time 0.62 seconds
Started Apr 02 12:27:03 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 193300 kb
Host smart-e91a21c3-e36d-44fe-b1c7-9c013aad4e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848165825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3848165825
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.329481004
Short name T758
Test name
Test status
Simulation time 69510434 ps
CPU time 0.62 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 194256 kb
Host smart-44bd10f6-21e7-424d-bf49-1d12a7ccf97f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329481004 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.329481004
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.367091929
Short name T820
Test name
Test status
Simulation time 32573234 ps
CPU time 1.57 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 197612 kb
Host smart-7ddbe5d7-a1f0-4609-b7ff-5ff47398c9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367091929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.367091929
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2003239133
Short name T747
Test name
Test status
Simulation time 73234162 ps
CPU time 1.1 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 197636 kb
Host smart-bed35652-55d5-4098-a059-c0e5b6ece24b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003239133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2003239133
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3938395725
Short name T746
Test name
Test status
Simulation time 20659158 ps
CPU time 0.99 seconds
Started Apr 02 12:27:05 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 197600 kb
Host smart-75ecc23b-5e51-4d2f-87f9-0af59baf3102
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938395725 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3938395725
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.861265301
Short name T774
Test name
Test status
Simulation time 13434714 ps
CPU time 0.62 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 194556 kb
Host smart-fec7ef84-3d36-47f5-98c5-871cb7ea80dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861265301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.861265301
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1975736887
Short name T766
Test name
Test status
Simulation time 16104624 ps
CPU time 0.58 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 193312 kb
Host smart-9d003c20-f6e7-4576-9aac-7b56a513f264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975736887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1975736887
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4255705148
Short name T833
Test name
Test status
Simulation time 19616059 ps
CPU time 0.62 seconds
Started Apr 02 12:27:09 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 194964 kb
Host smart-0d9e63b4-3898-415e-ab46-e238fe489854
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255705148 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4255705148
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1892940384
Short name T821
Test name
Test status
Simulation time 72890018 ps
CPU time 1.07 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:55 PM PDT 24
Peak memory 197436 kb
Host smart-e6224830-d860-4dfa-9963-c0dd61a4a92a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892940384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1892940384
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2070098491
Short name T798
Test name
Test status
Simulation time 335013844 ps
CPU time 1.13 seconds
Started Apr 02 12:27:17 PM PDT 24
Finished Apr 02 12:27:18 PM PDT 24
Peak memory 197680 kb
Host smart-a5e64ea3-f216-4d91-8c3b-b0b7aeeb3bc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070098491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2070098491
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1534276017
Short name T769
Test name
Test status
Simulation time 141442953 ps
CPU time 1.02 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197432 kb
Host smart-82a028d6-8b12-40c0-ad5b-ad363594b1b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534276017 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1534276017
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1096475629
Short name T778
Test name
Test status
Simulation time 40168713 ps
CPU time 0.61 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 195240 kb
Host smart-1bf9de7a-b0a0-4c8f-98fa-a0f8beeea249
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096475629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1096475629
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2509765611
Short name T780
Test name
Test status
Simulation time 15390359 ps
CPU time 0.61 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 193984 kb
Host smart-dd87586d-fa54-4b8e-8919-cc3a8d88a416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509765611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2509765611
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.366142819
Short name T819
Test name
Test status
Simulation time 94657809 ps
CPU time 0.71 seconds
Started Apr 02 12:27:19 PM PDT 24
Finished Apr 02 12:27:20 PM PDT 24
Peak memory 195084 kb
Host smart-16be2148-f472-4b4d-b519-1ba21dc530df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366142819 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.366142819
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.523463163
Short name T741
Test name
Test status
Simulation time 73132182 ps
CPU time 1.64 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:08 PM PDT 24
Peak memory 197680 kb
Host smart-62414c4c-b983-41be-a428-c5a0865bda9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523463163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.523463163
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3336079218
Short name T739
Test name
Test status
Simulation time 125922785 ps
CPU time 1.45 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 197632 kb
Host smart-1cd76a95-62ea-46dd-a112-a77942551936
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336079218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3336079218
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3681203073
Short name T737
Test name
Test status
Simulation time 146262470 ps
CPU time 0.91 seconds
Started Apr 02 12:27:09 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 197552 kb
Host smart-a44cbe62-b843-4731-9f13-baf3afc6f70b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681203073 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3681203073
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1709704060
Short name T74
Test name
Test status
Simulation time 22118732 ps
CPU time 0.58 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 194460 kb
Host smart-ddea2f73-57c2-4ec8-a113-cc8b047aaf4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709704060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1709704060
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.472544298
Short name T817
Test name
Test status
Simulation time 44460335 ps
CPU time 0.6 seconds
Started Apr 02 12:27:25 PM PDT 24
Finished Apr 02 12:27:30 PM PDT 24
Peak memory 193272 kb
Host smart-af775042-b888-422c-9863-0798c517cb82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472544298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.472544298
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2622719003
Short name T87
Test name
Test status
Simulation time 21623546 ps
CPU time 0.82 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:06 PM PDT 24
Peak memory 195992 kb
Host smart-67bbbfb8-829f-47f1-9f2a-df2f8f98bf51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622719003 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2622719003
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1203776775
Short name T726
Test name
Test status
Simulation time 965557342 ps
CPU time 2.25 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 197640 kb
Host smart-82485efe-9a3f-4215-a04c-6f9205031d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203776775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1203776775
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.408252497
Short name T777
Test name
Test status
Simulation time 95975926 ps
CPU time 1.42 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197564 kb
Host smart-c3ef4bde-ef3f-4d7c-b669-f1995042f823
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408252497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.408252497
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3176887281
Short name T82
Test name
Test status
Simulation time 41387773 ps
CPU time 0.92 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 195716 kb
Host smart-108c5345-3996-4049-bbe4-024b7ededc44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176887281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3176887281
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3798822405
Short name T808
Test name
Test status
Simulation time 500830964 ps
CPU time 1.52 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 196212 kb
Host smart-2adefe32-b334-480e-93b0-7977434967a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798822405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3798822405
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1610391485
Short name T78
Test name
Test status
Simulation time 17248728 ps
CPU time 0.63 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 194132 kb
Host smart-4273f4d4-a39b-4ce0-bc43-1811c0f64d82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610391485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1610391485
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3776413662
Short name T813
Test name
Test status
Simulation time 46114020 ps
CPU time 0.76 seconds
Started Apr 02 12:26:51 PM PDT 24
Finished Apr 02 12:26:52 PM PDT 24
Peak memory 197280 kb
Host smart-753f805c-3fb9-49e2-8b3f-be4d75cdafc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776413662 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3776413662
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1491620608
Short name T785
Test name
Test status
Simulation time 15733864 ps
CPU time 0.61 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:55 PM PDT 24
Peak memory 195044 kb
Host smart-5b530210-0329-435e-934e-d8a72a24a4a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491620608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1491620608
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2371250681
Short name T782
Test name
Test status
Simulation time 15650005 ps
CPU time 0.6 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 193328 kb
Host smart-44b35cf1-abec-46c5-b3bb-97ea32323d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371250681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2371250681
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2162521653
Short name T86
Test name
Test status
Simulation time 139442339 ps
CPU time 0.79 seconds
Started Apr 02 12:26:56 PM PDT 24
Finished Apr 02 12:26:57 PM PDT 24
Peak memory 195904 kb
Host smart-3f058240-6cbb-4586-95d8-6995fa3a2fb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162521653 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2162521653
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4130669713
Short name T802
Test name
Test status
Simulation time 157102997 ps
CPU time 2.27 seconds
Started Apr 02 12:26:53 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 197632 kb
Host smart-bfd217e6-98f1-4352-92d6-cf4ce6466e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130669713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4130669713
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1780486921
Short name T765
Test name
Test status
Simulation time 359721535 ps
CPU time 0.84 seconds
Started Apr 02 12:26:54 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 197468 kb
Host smart-ffad13c7-9aca-4c6e-9c33-3a68a2ddd6d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780486921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1780486921
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2892150680
Short name T836
Test name
Test status
Simulation time 14469935 ps
CPU time 0.59 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 194000 kb
Host smart-e4bc6808-7804-4642-ab4b-5bebbc57103c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892150680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2892150680
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3458173952
Short name T720
Test name
Test status
Simulation time 19856534 ps
CPU time 0.59 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 193340 kb
Host smart-61949bde-a70b-4fc9-ab56-005b9ccf7190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458173952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3458173952
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1813274425
Short name T784
Test name
Test status
Simulation time 70583565 ps
CPU time 0.64 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193360 kb
Host smart-65b20166-eefd-4da4-ad1b-0aeeae5ce73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813274425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1813274425
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1190791091
Short name T803
Test name
Test status
Simulation time 33498171 ps
CPU time 0.59 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 193940 kb
Host smart-362525f8-0252-4084-b826-cf75ca52f121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190791091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1190791091
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2912299858
Short name T734
Test name
Test status
Simulation time 14370775 ps
CPU time 0.59 seconds
Started Apr 02 12:27:09 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 194036 kb
Host smart-84039c1e-d26e-4936-91e0-b1ac7a96cb6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912299858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2912299858
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.746409136
Short name T761
Test name
Test status
Simulation time 59014400 ps
CPU time 0.56 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 193860 kb
Host smart-1b9f1b96-3a29-4036-9d80-7150b9563e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746409136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.746409136
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4003594110
Short name T788
Test name
Test status
Simulation time 22553875 ps
CPU time 0.55 seconds
Started Apr 02 12:27:12 PM PDT 24
Finished Apr 02 12:27:14 PM PDT 24
Peak memory 193256 kb
Host smart-97f27c2b-edee-4f75-9da7-d1a9356d8805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003594110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4003594110
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2735091252
Short name T793
Test name
Test status
Simulation time 52289404 ps
CPU time 0.62 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193340 kb
Host smart-af4a83b8-f306-4a44-b530-44d457ba4f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735091252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2735091252
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.4043473770
Short name T727
Test name
Test status
Simulation time 30855932 ps
CPU time 0.62 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193432 kb
Host smart-ffe46c1c-194c-4195-ac69-3b93c7b62d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043473770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.4043473770
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3788613394
Short name T756
Test name
Test status
Simulation time 57550183 ps
CPU time 0.61 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193272 kb
Host smart-13c15998-8cb0-4448-ac61-09ff5d63d892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788613394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3788613394
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1901284645
Short name T76
Test name
Test status
Simulation time 173135410 ps
CPU time 0.78 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 195636 kb
Host smart-04c4bc55-6ede-4edf-bec9-2489d805aa06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901284645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1901284645
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.493557753
Short name T89
Test name
Test status
Simulation time 1028276986 ps
CPU time 3.26 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 196508 kb
Host smart-0497eb6d-b7ba-49b9-9b6c-bc182c5a30d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493557753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.493557753
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1639893337
Short name T822
Test name
Test status
Simulation time 56851479 ps
CPU time 0.66 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 195304 kb
Host smart-cbf93053-35e7-4cb2-8594-dd8e8c1f5bb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639893337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1639893337
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.401151572
Short name T754
Test name
Test status
Simulation time 88650809 ps
CPU time 1.72 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 197684 kb
Host smart-887cc6dd-36dd-4cf6-ac33-b37d03f85fa5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401151572 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.401151572
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1939545772
Short name T745
Test name
Test status
Simulation time 168349381 ps
CPU time 0.64 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 194004 kb
Host smart-158e24fb-c5ec-4b7d-b645-e603b7740088
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939545772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1939545772
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1260278857
Short name T837
Test name
Test status
Simulation time 28930886 ps
CPU time 0.6 seconds
Started Apr 02 12:26:52 PM PDT 24
Finished Apr 02 12:26:53 PM PDT 24
Peak memory 193984 kb
Host smart-7ad219c1-b856-4a41-b002-cf487dd51787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260278857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1260278857
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1845946182
Short name T768
Test name
Test status
Simulation time 27972468 ps
CPU time 0.66 seconds
Started Apr 02 12:26:48 PM PDT 24
Finished Apr 02 12:26:49 PM PDT 24
Peak memory 195124 kb
Host smart-0e48060f-54ea-4d48-8879-04b73f7e0c76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845946182 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1845946182
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.749124985
Short name T759
Test name
Test status
Simulation time 23702062 ps
CPU time 1.33 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 197680 kb
Host smart-8c705f20-3713-4178-867c-f503463c1733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749124985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.749124985
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3892659866
Short name T783
Test name
Test status
Simulation time 156387541 ps
CPU time 1.09 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 197180 kb
Host smart-47d6cc5a-db47-4117-9f0f-fc24cdde4526
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892659866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3892659866
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.326809595
Short name T708
Test name
Test status
Simulation time 17047600 ps
CPU time 0.58 seconds
Started Apr 02 12:27:09 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 193252 kb
Host smart-d90e663d-fdda-4406-a971-d799da9dcc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326809595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.326809595
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2261359962
Short name T835
Test name
Test status
Simulation time 56492962 ps
CPU time 0.6 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 193980 kb
Host smart-3f9715b7-f6d8-4d93-8bd2-66052b3ced7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261359962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2261359962
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1931074102
Short name T736
Test name
Test status
Simulation time 47665190 ps
CPU time 0.56 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 194020 kb
Host smart-8a17233b-9c9a-4679-8f4d-509c7e6eb861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931074102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1931074102
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2743317130
Short name T806
Test name
Test status
Simulation time 173431821 ps
CPU time 0.58 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 193300 kb
Host smart-b0c242a1-0c17-400d-a6cb-a84311025268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743317130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2743317130
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3952807603
Short name T752
Test name
Test status
Simulation time 43632755 ps
CPU time 0.61 seconds
Started Apr 02 12:27:10 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 193284 kb
Host smart-66a18de8-33c3-48e7-9adb-1a98933b2b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952807603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3952807603
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3681953822
Short name T816
Test name
Test status
Simulation time 91216337 ps
CPU time 0.6 seconds
Started Apr 02 12:26:56 PM PDT 24
Finished Apr 02 12:26:57 PM PDT 24
Peak memory 193360 kb
Host smart-d876699a-04ee-4f6a-a1b7-f24cb31b44cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681953822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3681953822
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2437732054
Short name T804
Test name
Test status
Simulation time 41675121 ps
CPU time 0.59 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 193256 kb
Host smart-12e3e191-79e6-460a-a19b-e86eb6ea3dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437732054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2437732054
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2628716393
Short name T713
Test name
Test status
Simulation time 77356069 ps
CPU time 0.62 seconds
Started Apr 02 12:27:41 PM PDT 24
Finished Apr 02 12:27:42 PM PDT 24
Peak memory 193480 kb
Host smart-d018efb2-dc82-4a47-920a-5ad5bc14cb85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628716393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2628716393
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2526459563
Short name T735
Test name
Test status
Simulation time 77147855 ps
CPU time 0.6 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193140 kb
Host smart-a35b4063-49ba-4d34-8b63-ee8b0f0a0f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526459563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2526459563
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.928080344
Short name T714
Test name
Test status
Simulation time 139639902 ps
CPU time 0.6 seconds
Started Apr 02 12:27:24 PM PDT 24
Finished Apr 02 12:27:25 PM PDT 24
Peak memory 193356 kb
Host smart-9d33c496-a2e2-41fb-8b11-4d3d6e62b043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928080344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.928080344
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4171750759
Short name T800
Test name
Test status
Simulation time 508140056 ps
CPU time 3.28 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 197620 kb
Host smart-89965cc0-72ae-490f-a362-68b5405a8c9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171750759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4171750759
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1494004144
Short name T818
Test name
Test status
Simulation time 55949033 ps
CPU time 0.63 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 194088 kb
Host smart-5e2f8854-db9d-4904-b974-b3877f522fc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494004144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1494004144
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.671779073
Short name T771
Test name
Test status
Simulation time 40969180 ps
CPU time 1.01 seconds
Started Apr 02 12:27:07 PM PDT 24
Finished Apr 02 12:27:09 PM PDT 24
Peak memory 197536 kb
Host smart-6c7b416e-1e55-4fae-922a-6201f0f7555c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671779073 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.671779073
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3451746715
Short name T72
Test name
Test status
Simulation time 149177422 ps
CPU time 0.63 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 194472 kb
Host smart-aba03aab-fb7a-4b1a-9e33-4ebbd0001be9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451746715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3451746715
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.111413800
Short name T830
Test name
Test status
Simulation time 21021857 ps
CPU time 0.58 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 193324 kb
Host smart-0cfb9f65-0a98-4696-94dd-8dd0eb8a7f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111413800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.111413800
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1381342327
Short name T84
Test name
Test status
Simulation time 177126159 ps
CPU time 0.87 seconds
Started Apr 02 12:26:53 PM PDT 24
Finished Apr 02 12:26:55 PM PDT 24
Peak memory 195772 kb
Host smart-d49b7ac8-17f8-4511-9449-cbe412f9d12d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381342327 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1381342327
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2647920302
Short name T757
Test name
Test status
Simulation time 448875660 ps
CPU time 2.51 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 197576 kb
Host smart-4c4b375b-e8fc-421d-b890-6e0c9fa1a3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647920302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2647920302
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1890819797
Short name T49
Test name
Test status
Simulation time 87526862 ps
CPU time 0.93 seconds
Started Apr 02 12:26:53 PM PDT 24
Finished Apr 02 12:26:54 PM PDT 24
Peak memory 196900 kb
Host smart-e2f5d67f-d90e-4651-8602-d78579060acc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890819797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1890819797
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3664382841
Short name T711
Test name
Test status
Simulation time 39485655 ps
CPU time 0.58 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 193288 kb
Host smart-8ea8188b-eb92-4499-959e-1655ccfcb8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664382841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3664382841
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3813525809
Short name T809
Test name
Test status
Simulation time 17608861 ps
CPU time 0.57 seconds
Started Apr 02 12:27:14 PM PDT 24
Finished Apr 02 12:27:15 PM PDT 24
Peak memory 193996 kb
Host smart-c575a98b-425e-4603-8679-ff7d76a4e210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813525809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3813525809
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2087740539
Short name T797
Test name
Test status
Simulation time 14096864 ps
CPU time 0.58 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193284 kb
Host smart-d4d57e9b-1aba-4284-8907-781bc04ce0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087740539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2087740539
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4221045076
Short name T722
Test name
Test status
Simulation time 12734622 ps
CPU time 0.59 seconds
Started Apr 02 12:28:11 PM PDT 24
Finished Apr 02 12:28:11 PM PDT 24
Peak memory 193884 kb
Host smart-bdd4b0b2-2f39-4d39-820e-571b6a118a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221045076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4221045076
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2552386322
Short name T719
Test name
Test status
Simulation time 20812750 ps
CPU time 0.61 seconds
Started Apr 02 12:27:07 PM PDT 24
Finished Apr 02 12:27:09 PM PDT 24
Peak memory 193972 kb
Host smart-a5598cc7-e6d2-4363-8e66-44bdcfcf4b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552386322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2552386322
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3504204503
Short name T724
Test name
Test status
Simulation time 12807927 ps
CPU time 0.53 seconds
Started Apr 02 12:28:24 PM PDT 24
Finished Apr 02 12:28:25 PM PDT 24
Peak memory 193280 kb
Host smart-55010308-dc0c-4964-bb62-9bd850bc215d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504204503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3504204503
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.165416144
Short name T790
Test name
Test status
Simulation time 46203251 ps
CPU time 0.61 seconds
Started Apr 02 12:28:22 PM PDT 24
Finished Apr 02 12:28:23 PM PDT 24
Peak memory 194056 kb
Host smart-e0e12d49-bfc3-4105-ae42-9740c041964e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165416144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.165416144
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.393310070
Short name T740
Test name
Test status
Simulation time 48646466 ps
CPU time 0.59 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 194012 kb
Host smart-b56c7c28-a468-4b94-9292-c946a15f48f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393310070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.393310070
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3001290884
Short name T811
Test name
Test status
Simulation time 99009873 ps
CPU time 0.61 seconds
Started Apr 02 12:27:54 PM PDT 24
Finished Apr 02 12:27:55 PM PDT 24
Peak memory 192456 kb
Host smart-6dbce7c8-f888-480f-b1bd-5fa7898439dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001290884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3001290884
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1636641193
Short name T750
Test name
Test status
Simulation time 280082908 ps
CPU time 0.62 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:05 PM PDT 24
Peak memory 193996 kb
Host smart-bc777ee2-331b-4bd5-ba91-a6635282a9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636641193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1636641193
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1412143313
Short name T755
Test name
Test status
Simulation time 28056531 ps
CPU time 1.02 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 197412 kb
Host smart-b5f54bfd-2b3f-41c8-bf3b-c5af5094dd6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412143313 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1412143313
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1508423856
Short name T827
Test name
Test status
Simulation time 30992646 ps
CPU time 0.61 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 193988 kb
Host smart-65d47a9e-5313-4b86-b1ff-26ade8ad0f0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508423856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1508423856
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2861503059
Short name T749
Test name
Test status
Simulation time 14545357 ps
CPU time 0.59 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 193232 kb
Host smart-5a569b22-bcfa-49d4-921f-4a495e00ed7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861503059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2861503059
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3644468303
Short name T83
Test name
Test status
Simulation time 49172233 ps
CPU time 0.75 seconds
Started Apr 02 12:26:51 PM PDT 24
Finished Apr 02 12:26:52 PM PDT 24
Peak memory 195508 kb
Host smart-bd84b133-bbda-45f4-8d27-542db162bf6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644468303 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3644468303
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.796485884
Short name T751
Test name
Test status
Simulation time 73259482 ps
CPU time 0.98 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197464 kb
Host smart-aa46ec17-7df1-49ac-ae59-8dc74091ae6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796485884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.796485884
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.658053154
Short name T744
Test name
Test status
Simulation time 563342341 ps
CPU time 1.43 seconds
Started Apr 02 12:26:47 PM PDT 24
Finished Apr 02 12:26:48 PM PDT 24
Peak memory 197600 kb
Host smart-c28f01f1-5c64-4523-9c40-7e5f57faf3b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658053154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.658053154
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.878105794
Short name T805
Test name
Test status
Simulation time 29811188 ps
CPU time 0.83 seconds
Started Apr 02 12:27:06 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 197572 kb
Host smart-ced91a14-2414-4dcf-90c1-50142e054494
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878105794 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.878105794
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3368875869
Short name T79
Test name
Test status
Simulation time 20452014 ps
CPU time 0.6 seconds
Started Apr 02 12:27:22 PM PDT 24
Finished Apr 02 12:27:22 PM PDT 24
Peak memory 194328 kb
Host smart-879ec1be-1d4d-4fe9-8e14-fa43f6f9ee58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368875869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3368875869
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3057527548
Short name T712
Test name
Test status
Simulation time 14476089 ps
CPU time 0.57 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:57 PM PDT 24
Peak memory 193316 kb
Host smart-047ec136-5eea-43a2-9be8-09a41333e4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057527548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3057527548
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2897083539
Short name T71
Test name
Test status
Simulation time 119085275 ps
CPU time 0.75 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 195424 kb
Host smart-80b8d2f8-a78f-4308-bbf6-22673ecccd09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897083539 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2897083539
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2892207797
Short name T742
Test name
Test status
Simulation time 301258625 ps
CPU time 1.48 seconds
Started Apr 02 12:27:04 PM PDT 24
Finished Apr 02 12:27:06 PM PDT 24
Peak memory 197568 kb
Host smart-192460c5-a1ca-4d80-ac7d-2ca81fe81119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892207797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2892207797
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.490172246
Short name T47
Test name
Test status
Simulation time 102093891 ps
CPU time 1.4 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 197504 kb
Host smart-0c02edf8-2303-4f1b-89c4-f37434e51cc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490172246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.490172246
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4111525532
Short name T733
Test name
Test status
Simulation time 174541180 ps
CPU time 0.75 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 197364 kb
Host smart-ee0aaaff-a1f2-432c-b7ac-e612169ea595
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111525532 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4111525532
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1026507180
Short name T831
Test name
Test status
Simulation time 16482908 ps
CPU time 0.63 seconds
Started Apr 02 12:27:03 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 195016 kb
Host smart-befa9385-b5e6-4c1e-9167-f10ebd200ccd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026507180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1026507180
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2121556585
Short name T721
Test name
Test status
Simulation time 22597651 ps
CPU time 0.59 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 193376 kb
Host smart-1cdafc4f-0108-4951-a377-64ab11ddb3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121556585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2121556585
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.675745101
Short name T760
Test name
Test status
Simulation time 171014513 ps
CPU time 0.93 seconds
Started Apr 02 12:27:29 PM PDT 24
Finished Apr 02 12:27:30 PM PDT 24
Peak memory 196116 kb
Host smart-4406ee11-91c4-4a5a-878f-a17bd612eb40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675745101 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.675745101
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.998518939
Short name T717
Test name
Test status
Simulation time 609961365 ps
CPU time 3.3 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197616 kb
Host smart-e450ea74-e4ad-489f-8114-1cd03d8b6af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998518939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.998518939
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2773797114
Short name T39
Test name
Test status
Simulation time 115266027 ps
CPU time 1.41 seconds
Started Apr 02 12:26:49 PM PDT 24
Finished Apr 02 12:26:51 PM PDT 24
Peak memory 197632 kb
Host smart-36b21a37-4f04-4a60-a706-53d14cf507b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773797114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2773797114
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1455955289
Short name T710
Test name
Test status
Simulation time 30536471 ps
CPU time 1.31 seconds
Started Apr 02 12:27:03 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197624 kb
Host smart-ede65f5e-04da-42b5-bb87-9e0efdc172a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455955289 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1455955289
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.922998941
Short name T65
Test name
Test status
Simulation time 22239406 ps
CPU time 0.58 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 194312 kb
Host smart-1dc46590-a7d3-4f1a-a1f8-cea3f4709f91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922998941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.922998941
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.651134213
Short name T767
Test name
Test status
Simulation time 12496174 ps
CPU time 0.56 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:03 PM PDT 24
Peak memory 193872 kb
Host smart-e2b702d0-d80f-45f3-bb17-866c8c11d1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651134213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.651134213
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.456256925
Short name T66
Test name
Test status
Simulation time 57202890 ps
CPU time 0.75 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:26:59 PM PDT 24
Peak memory 195788 kb
Host smart-01274f0f-a80b-457a-b0b0-eae387a9aad3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456256925 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.456256925
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.538648402
Short name T716
Test name
Test status
Simulation time 124763623 ps
CPU time 1.41 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197608 kb
Host smart-14821568-52a8-4771-8a3b-28fe9f147521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538648402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.538648402
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1738753655
Short name T773
Test name
Test status
Simulation time 265173222 ps
CPU time 1.14 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197544 kb
Host smart-4e2aa6a9-6a7a-4a6b-8e52-5cfb00089270
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738753655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1738753655
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.127023205
Short name T743
Test name
Test status
Simulation time 156786781 ps
CPU time 1.55 seconds
Started Apr 02 12:27:05 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 197716 kb
Host smart-80770f58-83ac-4ec5-94a8-caad502e2337
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127023205 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.127023205
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2379603076
Short name T775
Test name
Test status
Simulation time 50041868 ps
CPU time 0.59 seconds
Started Apr 02 12:27:03 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 194296 kb
Host smart-857238b5-de76-49d9-8eee-306370c854dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379603076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2379603076
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4158956560
Short name T799
Test name
Test status
Simulation time 16941621 ps
CPU time 0.56 seconds
Started Apr 02 12:26:55 PM PDT 24
Finished Apr 02 12:26:56 PM PDT 24
Peak memory 193224 kb
Host smart-0a56accc-7ee1-46ea-a178-ed585716db92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158956560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4158956560
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.26559522
Short name T792
Test name
Test status
Simulation time 38453406 ps
CPU time 0.63 seconds
Started Apr 02 12:27:06 PM PDT 24
Finished Apr 02 12:27:13 PM PDT 24
Peak memory 194108 kb
Host smart-744af59f-680e-4d04-9c3d-1d6590f0e30f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559522 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.gpio_same_csr_outstanding.26559522
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.202569302
Short name T779
Test name
Test status
Simulation time 23036289 ps
CPU time 1.14 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197584 kb
Host smart-88bf83d8-b177-443a-8b55-78885df0bd4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202569302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.202569302
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1369641656
Short name T37
Test name
Test status
Simulation time 115943860 ps
CPU time 1.44 seconds
Started Apr 02 12:26:58 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197632 kb
Host smart-c159d3b4-6660-460d-afd8-0155a0136e8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369641656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1369641656
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4280488693
Short name T694
Test name
Test status
Simulation time 19374235 ps
CPU time 0.58 seconds
Started Apr 02 12:49:42 PM PDT 24
Finished Apr 02 12:49:43 PM PDT 24
Peak memory 193940 kb
Host smart-9087ab89-ddfe-4474-9ee5-f83790dd6616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280488693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4280488693
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1519607211
Short name T347
Test name
Test status
Simulation time 77481872 ps
CPU time 0.95 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 196196 kb
Host smart-8c93b090-e322-45f6-b8a2-edec8d186322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519607211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1519607211
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2589245335
Short name T396
Test name
Test status
Simulation time 1699482002 ps
CPU time 20.57 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 195528 kb
Host smart-ff1e09c5-2d0d-4bb2-8058-66e9eaae936d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589245335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2589245335
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1997754939
Short name T142
Test name
Test status
Simulation time 71551080 ps
CPU time 0.76 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 195752 kb
Host smart-eff25fb8-9703-4843-bbb7-986c801cd004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997754939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1997754939
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2469268959
Short name T329
Test name
Test status
Simulation time 60243716 ps
CPU time 1.24 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 195764 kb
Host smart-7a5de7e0-bef9-4953-a9dc-b8eef15ed4d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469268959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2469268959
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3716299792
Short name T212
Test name
Test status
Simulation time 1088320513 ps
CPU time 3.03 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 198072 kb
Host smart-3d189e1d-d076-4e79-ad4d-1006fc21daf8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716299792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3716299792
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2286568215
Short name T301
Test name
Test status
Simulation time 283381314 ps
CPU time 3.55 seconds
Started Apr 02 12:49:45 PM PDT 24
Finished Apr 02 12:49:49 PM PDT 24
Peak memory 198044 kb
Host smart-6ce100ac-cdfa-4981-ad17-14e892ca28c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286568215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2286568215
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.29468107
Short name T420
Test name
Test status
Simulation time 91747505 ps
CPU time 1.28 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 195844 kb
Host smart-9fc2bb2f-3724-4926-951b-3b9805635dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29468107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.29468107
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3830075886
Short name T706
Test name
Test status
Simulation time 189667759 ps
CPU time 1.16 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 198016 kb
Host smart-759a1d5f-2b06-44e5-9b40-e1e91f182a2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830075886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3830075886
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.203867772
Short name T122
Test name
Test status
Simulation time 81150590 ps
CPU time 3.86 seconds
Started Apr 02 12:49:43 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 197908 kb
Host smart-1089751f-7ba9-4109-a266-8597bcb51b0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203867772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.203867772
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1450254105
Short name T43
Test name
Test status
Simulation time 306035475 ps
CPU time 0.98 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 214956 kb
Host smart-2ee6f632-2044-487c-bb4a-dc448ff75e51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450254105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1450254105
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2303765959
Short name T92
Test name
Test status
Simulation time 47925448 ps
CPU time 1 seconds
Started Apr 02 12:49:40 PM PDT 24
Finished Apr 02 12:49:41 PM PDT 24
Peak memory 195572 kb
Host smart-971d7589-aa2e-4392-860a-ac0e606109bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303765959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2303765959
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.495449125
Short name T537
Test name
Test status
Simulation time 63336505 ps
CPU time 1.13 seconds
Started Apr 02 12:49:40 PM PDT 24
Finished Apr 02 12:49:41 PM PDT 24
Peak memory 195536 kb
Host smart-4042d798-40f7-4b39-8a32-839bbb228fba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495449125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.495449125
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1158346876
Short name T596
Test name
Test status
Simulation time 13000571231 ps
CPU time 87.91 seconds
Started Apr 02 12:49:43 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 198096 kb
Host smart-c81689e1-e287-4864-91ad-b9681cb5fa86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158346876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1158346876
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4063620949
Short name T35
Test name
Test status
Simulation time 64653054070 ps
CPU time 2220.48 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 01:26:47 PM PDT 24
Peak memory 198208 kb
Host smart-efca7f61-eb1d-4d4d-993f-92c150bde60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4063620949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4063620949
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3837711647
Short name T321
Test name
Test status
Simulation time 49886175 ps
CPU time 0.56 seconds
Started Apr 02 12:49:52 PM PDT 24
Finished Apr 02 12:49:52 PM PDT 24
Peak memory 194636 kb
Host smart-be534072-26e5-4261-a58b-70390ccba8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837711647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3837711647
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3593205603
Short name T477
Test name
Test status
Simulation time 28887186 ps
CPU time 0.97 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 195940 kb
Host smart-c299e0c8-f203-42de-9e21-84a0624ce09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593205603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3593205603
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4039767361
Short name T346
Test name
Test status
Simulation time 213378454 ps
CPU time 2.92 seconds
Started Apr 02 12:49:48 PM PDT 24
Finished Apr 02 12:49:51 PM PDT 24
Peak memory 195960 kb
Host smart-71b7745a-b1c8-4489-88ae-459f96488b54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039767361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4039767361
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2247097400
Short name T581
Test name
Test status
Simulation time 235359580 ps
CPU time 0.75 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 195868 kb
Host smart-5c4ecdfa-e22d-47db-810a-433588ea7ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247097400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2247097400
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.793624877
Short name T326
Test name
Test status
Simulation time 93131144 ps
CPU time 1.29 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 196564 kb
Host smart-3319b3b1-ec53-4366-8c9e-6480e936d6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793624877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.793624877
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1236298422
Short name T272
Test name
Test status
Simulation time 48529301 ps
CPU time 1.92 seconds
Started Apr 02 12:49:45 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 196348 kb
Host smart-23d1865a-4423-4d01-9e2b-ed67e57789ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236298422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1236298422
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1249829651
Short name T191
Test name
Test status
Simulation time 213831739 ps
CPU time 2.49 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 197144 kb
Host smart-22a86b8c-b990-4de7-8368-25f03cf475d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249829651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1249829651
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4205369875
Short name T386
Test name
Test status
Simulation time 275637287 ps
CPU time 1.38 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 196880 kb
Host smart-6deec8d2-7e8f-4f0b-a911-3f69968a8ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205369875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4205369875
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2505965272
Short name T578
Test name
Test status
Simulation time 75449532 ps
CPU time 0.99 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 196044 kb
Host smart-52db7282-1705-435b-95f3-a97c62455063
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505965272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2505965272
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.790630489
Short name T678
Test name
Test status
Simulation time 309900920 ps
CPU time 1.44 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 197988 kb
Host smart-506a2a97-1807-4940-993d-9ab1cdefd5ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790630489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.790630489
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3636970999
Short name T52
Test name
Test status
Simulation time 62655020 ps
CPU time 0.86 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 213736 kb
Host smart-73ae18a3-de00-4e79-a8a9-b544941916ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636970999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3636970999
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3790312877
Short name T589
Test name
Test status
Simulation time 180036719 ps
CPU time 1.08 seconds
Started Apr 02 12:49:44 PM PDT 24
Finished Apr 02 12:49:45 PM PDT 24
Peak memory 196424 kb
Host smart-a991a97a-12f0-4a30-90f8-ec928493333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790312877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3790312877
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3882149826
Short name T590
Test name
Test status
Simulation time 83598731 ps
CPU time 0.92 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:49:52 PM PDT 24
Peak memory 195516 kb
Host smart-67db1d8e-d106-47c0-96d0-69d884a19258
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882149826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3882149826
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2719397129
Short name T428
Test name
Test status
Simulation time 7342505650 ps
CPU time 178.73 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:52:46 PM PDT 24
Peak memory 198164 kb
Host smart-0c4e46a9-d374-4aee-9625-b81531a79116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719397129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2719397129
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3098154423
Short name T667
Test name
Test status
Simulation time 50006544 ps
CPU time 0.58 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 194076 kb
Host smart-263523e5-4f7d-4be4-a410-0d55a39fb5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098154423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3098154423
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.138142862
Short name T164
Test name
Test status
Simulation time 360177692 ps
CPU time 0.81 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 195428 kb
Host smart-0c856ed4-8375-46f9-8742-81ea832f1aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138142862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.138142862
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3962020791
Short name T311
Test name
Test status
Simulation time 2028587967 ps
CPU time 18.04 seconds
Started Apr 02 12:50:21 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 197080 kb
Host smart-cede27d0-e0ba-48e5-b0c7-6e291faf5116
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962020791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3962020791
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2168545276
Short name T556
Test name
Test status
Simulation time 33180843 ps
CPU time 0.76 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 12:50:24 PM PDT 24
Peak memory 196608 kb
Host smart-4649f60a-aac9-44bf-aed6-1c0667f6c25c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168545276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2168545276
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1537682791
Short name T150
Test name
Test status
Simulation time 69048268 ps
CPU time 1.13 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:21 PM PDT 24
Peak memory 196000 kb
Host smart-c14e2ed7-68c5-4311-acef-3ffef8277b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537682791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1537682791
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2078031536
Short name T362
Test name
Test status
Simulation time 60328332 ps
CPU time 2.33 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 198020 kb
Host smart-ebd875c3-829c-4a03-9dad-4396b6d09de5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078031536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2078031536
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2737052722
Short name T548
Test name
Test status
Simulation time 260924564 ps
CPU time 1.56 seconds
Started Apr 02 12:50:22 PM PDT 24
Finished Apr 02 12:50:24 PM PDT 24
Peak memory 195764 kb
Host smart-3444cd73-eb9d-4079-af99-41c9c869ebcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737052722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2737052722
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.858990721
Short name T204
Test name
Test status
Simulation time 464361495 ps
CPU time 1.28 seconds
Started Apr 02 12:50:20 PM PDT 24
Finished Apr 02 12:50:23 PM PDT 24
Peak memory 197116 kb
Host smart-6ab0319c-4429-4a1b-9827-151bbe8aef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858990721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.858990721
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1612189704
Short name T358
Test name
Test status
Simulation time 48517756 ps
CPU time 1.1 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 196740 kb
Host smart-86675bb9-1170-49bf-8a35-b70faeccf9e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612189704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1612189704
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1967875279
Short name T151
Test name
Test status
Simulation time 484264068 ps
CPU time 2.24 seconds
Started Apr 02 12:50:25 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 197920 kb
Host smart-2082a3a7-d5ee-4e80-a128-35c40a0b0ce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967875279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1967875279
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1108648577
Short name T616
Test name
Test status
Simulation time 53397273 ps
CPU time 1.38 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 196724 kb
Host smart-e552c9d9-46d1-4f0d-a8e6-6b576cffc567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108648577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1108648577
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.936013229
Short name T337
Test name
Test status
Simulation time 64996006 ps
CPU time 1.28 seconds
Started Apr 02 12:50:18 PM PDT 24
Finished Apr 02 12:50:20 PM PDT 24
Peak memory 196860 kb
Host smart-099a50c5-4ac5-4603-91fe-d3743b9c8e3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936013229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.936013229
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.871286562
Short name T382
Test name
Test status
Simulation time 26351027522 ps
CPU time 175.23 seconds
Started Apr 02 12:50:22 PM PDT 24
Finished Apr 02 12:53:18 PM PDT 24
Peak memory 198168 kb
Host smart-bdcb56f5-e0cc-48ba-9c06-a10570cdf4df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871286562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.871286562
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3368643023
Short name T693
Test name
Test status
Simulation time 142996657534 ps
CPU time 1507.64 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 01:15:31 PM PDT 24
Peak memory 198252 kb
Host smart-b6fe9a87-79bf-4f08-b33e-ff5c666eadc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3368643023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3368643023
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2436018987
Short name T568
Test name
Test status
Simulation time 69420672 ps
CPU time 0.6 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 194876 kb
Host smart-f0c8b6b6-81e6-4562-baab-570858169d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436018987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2436018987
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4011999210
Short name T102
Test name
Test status
Simulation time 30992839 ps
CPU time 0.75 seconds
Started Apr 02 12:50:25 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 195336 kb
Host smart-c7054a07-b8f5-44bd-a7f3-374995f78df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011999210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4011999210
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.708566739
Short name T313
Test name
Test status
Simulation time 433116661 ps
CPU time 13.62 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:39 PM PDT 24
Peak memory 197144 kb
Host smart-3e4e32ae-1df8-4732-b4ce-d04900bc3cdc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708566739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.708566739
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.728415308
Short name T107
Test name
Test status
Simulation time 108967684 ps
CPU time 0.72 seconds
Started Apr 02 12:50:29 PM PDT 24
Finished Apr 02 12:50:30 PM PDT 24
Peak memory 194648 kb
Host smart-52bb0aa8-64db-4bee-8610-545df6f5b2a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728415308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.728415308
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.4052888989
Short name T352
Test name
Test status
Simulation time 114007125 ps
CPU time 0.76 seconds
Started Apr 02 12:50:21 PM PDT 24
Finished Apr 02 12:50:23 PM PDT 24
Peak memory 196272 kb
Host smart-70f0a050-8fe5-4cea-9a41-38eeca1805f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052888989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.4052888989
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1517723457
Short name T263
Test name
Test status
Simulation time 22712271 ps
CPU time 0.98 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 196208 kb
Host smart-d962055c-3d09-42d4-a48d-d7cddb59c9a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517723457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1517723457
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3568561020
Short name T510
Test name
Test status
Simulation time 269858214 ps
CPU time 1.79 seconds
Started Apr 02 12:50:22 PM PDT 24
Finished Apr 02 12:50:25 PM PDT 24
Peak memory 195928 kb
Host smart-67d2429d-d2ea-4461-b855-e22740684745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568561020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3568561020
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3547926756
Short name T237
Test name
Test status
Simulation time 24684267 ps
CPU time 0.78 seconds
Started Apr 02 12:50:25 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 195404 kb
Host smart-b667a899-6395-4922-ad10-83d633e93d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547926756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3547926756
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4281867942
Short name T395
Test name
Test status
Simulation time 24281758 ps
CPU time 0.74 seconds
Started Apr 02 12:50:22 PM PDT 24
Finished Apr 02 12:50:24 PM PDT 24
Peak memory 196112 kb
Host smart-cdc1aed2-75ec-45e1-acf5-75caa3ad91fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281867942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4281867942
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.530994156
Short name T649
Test name
Test status
Simulation time 68357617 ps
CPU time 1.51 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 197964 kb
Host smart-5f9b7a39-6266-4915-8461-130487790dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530994156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.530994156
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.574464052
Short name T688
Test name
Test status
Simulation time 36195011 ps
CPU time 1.07 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 196256 kb
Host smart-08b00dd1-2aac-4ce8-b9de-42087457f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574464052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.574464052
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2282786910
Short name T91
Test name
Test status
Simulation time 48348960 ps
CPU time 1.35 seconds
Started Apr 02 12:50:26 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 196832 kb
Host smart-16cc245e-55db-4bc9-aa50-b34462260410
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282786910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2282786910
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2954566289
Short name T427
Test name
Test status
Simulation time 27335390432 ps
CPU time 173.94 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:53:19 PM PDT 24
Peak memory 198148 kb
Host smart-ecc6eff7-22ae-4c07-a8e4-e604d9b1714a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954566289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2954566289
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1182101174
Short name T704
Test name
Test status
Simulation time 12274829 ps
CPU time 0.63 seconds
Started Apr 02 12:50:28 PM PDT 24
Finished Apr 02 12:50:28 PM PDT 24
Peak memory 193860 kb
Host smart-bd00e32d-ac0e-4dec-9a14-0e6b9b71ea27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182101174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1182101174
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2119008949
Short name T366
Test name
Test status
Simulation time 76448505 ps
CPU time 0.75 seconds
Started Apr 02 12:50:29 PM PDT 24
Finished Apr 02 12:50:30 PM PDT 24
Peak memory 196096 kb
Host smart-bda3c56b-dadf-4fd1-9124-41afc4fa1208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119008949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2119008949
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3170367127
Short name T682
Test name
Test status
Simulation time 3267419019 ps
CPU time 27.64 seconds
Started Apr 02 12:50:28 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 195940 kb
Host smart-6dff0556-4a03-424d-956c-ae178e8db86e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170367127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3170367127
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1756232695
Short name T157
Test name
Test status
Simulation time 600907737 ps
CPU time 1.03 seconds
Started Apr 02 12:50:28 PM PDT 24
Finished Apr 02 12:50:29 PM PDT 24
Peak memory 196704 kb
Host smart-53dffaf9-bd60-40a6-8d75-f76f0dcbaa1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756232695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1756232695
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2752366317
Short name T132
Test name
Test status
Simulation time 83661366 ps
CPU time 0.73 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 194336 kb
Host smart-edc83936-e915-4e27-a0c4-e604db828fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752366317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2752366317
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4095771596
Short name T198
Test name
Test status
Simulation time 139533797 ps
CPU time 3.09 seconds
Started Apr 02 12:50:28 PM PDT 24
Finished Apr 02 12:50:32 PM PDT 24
Peak memory 198000 kb
Host smart-c3eff171-2f58-4020-bec3-2f05c7b92629
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095771596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4095771596
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2675088619
Short name T236
Test name
Test status
Simulation time 113371907 ps
CPU time 1.78 seconds
Started Apr 02 12:50:28 PM PDT 24
Finished Apr 02 12:50:30 PM PDT 24
Peak memory 195732 kb
Host smart-ddcb5612-9282-436b-829d-453505f079f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675088619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2675088619
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.896788907
Short name T162
Test name
Test status
Simulation time 53426711 ps
CPU time 0.83 seconds
Started Apr 02 12:50:26 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 195496 kb
Host smart-59549fdf-a260-4548-9c99-71b1c624dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896788907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.896788907
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3628124017
Short name T171
Test name
Test status
Simulation time 403390601 ps
CPU time 1.02 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:26 PM PDT 24
Peak memory 196036 kb
Host smart-79049032-045b-40ca-b5c8-25115f2c3471
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628124017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3628124017
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.4177522395
Short name T487
Test name
Test status
Simulation time 422549671 ps
CPU time 4.98 seconds
Started Apr 02 12:50:29 PM PDT 24
Finished Apr 02 12:50:34 PM PDT 24
Peak memory 197972 kb
Host smart-c8983912-82ec-4c9e-8d9d-c88e7cca3636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177522395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.4177522395
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.790071501
Short name T664
Test name
Test status
Simulation time 222033448 ps
CPU time 1.07 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 12:50:25 PM PDT 24
Peak memory 195716 kb
Host smart-09befb7a-34ae-45ca-9f93-4dce07c275c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790071501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.790071501
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3632661240
Short name T657
Test name
Test status
Simulation time 51030478 ps
CPU time 1.48 seconds
Started Apr 02 12:50:21 PM PDT 24
Finished Apr 02 12:50:23 PM PDT 24
Peak memory 196688 kb
Host smart-7781fe2e-d09c-4d6f-adb8-5902b1959bbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632661240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3632661240
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.236703404
Short name T606
Test name
Test status
Simulation time 10556646989 ps
CPU time 122.74 seconds
Started Apr 02 12:50:31 PM PDT 24
Finished Apr 02 12:52:34 PM PDT 24
Peak memory 198252 kb
Host smart-3509b441-21b4-4f25-85db-4daae8a8c51d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236703404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.236703404
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.907879013
Short name T559
Test name
Test status
Simulation time 18575418 ps
CPU time 0.63 seconds
Started Apr 02 12:50:30 PM PDT 24
Finished Apr 02 12:50:31 PM PDT 24
Peak memory 193992 kb
Host smart-d67f8aaa-5b99-426e-b0c6-ed35d41ff81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907879013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.907879013
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2083610594
Short name T368
Test name
Test status
Simulation time 6680625283 ps
CPU time 14 seconds
Started Apr 02 12:50:26 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 197120 kb
Host smart-c9ff2de4-e2e1-40a6-b0b2-29e274273224
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083610594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2083610594
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.581844221
Short name T332
Test name
Test status
Simulation time 140692374 ps
CPU time 0.62 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:28 PM PDT 24
Peak memory 195372 kb
Host smart-cb2117e0-3f45-448a-8cc9-01aea1a77afe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581844221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.581844221
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2784100157
Short name T220
Test name
Test status
Simulation time 38912015 ps
CPU time 0.94 seconds
Started Apr 02 12:50:32 PM PDT 24
Finished Apr 02 12:50:33 PM PDT 24
Peak memory 197380 kb
Host smart-fef6acd2-d734-40b3-8963-fa1067a7e2d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784100157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2784100157
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3894172863
Short name T275
Test name
Test status
Simulation time 209150620 ps
CPU time 2.5 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:30 PM PDT 24
Peak memory 198016 kb
Host smart-e576b8dc-d718-4ab1-8dc0-0566f0eda615
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894172863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3894172863
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2520272844
Short name T505
Test name
Test status
Simulation time 864645055 ps
CPU time 1.86 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:29 PM PDT 24
Peak memory 196100 kb
Host smart-c8a97306-9903-47a8-a795-68081ebe4954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520272844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2520272844
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1812047523
Short name T592
Test name
Test status
Simulation time 270280955 ps
CPU time 1.48 seconds
Started Apr 02 12:50:25 PM PDT 24
Finished Apr 02 12:50:27 PM PDT 24
Peak memory 198044 kb
Host smart-9540ea59-31f9-4abd-9c5e-cfbf8afe439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812047523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1812047523
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1259025578
Short name T353
Test name
Test status
Simulation time 34749174 ps
CPU time 0.91 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:28 PM PDT 24
Peak memory 195940 kb
Host smart-5dc18c96-87e8-4157-990c-991df2e3d544
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259025578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1259025578
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1802793300
Short name T264
Test name
Test status
Simulation time 422575271 ps
CPU time 3.67 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:31 PM PDT 24
Peak memory 198040 kb
Host smart-182f8cf1-b1a8-4cfb-9738-8dddf085d735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802793300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1802793300
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2471539364
Short name T228
Test name
Test status
Simulation time 41583156 ps
CPU time 0.88 seconds
Started Apr 02 12:50:29 PM PDT 24
Finished Apr 02 12:50:31 PM PDT 24
Peak memory 195376 kb
Host smart-8bf44e13-775b-4e10-9c27-924e9d1217cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471539364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2471539364
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2112470659
Short name T676
Test name
Test status
Simulation time 68302574 ps
CPU time 0.85 seconds
Started Apr 02 12:50:27 PM PDT 24
Finished Apr 02 12:50:28 PM PDT 24
Peak memory 195256 kb
Host smart-ef448d56-5ec9-4c85-8ccd-1c2f0910b064
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112470659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2112470659
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.764644181
Short name T431
Test name
Test status
Simulation time 19867762661 ps
CPU time 213.83 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:54:12 PM PDT 24
Peak memory 198172 kb
Host smart-ea8faa9d-2fe5-40fc-a6ad-769b90b03e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764644181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.764644181
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1786485954
Short name T254
Test name
Test status
Simulation time 35979137 ps
CPU time 0.6 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 193932 kb
Host smart-459df6b9-1a55-4b39-aad9-8d015a51c373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786485954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1786485954
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2340675608
Short name T557
Test name
Test status
Simulation time 67485300 ps
CPU time 0.67 seconds
Started Apr 02 12:50:32 PM PDT 24
Finished Apr 02 12:50:33 PM PDT 24
Peak memory 194804 kb
Host smart-b428693f-8e8f-47c1-bd3f-f7debcfb5ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340675608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2340675608
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2637138343
Short name T18
Test name
Test status
Simulation time 1368092689 ps
CPU time 9.33 seconds
Started Apr 02 12:50:30 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 196840 kb
Host smart-4dcd5358-60f2-48dd-8c70-81dec47bafa7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637138343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2637138343
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1226930363
Short name T545
Test name
Test status
Simulation time 272027699 ps
CPU time 1.03 seconds
Started Apr 02 12:50:32 PM PDT 24
Finished Apr 02 12:50:33 PM PDT 24
Peak memory 196696 kb
Host smart-1552ee8b-21f3-45c2-a1e0-734693eb4954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226930363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1226930363
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4121381295
Short name T340
Test name
Test status
Simulation time 90777793 ps
CPU time 0.93 seconds
Started Apr 02 12:50:31 PM PDT 24
Finished Apr 02 12:50:33 PM PDT 24
Peak memory 196120 kb
Host smart-7ddf6abf-429a-434f-8cb2-fa4bc3a41aa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121381295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4121381295
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3048306580
Short name T214
Test name
Test status
Simulation time 382354855 ps
CPU time 2.5 seconds
Started Apr 02 12:50:33 PM PDT 24
Finished Apr 02 12:50:36 PM PDT 24
Peak memory 198104 kb
Host smart-5fefcb3f-6527-48ad-866f-af879b4b936b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048306580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3048306580
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2328187013
Short name T621
Test name
Test status
Simulation time 147275436 ps
CPU time 2.87 seconds
Started Apr 02 12:50:33 PM PDT 24
Finished Apr 02 12:50:36 PM PDT 24
Peak memory 197212 kb
Host smart-0c0d936b-fe0a-491e-ac4d-1a7457092ef3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328187013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2328187013
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2114189205
Short name T495
Test name
Test status
Simulation time 21390823 ps
CPU time 0.67 seconds
Started Apr 02 12:50:32 PM PDT 24
Finished Apr 02 12:50:33 PM PDT 24
Peak memory 194308 kb
Host smart-ee55e51c-af22-4180-a7c0-44decf34e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114189205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2114189205
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4166117173
Short name T522
Test name
Test status
Simulation time 19296751 ps
CPU time 0.72 seconds
Started Apr 02 12:50:31 PM PDT 24
Finished Apr 02 12:50:32 PM PDT 24
Peak memory 194304 kb
Host smart-b60e223a-a6ad-4213-9b94-46590902d36c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166117173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4166117173
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2751481065
Short name T369
Test name
Test status
Simulation time 459458349 ps
CPU time 5.47 seconds
Started Apr 02 12:50:33 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 197968 kb
Host smart-14a4085c-2441-4c9b-96dd-3217ac886fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751481065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2751481065
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.569917118
Short name T457
Test name
Test status
Simulation time 70426580 ps
CPU time 1.23 seconds
Started Apr 02 12:50:31 PM PDT 24
Finished Apr 02 12:50:32 PM PDT 24
Peak memory 197996 kb
Host smart-cd0fafd3-3dac-4edf-b924-3daf408db1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569917118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.569917118
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1600392067
Short name T235
Test name
Test status
Simulation time 36633774 ps
CPU time 1.08 seconds
Started Apr 02 12:50:30 PM PDT 24
Finished Apr 02 12:50:31 PM PDT 24
Peak memory 196484 kb
Host smart-b1c3827f-dc6e-43e2-a47a-a178fa924fcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600392067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1600392067
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1511729387
Short name T291
Test name
Test status
Simulation time 57820247123 ps
CPU time 110.46 seconds
Started Apr 02 12:50:30 PM PDT 24
Finished Apr 02 12:52:21 PM PDT 24
Peak memory 198128 kb
Host smart-03fc30ee-ca61-4971-8699-9f642880cd4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511729387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1511729387
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.614391107
Short name T623
Test name
Test status
Simulation time 15127643 ps
CPU time 0.6 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 12:50:36 PM PDT 24
Peak memory 194016 kb
Host smart-a9679cf1-a745-41d9-aca9-e528857e8e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614391107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.614391107
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.553343588
Short name T566
Test name
Test status
Simulation time 86220564 ps
CPU time 0.82 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 12:50:36 PM PDT 24
Peak memory 195320 kb
Host smart-9b8874a4-8039-402c-98ae-6bc7a4fd1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553343588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.553343588
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.444153961
Short name T604
Test name
Test status
Simulation time 956376451 ps
CPU time 23.28 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:51:02 PM PDT 24
Peak memory 195516 kb
Host smart-de1ab036-a601-4c70-b002-97d8fd38d755
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444153961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.444153961
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1320847802
Short name T188
Test name
Test status
Simulation time 87790916 ps
CPU time 0.79 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 12:50:37 PM PDT 24
Peak memory 196616 kb
Host smart-aa14174f-f4c3-4ae9-81b5-e5e6e76e1e9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320847802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1320847802
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2572660836
Short name T485
Test name
Test status
Simulation time 610457274 ps
CPU time 1 seconds
Started Apr 02 12:50:36 PM PDT 24
Finished Apr 02 12:50:37 PM PDT 24
Peak memory 196000 kb
Host smart-7493e02b-a19a-45b3-ba85-90b8b2a4f609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572660836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2572660836
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1860477370
Short name T296
Test name
Test status
Simulation time 388566634 ps
CPU time 2.39 seconds
Started Apr 02 12:50:36 PM PDT 24
Finished Apr 02 12:50:39 PM PDT 24
Peak memory 198032 kb
Host smart-0b4ae339-c9b3-4947-abbb-f32c1d72f6d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860477370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1860477370
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3210007805
Short name T133
Test name
Test status
Simulation time 180829631 ps
CPU time 3.44 seconds
Started Apr 02 12:50:36 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 197120 kb
Host smart-2cfce42e-3fe9-4a84-a7b7-c8c8cc8c02c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210007805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3210007805
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3218082658
Short name T223
Test name
Test status
Simulation time 35426220 ps
CPU time 0.67 seconds
Started Apr 02 12:50:37 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 194288 kb
Host smart-4e7cb70a-3048-44ab-b510-b695d9016341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218082658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3218082658
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3395177506
Short name T182
Test name
Test status
Simulation time 52842556 ps
CPU time 1.2 seconds
Started Apr 02 12:50:36 PM PDT 24
Finished Apr 02 12:50:37 PM PDT 24
Peak memory 197136 kb
Host smart-f3b61661-820d-46e2-97bb-b457dd9d24a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395177506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3395177506
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.404446050
Short name T153
Test name
Test status
Simulation time 113249455 ps
CPU time 5.29 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:44 PM PDT 24
Peak memory 197948 kb
Host smart-00cef50e-c653-4711-b1d8-e27bf7178b2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404446050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.404446050
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.822117761
Short name T175
Test name
Test status
Simulation time 43777012 ps
CPU time 1.29 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:42 PM PDT 24
Peak memory 196548 kb
Host smart-ca63fc8e-4e7b-4f25-a268-677998aace36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822117761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.822117761
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3678265469
Short name T608
Test name
Test status
Simulation time 58139270 ps
CPU time 1.16 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 12:50:36 PM PDT 24
Peak memory 195516 kb
Host smart-77af5901-0731-4c61-ab80-1d954001bccb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678265469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3678265469
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2417344167
Short name T634
Test name
Test status
Simulation time 18568483815 ps
CPU time 98.67 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 12:52:14 PM PDT 24
Peak memory 198140 kb
Host smart-057b3a63-a424-4b50-a653-dfe248a3414d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417344167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2417344167
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2250577646
Short name T504
Test name
Test status
Simulation time 356188730328 ps
CPU time 2050.97 seconds
Started Apr 02 12:50:35 PM PDT 24
Finished Apr 02 01:24:46 PM PDT 24
Peak memory 198204 kb
Host smart-e2b7b78c-af1c-443f-b78d-460bfdfb3f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2250577646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2250577646
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2574057705
Short name T411
Test name
Test status
Simulation time 16537697 ps
CPU time 0.59 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 194144 kb
Host smart-211dcbf3-d3fe-43a2-b2fd-cf54be3c11bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574057705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2574057705
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.496423664
Short name T582
Test name
Test status
Simulation time 42164996 ps
CPU time 0.61 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 194552 kb
Host smart-5454c93e-bb1f-457b-a389-7153a46b69a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496423664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.496423664
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.574093232
Short name T210
Test name
Test status
Simulation time 1481513265 ps
CPU time 26.7 seconds
Started Apr 02 12:50:41 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 197032 kb
Host smart-c716f53a-d347-4f9b-befb-c974b5a205a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574093232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.574093232
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.994802591
Short name T398
Test name
Test status
Simulation time 67936550 ps
CPU time 0.89 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 197044 kb
Host smart-305109c1-7d5e-47a0-9453-decd04c01f4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994802591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.994802591
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.119015287
Short name T247
Test name
Test status
Simulation time 125498663 ps
CPU time 1.46 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 197144 kb
Host smart-c707bd20-a17e-40a2-a08b-37fc2c63eb97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119015287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.119015287
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4268923479
Short name T425
Test name
Test status
Simulation time 410088332 ps
CPU time 3.73 seconds
Started Apr 02 12:50:37 PM PDT 24
Finished Apr 02 12:50:41 PM PDT 24
Peak memory 198044 kb
Host smart-8c60a18e-3904-4b36-bd57-f1f5bddace48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268923479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4268923479
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2922907272
Short name T647
Test name
Test status
Simulation time 349602914 ps
CPU time 2.1 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:50:41 PM PDT 24
Peak memory 197128 kb
Host smart-e19ad794-c6be-4d80-be8a-e10d623ebb53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922907272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2922907272
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2272205564
Short name T284
Test name
Test status
Simulation time 49436334 ps
CPU time 1.01 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 195940 kb
Host smart-0aec98ea-f6ae-4b36-ad15-e9b44b922980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272205564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2272205564
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1432879281
Short name T105
Test name
Test status
Simulation time 108055157 ps
CPU time 1.01 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:50:39 PM PDT 24
Peak memory 195980 kb
Host smart-c540cd2f-51e3-499b-940d-d6a2d32ee983
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432879281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1432879281
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3151426988
Short name T424
Test name
Test status
Simulation time 502963440 ps
CPU time 5.89 seconds
Started Apr 02 12:50:41 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 197940 kb
Host smart-bec7baaf-dac1-4895-90f4-c0ae3d857d66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151426988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3151426988
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1225338859
Short name T464
Test name
Test status
Simulation time 85034469 ps
CPU time 0.8 seconds
Started Apr 02 12:50:40 PM PDT 24
Finished Apr 02 12:50:41 PM PDT 24
Peak memory 195912 kb
Host smart-38234acf-ce85-4df5-afc6-ebd57e6087d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225338859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1225338859
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4224546910
Short name T486
Test name
Test status
Simulation time 49416892 ps
CPU time 1.38 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:42 PM PDT 24
Peak memory 196232 kb
Host smart-056d8b32-9635-42cf-8738-934deae92ae3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224546910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4224546910
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.364852085
Short name T405
Test name
Test status
Simulation time 17302815431 ps
CPU time 62.11 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:51:49 PM PDT 24
Peak memory 198200 kb
Host smart-dc780b15-ea83-4fac-b329-4eba5634e23d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364852085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.364852085
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.127441012
Short name T438
Test name
Test status
Simulation time 20832737 ps
CPU time 0.58 seconds
Started Apr 02 12:50:46 PM PDT 24
Finished Apr 02 12:50:47 PM PDT 24
Peak memory 193908 kb
Host smart-6e2e5252-c3c8-484a-a3e3-6e7607c8b9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127441012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.127441012
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.929708513
Short name T253
Test name
Test status
Simulation time 76267919 ps
CPU time 0.65 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 194108 kb
Host smart-6461977f-613b-4d9f-bc05-c6af0d6e909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929708513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.929708513
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.308144292
Short name T117
Test name
Test status
Simulation time 498364842 ps
CPU time 9.61 seconds
Started Apr 02 12:50:42 PM PDT 24
Finished Apr 02 12:50:52 PM PDT 24
Peak memory 196956 kb
Host smart-5487eaa4-0869-4cec-bb18-8aa864d85616
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308144292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.308144292
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1553832636
Short name T3
Test name
Test status
Simulation time 76596438 ps
CPU time 1 seconds
Started Apr 02 12:50:44 PM PDT 24
Finished Apr 02 12:50:45 PM PDT 24
Peak memory 196692 kb
Host smart-eca74c49-a19e-4e03-9e96-aed7b6402672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553832636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1553832636
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.691869519
Short name T404
Test name
Test status
Simulation time 50681568 ps
CPU time 0.72 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:40 PM PDT 24
Peak memory 196224 kb
Host smart-e85fa091-0c1a-4f90-bf43-9b197b333523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691869519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.691869519
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.304295692
Short name T572
Test name
Test status
Simulation time 80796330 ps
CPU time 3.05 seconds
Started Apr 02 12:50:41 PM PDT 24
Finished Apr 02 12:50:45 PM PDT 24
Peak memory 198112 kb
Host smart-498acb8e-7e4a-4b30-8a8f-dd9fcbdb00f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304295692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.304295692
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.99487936
Short name T359
Test name
Test status
Simulation time 804233397 ps
CPU time 3.22 seconds
Started Apr 02 12:50:38 PM PDT 24
Finished Apr 02 12:50:42 PM PDT 24
Peak memory 195824 kb
Host smart-3790f794-131d-44ad-a793-f4dc0813ded8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99487936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.99487936
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3341278995
Short name T374
Test name
Test status
Simulation time 84669427 ps
CPU time 0.69 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 195036 kb
Host smart-f9175c2c-62eb-4756-8417-2a6f7835708e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341278995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3341278995
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3051554396
Short name T338
Test name
Test status
Simulation time 83958716 ps
CPU time 0.91 seconds
Started Apr 02 12:50:40 PM PDT 24
Finished Apr 02 12:50:42 PM PDT 24
Peak memory 195848 kb
Host smart-2b7ef41f-ceb4-483e-8ae0-ecd009e9bde6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051554396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3051554396
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1460683376
Short name T269
Test name
Test status
Simulation time 106188375 ps
CPU time 4.48 seconds
Started Apr 02 12:50:42 PM PDT 24
Finished Apr 02 12:50:47 PM PDT 24
Peak memory 198040 kb
Host smart-8483d6f8-ec48-40d6-a766-eff580dea39d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460683376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1460683376
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1251991211
Short name T195
Test name
Test status
Simulation time 25858798 ps
CPU time 0.7 seconds
Started Apr 02 12:50:37 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 194128 kb
Host smart-3fd3a25d-f38c-4b37-9e48-6840ebd90cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251991211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1251991211
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2758501759
Short name T262
Test name
Test status
Simulation time 41545989 ps
CPU time 1.32 seconds
Started Apr 02 12:50:39 PM PDT 24
Finished Apr 02 12:50:42 PM PDT 24
Peak memory 196652 kb
Host smart-d4f5cb01-0de7-42ca-b6d8-c142b964501e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758501759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2758501759
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.943747465
Short name T7
Test name
Test status
Simulation time 13761125820 ps
CPU time 137.59 seconds
Started Apr 02 12:50:46 PM PDT 24
Finished Apr 02 12:53:04 PM PDT 24
Peak memory 198152 kb
Host smart-ed7f8c85-9e46-4375-96da-2eec6dca15fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943747465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.943747465
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2023582222
Short name T330
Test name
Test status
Simulation time 19764736 ps
CPU time 0.55 seconds
Started Apr 02 12:50:48 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 193908 kb
Host smart-eebcf7d1-2e0d-4b16-9ea2-7ab0683b818d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023582222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2023582222
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1301323007
Short name T422
Test name
Test status
Simulation time 68823081 ps
CPU time 0.72 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 195328 kb
Host smart-d5f64979-939a-407f-a262-936db1a7dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301323007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1301323007
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.571990472
Short name T378
Test name
Test status
Simulation time 4786178698 ps
CPU time 21.19 seconds
Started Apr 02 12:50:44 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 198192 kb
Host smart-7996328a-c4f3-4138-a974-470447270fdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571990472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.571990472
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3590013937
Short name T468
Test name
Test status
Simulation time 56008258 ps
CPU time 0.82 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:53 PM PDT 24
Peak memory 195980 kb
Host smart-8a5e93cc-eeca-40fe-b25a-552748e8f10f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590013937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3590013937
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1707038453
Short name T656
Test name
Test status
Simulation time 46500341 ps
CPU time 0.89 seconds
Started Apr 02 12:50:44 PM PDT 24
Finished Apr 02 12:50:45 PM PDT 24
Peak memory 196408 kb
Host smart-3f4608cc-52f7-4e96-8acc-424146ab3180
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707038453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1707038453
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1281961662
Short name T285
Test name
Test status
Simulation time 346081681 ps
CPU time 3.53 seconds
Started Apr 02 12:50:40 PM PDT 24
Finished Apr 02 12:50:44 PM PDT 24
Peak memory 197928 kb
Host smart-682b50bb-f720-43cf-a067-76ccc803409f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281961662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1281961662
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3332336497
Short name T462
Test name
Test status
Simulation time 128211333 ps
CPU time 3.69 seconds
Started Apr 02 12:50:42 PM PDT 24
Finished Apr 02 12:50:46 PM PDT 24
Peak memory 198088 kb
Host smart-1a2d88c4-5398-40be-b37e-018c4285be9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332336497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3332336497
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1210412890
Short name T479
Test name
Test status
Simulation time 64360949 ps
CPU time 1.21 seconds
Started Apr 02 12:50:42 PM PDT 24
Finished Apr 02 12:50:44 PM PDT 24
Peak memory 195740 kb
Host smart-90b2c600-49b9-40f9-866e-6e7ea93c4b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210412890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1210412890
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1609400751
Short name T225
Test name
Test status
Simulation time 38010234 ps
CPU time 1.43 seconds
Started Apr 02 12:50:43 PM PDT 24
Finished Apr 02 12:50:44 PM PDT 24
Peak memory 198020 kb
Host smart-b4b96679-254e-46ec-8932-f2efd18cfbcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609400751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1609400751
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3866260560
Short name T383
Test name
Test status
Simulation time 198591863 ps
CPU time 2.23 seconds
Started Apr 02 12:50:48 PM PDT 24
Finished Apr 02 12:50:50 PM PDT 24
Peak memory 197992 kb
Host smart-a4102f24-8fce-42e1-828f-2f174a99c767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866260560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3866260560
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3749318542
Short name T278
Test name
Test status
Simulation time 97478251 ps
CPU time 0.84 seconds
Started Apr 02 12:50:41 PM PDT 24
Finished Apr 02 12:50:43 PM PDT 24
Peak memory 195976 kb
Host smart-1572903f-eafb-476f-96b3-2b4a844c15d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749318542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3749318542
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2151034789
Short name T480
Test name
Test status
Simulation time 117588375 ps
CPU time 0.85 seconds
Started Apr 02 12:50:43 PM PDT 24
Finished Apr 02 12:50:44 PM PDT 24
Peak memory 196144 kb
Host smart-913621f1-2602-4aa0-a343-77d54cccf9ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151034789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2151034789
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1603726788
Short name T600
Test name
Test status
Simulation time 59633241974 ps
CPU time 135.44 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:53:08 PM PDT 24
Peak memory 198116 kb
Host smart-f7a25f0d-1d74-4e9e-a1fb-270144cf0dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603726788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1603726788
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4223607880
Short name T599
Test name
Test status
Simulation time 42703308 ps
CPU time 0.55 seconds
Started Apr 02 12:50:49 PM PDT 24
Finished Apr 02 12:50:49 PM PDT 24
Peak memory 194600 kb
Host smart-08a2a386-4e13-4ae3-9c15-91938b6c912e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223607880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4223607880
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2211160548
Short name T408
Test name
Test status
Simulation time 276088292 ps
CPU time 0.74 seconds
Started Apr 02 12:50:50 PM PDT 24
Finished Apr 02 12:50:51 PM PDT 24
Peak memory 194028 kb
Host smart-0cd36a4a-917f-4ef6-8830-55ce0452a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211160548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2211160548
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1510191422
Short name T444
Test name
Test status
Simulation time 1416516963 ps
CPU time 17.91 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 196804 kb
Host smart-7bbe4801-3319-4300-9d16-d1291a5c25b9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510191422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1510191422
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.803177828
Short name T297
Test name
Test status
Simulation time 124821276 ps
CPU time 0.78 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:52 PM PDT 24
Peak memory 196064 kb
Host smart-0084c435-6142-4cac-b08e-81d6d9c7f3df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803177828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.803177828
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2066107269
Short name T206
Test name
Test status
Simulation time 36116290 ps
CPU time 1.09 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 196144 kb
Host smart-4b1a7232-6295-4734-9cae-e8f4c4ec863c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066107269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2066107269
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.728295553
Short name T90
Test name
Test status
Simulation time 101732641 ps
CPU time 2.2 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:53 PM PDT 24
Peak memory 197756 kb
Host smart-98c47f69-9deb-46bb-a472-68fe474f4117
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728295553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.728295553
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1169153869
Short name T673
Test name
Test status
Simulation time 114519462 ps
CPU time 2.68 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 198080 kb
Host smart-6564949f-97b8-4d78-a0ba-438628078b63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169153869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1169153869
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3378395466
Short name T493
Test name
Test status
Simulation time 50725009 ps
CPU time 1.05 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 195808 kb
Host smart-39c5a125-8f06-4be1-99ef-88a7a0aadea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378395466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3378395466
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3861559111
Short name T342
Test name
Test status
Simulation time 803643284 ps
CPU time 1.46 seconds
Started Apr 02 12:50:47 PM PDT 24
Finished Apr 02 12:50:49 PM PDT 24
Peak memory 195772 kb
Host smart-ae4a1358-2c06-406f-91af-242138ea625e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861559111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3861559111
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_smoke.3566544592
Short name T527
Test name
Test status
Simulation time 684237167 ps
CPU time 1.4 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:52 PM PDT 24
Peak memory 197988 kb
Host smart-7e1ed405-28cf-4515-a1af-33252e6b9201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566544592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3566544592
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1519310419
Short name T489
Test name
Test status
Simulation time 98048389 ps
CPU time 1 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:52 PM PDT 24
Peak memory 195720 kb
Host smart-2f43c767-1d78-4b42-b809-53d904c59cb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519310419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1519310419
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3909519714
Short name T414
Test name
Test status
Simulation time 52996010920 ps
CPU time 137.35 seconds
Started Apr 02 12:50:45 PM PDT 24
Finished Apr 02 12:53:03 PM PDT 24
Peak memory 198180 kb
Host smart-300b2aba-cde5-4ffa-a06f-4c648d7ead6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909519714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3909519714
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1393123392
Short name T57
Test name
Test status
Simulation time 13230591812 ps
CPU time 375.4 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:57:09 PM PDT 24
Peak memory 198292 kb
Host smart-96ae8643-876f-499b-b1e6-3f6803552f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1393123392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1393123392
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.728943538
Short name T471
Test name
Test status
Simulation time 13183933 ps
CPU time 0.59 seconds
Started Apr 02 12:49:50 PM PDT 24
Finished Apr 02 12:49:51 PM PDT 24
Peak memory 194580 kb
Host smart-c93db846-31a6-4166-8531-d3c4d30cda85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728943538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.728943538
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2647684222
Short name T644
Test name
Test status
Simulation time 159742430 ps
CPU time 1.01 seconds
Started Apr 02 12:49:48 PM PDT 24
Finished Apr 02 12:49:49 PM PDT 24
Peak memory 196604 kb
Host smart-2c1fc6ad-2cf2-4864-9793-a28b63f604bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647684222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2647684222
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2445391973
Short name T609
Test name
Test status
Simulation time 1069423380 ps
CPU time 27.15 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:50:19 PM PDT 24
Peak memory 197000 kb
Host smart-95561d4d-4c8b-4666-bc02-9f672904708e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445391973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2445391973
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2128367676
Short name T567
Test name
Test status
Simulation time 45275314 ps
CPU time 0.8 seconds
Started Apr 02 12:49:53 PM PDT 24
Finished Apr 02 12:49:54 PM PDT 24
Peak memory 196584 kb
Host smart-6b18b170-24b1-45bc-9fc9-2bd461b83153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128367676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2128367676
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.29477277
Short name T54
Test name
Test status
Simulation time 274768089 ps
CPU time 1.09 seconds
Started Apr 02 12:49:53 PM PDT 24
Finished Apr 02 12:49:54 PM PDT 24
Peak memory 196480 kb
Host smart-98c0659c-bf91-4135-b4e4-88ee8c27d248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29477277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.29477277
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.426249770
Short name T499
Test name
Test status
Simulation time 142334507 ps
CPU time 2.84 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:49:54 PM PDT 24
Peak memory 196340 kb
Host smart-29c38a2f-af6c-44d0-add4-167834325f6b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426249770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.426249770
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3012389155
Short name T401
Test name
Test status
Simulation time 106670131 ps
CPU time 3.03 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:49:54 PM PDT 24
Peak memory 195812 kb
Host smart-d83527e8-81fc-4e9a-9da3-25966d92d924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012389155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3012389155
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4276823348
Short name T196
Test name
Test status
Simulation time 27771529 ps
CPU time 0.82 seconds
Started Apr 02 12:49:46 PM PDT 24
Finished Apr 02 12:49:47 PM PDT 24
Peak memory 196160 kb
Host smart-ebc6aafa-d9d4-42b8-be13-aa76c4b521a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276823348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4276823348
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1552996385
Short name T224
Test name
Test status
Simulation time 49569291 ps
CPU time 1.14 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 195804 kb
Host smart-b0223eed-6323-41f9-a3dd-0aae554d78a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552996385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1552996385
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3385608168
Short name T20
Test name
Test status
Simulation time 122618357 ps
CPU time 1.16 seconds
Started Apr 02 12:49:53 PM PDT 24
Finished Apr 02 12:49:54 PM PDT 24
Peak memory 196536 kb
Host smart-7c348a3b-052c-4298-a66a-e4dba153a846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385608168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3385608168
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2371717178
Short name T51
Test name
Test status
Simulation time 70076325 ps
CPU time 0.9 seconds
Started Apr 02 12:49:51 PM PDT 24
Finished Apr 02 12:49:52 PM PDT 24
Peak memory 213696 kb
Host smart-9dd31ab3-aa20-4bc6-86ea-27f4f7c272bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371717178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2371717178
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2332608596
Short name T298
Test name
Test status
Simulation time 211280585 ps
CPU time 0.99 seconds
Started Apr 02 12:49:49 PM PDT 24
Finished Apr 02 12:49:50 PM PDT 24
Peak memory 195784 kb
Host smart-9481a3c1-f8f6-4f09-94fc-c92b3eff7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332608596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2332608596
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2681777283
Short name T576
Test name
Test status
Simulation time 76958534 ps
CPU time 1.14 seconds
Started Apr 02 12:49:47 PM PDT 24
Finished Apr 02 12:49:48 PM PDT 24
Peak memory 196476 kb
Host smart-b327fde7-a549-4672-9715-22dcb67ff195
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681777283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2681777283
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1063603294
Short name T270
Test name
Test status
Simulation time 234106393800 ps
CPU time 200.87 seconds
Started Apr 02 12:49:53 PM PDT 24
Finished Apr 02 12:53:14 PM PDT 24
Peak memory 198220 kb
Host smart-ae1710c6-e917-4ad3-8f8f-72e57ee108bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063603294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1063603294
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2696758101
Short name T120
Test name
Test status
Simulation time 13764787 ps
CPU time 0.59 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 194636 kb
Host smart-982dc72c-5566-44c1-b9ed-26e1f45d1bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696758101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2696758101
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.805083503
Short name T584
Test name
Test status
Simulation time 26851615 ps
CPU time 0.75 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 196036 kb
Host smart-436f6689-50ba-4288-82b6-41ff516b271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805083503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.805083503
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1547380358
Short name T154
Test name
Test status
Simulation time 2035580369 ps
CPU time 26.09 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 196720 kb
Host smart-852acb07-8670-4e2c-b5f3-8dc3e36356e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547380358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1547380358
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.4054301071
Short name T33
Test name
Test status
Simulation time 175217679 ps
CPU time 0.76 seconds
Started Apr 02 12:50:54 PM PDT 24
Finished Apr 02 12:50:56 PM PDT 24
Peak memory 195800 kb
Host smart-9db11c25-4c9a-4fb9-ade9-3314d88964f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054301071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.4054301071
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2875717784
Short name T112
Test name
Test status
Simulation time 102497231 ps
CPU time 1.35 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:55 PM PDT 24
Peak memory 197104 kb
Host smart-643088db-c4af-41a6-80d9-139d75bc0f7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875717784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2875717784
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.590566493
Short name T215
Test name
Test status
Simulation time 95239259 ps
CPU time 3.25 seconds
Started Apr 02 12:50:50 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 198068 kb
Host smart-936efaed-c871-4514-a5c7-1cdef1740da9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590566493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.590566493
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1890347485
Short name T390
Test name
Test status
Simulation time 94267001 ps
CPU time 2.1 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 198040 kb
Host smart-01243cbd-e35a-4e1e-a3b5-a9c179106f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890347485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1890347485
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2355014097
Short name T612
Test name
Test status
Simulation time 28045259 ps
CPU time 0.79 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 196216 kb
Host smart-df2e8507-a4bf-4729-80b4-9d7197cad6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355014097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2355014097
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.748156945
Short name T703
Test name
Test status
Simulation time 33165180 ps
CPU time 0.85 seconds
Started Apr 02 12:50:46 PM PDT 24
Finished Apr 02 12:50:48 PM PDT 24
Peak memory 196620 kb
Host smart-c8ff7432-517d-4086-8f7b-78482f95d1f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748156945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.748156945
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2155720965
Short name T370
Test name
Test status
Simulation time 265154424 ps
CPU time 4.61 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:09 PM PDT 24
Peak memory 197980 kb
Host smart-4607069b-0494-4aa2-b8ff-c52c2287c869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155720965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2155720965
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1986608764
Short name T163
Test name
Test status
Simulation time 126045769 ps
CPU time 1 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:52 PM PDT 24
Peak memory 196356 kb
Host smart-a22fcc1c-f7f9-4d25-a0cd-f8a25b56bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986608764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1986608764
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3633637046
Short name T626
Test name
Test status
Simulation time 66837897 ps
CPU time 1.05 seconds
Started Apr 02 12:50:46 PM PDT 24
Finished Apr 02 12:50:47 PM PDT 24
Peak memory 195660 kb
Host smart-c4dd822c-caa9-4583-b8be-5a8f0ed77009
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633637046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3633637046
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1231623059
Short name T21
Test name
Test status
Simulation time 166046997344 ps
CPU time 213.41 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:54:30 PM PDT 24
Peak memory 198144 kb
Host smart-a06747f3-acb9-4857-8032-4db2cce10398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231623059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1231623059
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3602154738
Short name T603
Test name
Test status
Simulation time 377575560960 ps
CPU time 2230.12 seconds
Started Apr 02 12:50:54 PM PDT 24
Finished Apr 02 01:28:06 PM PDT 24
Peak memory 198244 kb
Host smart-ee424246-2966-4ee4-925a-38363f03a61b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3602154738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3602154738
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1154499048
Short name T483
Test name
Test status
Simulation time 15202048 ps
CPU time 0.58 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:56 PM PDT 24
Peak memory 194588 kb
Host smart-0c16a6b9-535b-47b7-a342-2ede3f797fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154499048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1154499048
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1020890923
Short name T288
Test name
Test status
Simulation time 103803249 ps
CPU time 0.85 seconds
Started Apr 02 12:50:57 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 197204 kb
Host smart-c488673b-5a1e-41d1-832b-f23c2dacb544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020890923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1020890923
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2737015583
Short name T193
Test name
Test status
Simulation time 406479201 ps
CPU time 6.51 seconds
Started Apr 02 12:50:50 PM PDT 24
Finished Apr 02 12:50:56 PM PDT 24
Peak memory 197976 kb
Host smart-8c858513-5dc5-4d8d-96ba-ac7cc5468062
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737015583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2737015583
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1100980476
Short name T22
Test name
Test status
Simulation time 135839155 ps
CPU time 0.87 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 197228 kb
Host smart-c54d1298-8238-42ad-8349-24432b42e045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100980476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1100980476
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3792176466
Short name T665
Test name
Test status
Simulation time 73128203 ps
CPU time 0.78 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:58 PM PDT 24
Peak memory 195152 kb
Host smart-7c94590a-00c2-4e24-9d5f-27591837a5f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792176466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3792176466
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1655620965
Short name T456
Test name
Test status
Simulation time 163302202 ps
CPU time 1.67 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:53 PM PDT 24
Peak memory 196732 kb
Host smart-e53ced8e-79e8-4aa0-8c13-d280e1e533bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655620965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1655620965
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.146153582
Short name T189
Test name
Test status
Simulation time 1474595323 ps
CPU time 2.44 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 195844 kb
Host smart-bdfb5ed2-3b12-4744-b621-aa4b0b021f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146153582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
146153582
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3170026777
Short name T638
Test name
Test status
Simulation time 39427274 ps
CPU time 0.92 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:55 PM PDT 24
Peak memory 196524 kb
Host smart-a5bb8fa8-de64-46e2-a6cc-4154454859b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170026777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3170026777
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3847217245
Short name T417
Test name
Test status
Simulation time 198308097 ps
CPU time 1.27 seconds
Started Apr 02 12:50:51 PM PDT 24
Finished Apr 02 12:50:53 PM PDT 24
Peak memory 197960 kb
Host smart-083f4733-47d9-428c-ab69-ce2fd205efd0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847217245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3847217245
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2063996204
Short name T28
Test name
Test status
Simulation time 156930459 ps
CPU time 2.85 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 198020 kb
Host smart-2c380330-e8ef-4bf6-9662-656e91ed811e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063996204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2063996204
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2242999941
Short name T344
Test name
Test status
Simulation time 85796433 ps
CPU time 1.42 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 197952 kb
Host smart-f213fed2-93d4-4901-94dd-af8727c7cb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242999941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2242999941
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3228820644
Short name T577
Test name
Test status
Simulation time 261573472 ps
CPU time 1.33 seconds
Started Apr 02 12:50:52 PM PDT 24
Finished Apr 02 12:50:55 PM PDT 24
Peak memory 196372 kb
Host smart-3d68a90d-4eb3-4b15-8368-a7e075052349
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228820644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3228820644
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4081252675
Short name T450
Test name
Test status
Simulation time 19593398225 ps
CPU time 45.8 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:51:41 PM PDT 24
Peak memory 198160 kb
Host smart-ddaec300-cb9d-4d37-b437-1b409566dae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081252675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4081252675
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3894552029
Short name T364
Test name
Test status
Simulation time 14265314 ps
CPU time 0.57 seconds
Started Apr 02 12:51:08 PM PDT 24
Finished Apr 02 12:51:09 PM PDT 24
Peak memory 193888 kb
Host smart-e3f3c824-bb87-408b-8bb8-03f7c670c542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894552029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3894552029
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2687020270
Short name T356
Test name
Test status
Simulation time 53135680 ps
CPU time 0.8 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:50:54 PM PDT 24
Peak memory 195172 kb
Host smart-7221e38a-6387-42a2-a48a-7d317315b561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687020270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2687020270
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3369050138
Short name T146
Test name
Test status
Simulation time 1315002101 ps
CPU time 23 seconds
Started Apr 02 12:50:53 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 197968 kb
Host smart-813f6ab4-7f2f-43dc-9002-5e8746372503
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369050138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3369050138
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2545432698
Short name T514
Test name
Test status
Simulation time 118337652 ps
CPU time 0.68 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 194540 kb
Host smart-9e127071-6a32-4e9d-a54b-6ce802be11f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545432698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2545432698
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3156899870
Short name T415
Test name
Test status
Simulation time 55051864 ps
CPU time 1.05 seconds
Started Apr 02 12:50:54 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 195796 kb
Host smart-1e2a41f4-a45d-424c-a0f5-803721866a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156899870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3156899870
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3220284499
Short name T282
Test name
Test status
Simulation time 270487005 ps
CPU time 2.14 seconds
Started Apr 02 12:50:57 PM PDT 24
Finished Apr 02 12:51:00 PM PDT 24
Peak memory 197900 kb
Host smart-7daa8cba-4d3d-455d-9b6f-bdf41a110662
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220284499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3220284499
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.203663042
Short name T492
Test name
Test status
Simulation time 119521091 ps
CPU time 2.56 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 196488 kb
Host smart-73aac5e3-2562-47be-a957-00d01de4fdb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203663042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
203663042
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.195302025
Short name T430
Test name
Test status
Simulation time 19950286 ps
CPU time 0.67 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:58 PM PDT 24
Peak memory 194992 kb
Host smart-afa5fdfd-8d7b-439d-9245-ca408be6eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195302025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.195302025
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3434920506
Short name T652
Test name
Test status
Simulation time 49186821 ps
CPU time 1.11 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:58 PM PDT 24
Peak memory 196132 kb
Host smart-49876772-0f38-45c2-93b2-3d6abcc2855e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434920506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3434920506
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3075772981
Short name T10
Test name
Test status
Simulation time 314135529 ps
CPU time 4.01 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:51:01 PM PDT 24
Peak memory 197948 kb
Host smart-c5a97210-7c43-4e5e-ad48-8ac6cfd04d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075772981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3075772981
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2508901315
Short name T552
Test name
Test status
Simulation time 193129731 ps
CPU time 0.98 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:03 PM PDT 24
Peak memory 195688 kb
Host smart-c269125b-7d5f-489c-abd4-70b6b3295697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508901315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2508901315
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3821663477
Short name T197
Test name
Test status
Simulation time 70354047 ps
CPU time 1.32 seconds
Started Apr 02 12:50:54 PM PDT 24
Finished Apr 02 12:50:57 PM PDT 24
Peak memory 195848 kb
Host smart-7e4db6db-5ba0-4b4b-81ab-f448a003f428
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821663477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3821663477
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1507624847
Short name T434
Test name
Test status
Simulation time 8246661468 ps
CPU time 50.62 seconds
Started Apr 02 12:50:58 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 198176 kb
Host smart-1ab166b8-e24f-42f2-b7d1-c5fde0492700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507624847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1507624847
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.181871394
Short name T180
Test name
Test status
Simulation time 42352008 ps
CPU time 0.55 seconds
Started Apr 02 12:50:58 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 193856 kb
Host smart-693434cd-2202-4c0e-a95a-cbc4a321e784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181871394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.181871394
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2768134625
Short name T300
Test name
Test status
Simulation time 19160594 ps
CPU time 0.7 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 194128 kb
Host smart-682edc68-5509-4af8-9ab6-d3a98904b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768134625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2768134625
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4093451662
Short name T697
Test name
Test status
Simulation time 157493449 ps
CPU time 8.2 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 197992 kb
Host smart-b1904e68-4902-4e9a-b9dd-0e26cdc62aa2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093451662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4093451662
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3707215248
Short name T121
Test name
Test status
Simulation time 60197402 ps
CPU time 0.95 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:03 PM PDT 24
Peak memory 196552 kb
Host smart-6ed5ac58-2be9-4262-b92b-3d3285ba1948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707215248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3707215248
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.283576559
Short name T273
Test name
Test status
Simulation time 1020251933 ps
CPU time 1.44 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:02 PM PDT 24
Peak memory 197236 kb
Host smart-50bf7f44-51f2-44d1-a4e9-2b3b80c504b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283576559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.283576559
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1625646859
Short name T230
Test name
Test status
Simulation time 31329486 ps
CPU time 1.23 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 196668 kb
Host smart-e0b9f706-c3d4-4351-8532-7f35df1a5ba5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625646859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1625646859
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3184865127
Short name T371
Test name
Test status
Simulation time 48038783 ps
CPU time 1.55 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 196080 kb
Host smart-045640a1-6e73-4e77-b3c3-9c6f394604af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184865127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3184865127
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.77729496
Short name T452
Test name
Test status
Simulation time 45595044 ps
CPU time 1.02 seconds
Started Apr 02 12:50:58 PM PDT 24
Finished Apr 02 12:51:01 PM PDT 24
Peak memory 195900 kb
Host smart-9e552586-a432-48e1-a686-4362d6441172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77729496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.77729496
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.123967389
Short name T101
Test name
Test status
Simulation time 319238089 ps
CPU time 1.21 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 197148 kb
Host smart-a7f0996a-6e6f-48c7-9e21-d3d8920302eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123967389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.123967389
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3739029600
Short name T407
Test name
Test status
Simulation time 1226287912 ps
CPU time 4.51 seconds
Started Apr 02 12:50:55 PM PDT 24
Finished Apr 02 12:51:00 PM PDT 24
Peak memory 197984 kb
Host smart-003f4ad2-ccdb-4f3c-b41f-bfd826c9c1a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739029600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3739029600
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.351726307
Short name T95
Test name
Test status
Simulation time 57137034 ps
CPU time 1 seconds
Started Apr 02 12:50:56 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 197340 kb
Host smart-87468aec-569d-446a-a333-86e31da1626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351726307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.351726307
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.578543798
Short name T183
Test name
Test status
Simulation time 89166803 ps
CPU time 1.03 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 196392 kb
Host smart-f693b8e2-f0f7-43c8-b102-4e0598985e9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578543798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.578543798
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1658163234
Short name T2
Test name
Test status
Simulation time 24073332820 ps
CPU time 103.7 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:52:44 PM PDT 24
Peak memory 198156 kb
Host smart-ea5cd456-84dc-4d8f-81cb-e5a50543e3ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658163234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1658163234
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1392734444
Short name T561
Test name
Test status
Simulation time 88046199 ps
CPU time 0.57 seconds
Started Apr 02 12:51:08 PM PDT 24
Finished Apr 02 12:51:09 PM PDT 24
Peak memory 193928 kb
Host smart-1c6825c6-9d37-4300-b675-31d4284ec00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392734444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1392734444
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3448274892
Short name T258
Test name
Test status
Simulation time 25801429 ps
CPU time 0.7 seconds
Started Apr 02 12:50:57 PM PDT 24
Finished Apr 02 12:50:59 PM PDT 24
Peak memory 195216 kb
Host smart-2678f8f9-dd7d-443b-84e9-c238256d8be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448274892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3448274892
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.32697773
Short name T540
Test name
Test status
Simulation time 226383166 ps
CPU time 7.85 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:10 PM PDT 24
Peak memory 196680 kb
Host smart-4e50b185-a4ac-4796-a8ef-34b4bb0515b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32697773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stress
.32697773
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3619289335
Short name T124
Test name
Test status
Simulation time 61055872 ps
CPU time 0.75 seconds
Started Apr 02 12:51:02 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 194900 kb
Host smart-709b7046-e899-47eb-ac80-0a1a6d9d3019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619289335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3619289335
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1442448741
Short name T294
Test name
Test status
Simulation time 84797370 ps
CPU time 1.19 seconds
Started Apr 02 12:50:58 PM PDT 24
Finished Apr 02 12:51:01 PM PDT 24
Peak memory 195728 kb
Host smart-e4ac52e6-bb9f-41af-bd86-6c0162ee7f29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442448741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1442448741
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.986609566
Short name T316
Test name
Test status
Simulation time 440687061 ps
CPU time 1.13 seconds
Started Apr 02 12:50:58 PM PDT 24
Finished Apr 02 12:51:00 PM PDT 24
Peak memory 197592 kb
Host smart-35a61293-bdd5-41c8-a2ad-f9ae4ae06dec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986609566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.986609566
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2070159244
Short name T135
Test name
Test status
Simulation time 186302661 ps
CPU time 2.42 seconds
Started Apr 02 12:50:57 PM PDT 24
Finished Apr 02 12:51:01 PM PDT 24
Peak memory 197120 kb
Host smart-94687d83-c1a3-4490-a691-87077f488cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070159244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2070159244
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1266661623
Short name T217
Test name
Test status
Simulation time 113833095 ps
CPU time 1.37 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:02 PM PDT 24
Peak memory 197956 kb
Host smart-a16c7664-42c9-4bbf-b1ee-113dde3e477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266661623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1266661623
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1420274941
Short name T574
Test name
Test status
Simulation time 187138456 ps
CPU time 0.63 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:02 PM PDT 24
Peak memory 194316 kb
Host smart-7d7cb104-0759-471a-9430-2cee6478a41c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420274941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1420274941
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4092784189
Short name T620
Test name
Test status
Simulation time 1616806918 ps
CPU time 4.03 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 197840 kb
Host smart-50268562-a845-4508-b780-e57cc58c3d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092784189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4092784189
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1890125121
Short name T336
Test name
Test status
Simulation time 65824097 ps
CPU time 1.19 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 195600 kb
Host smart-d705dcb9-01d6-47d3-ad10-6ddafddda9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890125121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1890125121
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2624381105
Short name T531
Test name
Test status
Simulation time 116584194 ps
CPU time 0.98 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:03 PM PDT 24
Peak memory 195596 kb
Host smart-30f50ca9-0529-428d-b84f-102f9eeadb1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624381105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2624381105
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3672764967
Short name T128
Test name
Test status
Simulation time 5141014535 ps
CPU time 27.64 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:30 PM PDT 24
Peak memory 198136 kb
Host smart-0550aa4d-07e9-4c6a-b097-edb2b3aff16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672764967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3672764967
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1623481632
Short name T172
Test name
Test status
Simulation time 13954003 ps
CPU time 0.59 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 194000 kb
Host smart-2a071706-b973-4226-a1ea-bbab06c0ada2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623481632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1623481632
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2011996166
Short name T31
Test name
Test status
Simulation time 30759354 ps
CPU time 0.82 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 195332 kb
Host smart-a437dca7-c4ee-4ca2-8580-ad8ba72699ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011996166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2011996166
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.500735165
Short name T320
Test name
Test status
Simulation time 852911376 ps
CPU time 7.38 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:10 PM PDT 24
Peak memory 196892 kb
Host smart-cc147880-2e79-4119-8142-afcb3a0dfbb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500735165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.500735165
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1937425812
Short name T12
Test name
Test status
Simulation time 79994820 ps
CPU time 0.96 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 196120 kb
Host smart-858b0c25-6bc4-4ae8-9ff8-945ae94d0ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937425812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1937425812
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2824170494
Short name T190
Test name
Test status
Simulation time 123319639 ps
CPU time 0.74 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 196160 kb
Host smart-58ccadb3-b2d2-401b-b585-2feef667cf36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824170494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2824170494
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3178513725
Short name T446
Test name
Test status
Simulation time 83192088 ps
CPU time 1.79 seconds
Started Apr 02 12:51:00 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 196780 kb
Host smart-bfee699b-ea4c-406c-8ced-0ffdb273b4bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178513725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3178513725
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1478821979
Short name T194
Test name
Test status
Simulation time 84702318 ps
CPU time 2.15 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 195892 kb
Host smart-823fa557-f9d6-4a70-b7cd-ea3ab37c5019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478821979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1478821979
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3402314788
Short name T416
Test name
Test status
Simulation time 38266532 ps
CPU time 0.85 seconds
Started Apr 02 12:51:02 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 195516 kb
Host smart-0b1555e9-9f3c-4497-b6d3-e734805d3a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402314788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3402314788
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3555152926
Short name T239
Test name
Test status
Simulation time 30653239 ps
CPU time 0.77 seconds
Started Apr 02 12:51:02 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 195568 kb
Host smart-f7b7924e-8c68-4d3a-baec-1a5a6c3a5083
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555152926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3555152926
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4050836009
Short name T473
Test name
Test status
Simulation time 120586900 ps
CPU time 2.07 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 197192 kb
Host smart-3e2f107c-814f-49d6-8a9b-2d4a8bb32c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050836009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4050836009
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1218035642
Short name T100
Test name
Test status
Simulation time 138937674 ps
CPU time 1.15 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 195704 kb
Host smart-14cd4ca3-c4b7-41b4-a53d-f29b24bd3b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218035642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1218035642
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1533431921
Short name T583
Test name
Test status
Simulation time 74059759 ps
CPU time 1.37 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 196776 kb
Host smart-0e0782fd-322b-4697-bc92-338dd17bf489
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533431921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1533431921
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.120641936
Short name T448
Test name
Test status
Simulation time 10324200634 ps
CPU time 91.69 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:52:44 PM PDT 24
Peak memory 198152 kb
Host smart-a17fb716-435d-4f6d-bd7b-152facc5ef98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120641936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.120641936
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1597948601
Short name T605
Test name
Test status
Simulation time 196073656543 ps
CPU time 1110.52 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 01:09:34 PM PDT 24
Peak memory 198200 kb
Host smart-834e18a4-9282-4bdf-a0bf-3758cc81270b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1597948601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1597948601
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2964838055
Short name T351
Test name
Test status
Simulation time 12385461 ps
CPU time 0.56 seconds
Started Apr 02 12:51:04 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 193528 kb
Host smart-6f6a04b3-11b1-4291-a349-be0c7bd5a514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964838055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2964838055
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3579907821
Short name T475
Test name
Test status
Simulation time 159824506 ps
CPU time 0.87 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 196428 kb
Host smart-3abaf70e-8b7e-40a2-81ee-dc2ba7417c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579907821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3579907821
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1644686576
Short name T643
Test name
Test status
Simulation time 369412885 ps
CPU time 19.1 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 197988 kb
Host smart-5198fcc5-e2aa-4ad0-af44-2d14c61887ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644686576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1644686576
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3438205218
Short name T677
Test name
Test status
Simulation time 61752766 ps
CPU time 0.94 seconds
Started Apr 02 12:51:04 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 196516 kb
Host smart-d9975fa1-e01b-49b6-aa18-a64d47a2c0ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438205218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3438205218
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2154189233
Short name T575
Test name
Test status
Simulation time 58457952 ps
CPU time 0.68 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 195100 kb
Host smart-f215a5cf-0128-4350-bcfe-250616ed994e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154189233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2154189233
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1883373796
Short name T140
Test name
Test status
Simulation time 185139223 ps
CPU time 3.25 seconds
Started Apr 02 12:50:59 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 197976 kb
Host smart-f68aed7a-6856-425c-adc3-982cd4b7a88e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883373796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1883373796
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.712545646
Short name T481
Test name
Test status
Simulation time 228857581 ps
CPU time 3.56 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:07 PM PDT 24
Peak memory 197904 kb
Host smart-2e267c79-83c2-4d20-8de7-2890298e8449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712545646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
712545646
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2022595510
Short name T286
Test name
Test status
Simulation time 37634408 ps
CPU time 0.71 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 195012 kb
Host smart-50748c7f-0271-4a2d-8fcc-9a24739f2e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022595510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2022595510
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.177925330
Short name T185
Test name
Test status
Simulation time 121991495 ps
CPU time 0.9 seconds
Started Apr 02 12:51:01 PM PDT 24
Finished Apr 02 12:51:04 PM PDT 24
Peak memory 195932 kb
Host smart-5d6be350-9a47-405b-91de-f38a129b2c76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177925330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.177925330
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1004546121
Short name T14
Test name
Test status
Simulation time 58982719 ps
CPU time 2.92 seconds
Started Apr 02 12:51:03 PM PDT 24
Finished Apr 02 12:51:07 PM PDT 24
Peak memory 197912 kb
Host smart-957d14a8-c159-47e9-b0c0-0dc92fa2db77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004546121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1004546121
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3162419131
Short name T15
Test name
Test status
Simulation time 55588154 ps
CPU time 0.95 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:12 PM PDT 24
Peak memory 195460 kb
Host smart-fb9a8f23-7c59-4e0d-b512-980815b1d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162419131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3162419131
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2790656676
Short name T136
Test name
Test status
Simulation time 79882153 ps
CPU time 1.29 seconds
Started Apr 02 12:51:02 PM PDT 24
Finished Apr 02 12:51:05 PM PDT 24
Peak memory 195776 kb
Host smart-6e721577-b5be-4826-818a-588677e5d9ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790656676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2790656676
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1359492128
Short name T541
Test name
Test status
Simulation time 2298038013 ps
CPU time 26.41 seconds
Started Apr 02 12:51:04 PM PDT 24
Finished Apr 02 12:51:31 PM PDT 24
Peak memory 198176 kb
Host smart-7d15dbd5-601e-4f42-bc03-64780f49ff07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359492128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1359492128
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2014759494
Short name T380
Test name
Test status
Simulation time 14901583 ps
CPU time 0.59 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:12 PM PDT 24
Peak memory 194560 kb
Host smart-99724444-6b4b-4629-bde2-ecb5b92ca9a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014759494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2014759494
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2448585826
Short name T686
Test name
Test status
Simulation time 25504223 ps
CPU time 0.64 seconds
Started Apr 02 12:51:05 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 194012 kb
Host smart-8da16da7-793b-41f2-b2b4-bf65bb8e4f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448585826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2448585826
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2468964046
Short name T503
Test name
Test status
Simulation time 396249748 ps
CPU time 3.64 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 195712 kb
Host smart-6c9cec29-64af-4d5b-a73c-c3a8f8c9c486
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468964046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2468964046
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.841508820
Short name T143
Test name
Test status
Simulation time 324239719 ps
CPU time 1 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 196624 kb
Host smart-270533c8-0c12-42c6-8433-a0484240087e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841508820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.841508820
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.191194003
Short name T363
Test name
Test status
Simulation time 788062674 ps
CPU time 1.29 seconds
Started Apr 02 12:51:05 PM PDT 24
Finished Apr 02 12:51:07 PM PDT 24
Peak memory 195968 kb
Host smart-c0fafadb-d1aa-43f2-9110-defa13aed34b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191194003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.191194003
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2599684232
Short name T402
Test name
Test status
Simulation time 74918281 ps
CPU time 2.98 seconds
Started Apr 02 12:51:02 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 198036 kb
Host smart-49e12c6f-13cb-4bc0-82dd-65462a01e03f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599684232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2599684232
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.972867811
Short name T205
Test name
Test status
Simulation time 189243429 ps
CPU time 3.52 seconds
Started Apr 02 12:51:07 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 197108 kb
Host smart-020a0d9b-b284-4745-a6de-4bb39c0fb45f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972867811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
972867811
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4273336010
Short name T147
Test name
Test status
Simulation time 180177788 ps
CPU time 1.11 seconds
Started Apr 02 12:51:05 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 196092 kb
Host smart-7c5749a2-feef-407b-ad31-b528e785f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273336010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4273336010
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3900467379
Short name T439
Test name
Test status
Simulation time 31670290 ps
CPU time 0.86 seconds
Started Apr 02 12:51:05 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 196520 kb
Host smart-94b667d9-98d6-494d-9b5c-88ea3c3cfce3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900467379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3900467379
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4175976387
Short name T399
Test name
Test status
Simulation time 357217142 ps
CPU time 1.6 seconds
Started Apr 02 12:51:04 PM PDT 24
Finished Apr 02 12:51:07 PM PDT 24
Peak memory 197964 kb
Host smart-cf345ea6-7a16-406d-8453-e3c835b338aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175976387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4175976387
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.810460088
Short name T259
Test name
Test status
Simulation time 345114410 ps
CPU time 1.58 seconds
Started Apr 02 12:51:06 PM PDT 24
Finished Apr 02 12:51:08 PM PDT 24
Peak memory 196828 kb
Host smart-ad6acb8f-9669-46b4-bde4-1ee8609642a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810460088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.810460088
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4256021793
Short name T511
Test name
Test status
Simulation time 40435421 ps
CPU time 0.89 seconds
Started Apr 02 12:51:04 PM PDT 24
Finished Apr 02 12:51:06 PM PDT 24
Peak memory 195380 kb
Host smart-8b2040f9-837c-4bdb-a41c-647c09dcf45e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256021793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4256021793
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2800060648
Short name T580
Test name
Test status
Simulation time 20514212074 ps
CPU time 219.2 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:54:52 PM PDT 24
Peak memory 198228 kb
Host smart-07e51f6e-47d9-4a47-991f-93ba54993ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800060648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2800060648
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1523494783
Short name T655
Test name
Test status
Simulation time 19980258 ps
CPU time 0.56 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:15 PM PDT 24
Peak memory 193948 kb
Host smart-c2e1b60b-c8aa-44da-9599-e75c6cec0e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523494783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1523494783
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4234645777
Short name T106
Test name
Test status
Simulation time 109222295 ps
CPU time 0.93 seconds
Started Apr 02 12:51:08 PM PDT 24
Finished Apr 02 12:51:10 PM PDT 24
Peak memory 197300 kb
Host smart-41a9f83b-f6cc-4925-b436-569bd79b6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234645777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4234645777
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.951506130
Short name T550
Test name
Test status
Simulation time 1084919362 ps
CPU time 20.27 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 196880 kb
Host smart-9faf8809-4a62-458f-8131-f7c2134faaf0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951506130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.951506130
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3625889276
Short name T307
Test name
Test status
Simulation time 48244946 ps
CPU time 0.77 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:51:13 PM PDT 24
Peak memory 196700 kb
Host smart-d1122861-40fd-48a1-8a43-8b41d09216ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625889276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3625889276
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.120140397
Short name T482
Test name
Test status
Simulation time 36613272 ps
CPU time 0.99 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:12 PM PDT 24
Peak memory 195920 kb
Host smart-f82b96e8-813b-4cb9-b686-841e9082f5d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120140397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.120140397
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.138374921
Short name T203
Test name
Test status
Simulation time 251292982 ps
CPU time 2.55 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 198108 kb
Host smart-22f280e6-1804-48d3-a51e-104e40ebc838
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138374921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.138374921
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1991319854
Short name T624
Test name
Test status
Simulation time 312195796 ps
CPU time 2.41 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:13 PM PDT 24
Peak memory 197916 kb
Host smart-39d07a66-dab6-4b25-abae-d73e06dda069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991319854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1991319854
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3073846422
Short name T628
Test name
Test status
Simulation time 93168502 ps
CPU time 0.92 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 195944 kb
Host smart-249bc4ac-7687-4ac2-9693-d2023f9cad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073846422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3073846422
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1459633546
Short name T24
Test name
Test status
Simulation time 34775939 ps
CPU time 0.88 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:11 PM PDT 24
Peak memory 196672 kb
Host smart-37499deb-3ec1-444e-8cef-ba5e43ef1626
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459633546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1459633546
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3903494282
Short name T256
Test name
Test status
Simulation time 1398728128 ps
CPU time 6.19 seconds
Started Apr 02 12:51:13 PM PDT 24
Finished Apr 02 12:51:20 PM PDT 24
Peak memory 197896 kb
Host smart-0df3a8b9-f1ec-4b3d-b5bd-05d3b144a8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903494282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3903494282
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4153226607
Short name T660
Test name
Test status
Simulation time 88148732 ps
CPU time 0.92 seconds
Started Apr 02 12:51:09 PM PDT 24
Finished Apr 02 12:51:10 PM PDT 24
Peak memory 196388 kb
Host smart-6d68dfcd-0883-4f72-81b5-58f068d822cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153226607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4153226607
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.714540152
Short name T129
Test name
Test status
Simulation time 167234983 ps
CPU time 1.25 seconds
Started Apr 02 12:51:09 PM PDT 24
Finished Apr 02 12:51:10 PM PDT 24
Peak memory 196848 kb
Host smart-8619ee3b-e2c0-4ccc-a54a-25d092350606
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714540152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.714540152
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1588395658
Short name T601
Test name
Test status
Simulation time 15389793437 ps
CPU time 58.07 seconds
Started Apr 02 12:51:11 PM PDT 24
Finished Apr 02 12:52:10 PM PDT 24
Peak memory 198196 kb
Host smart-6a11fffe-283f-4538-9367-947b2bcaf012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588395658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1588395658
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3332756156
Short name T61
Test name
Test status
Simulation time 158000994840 ps
CPU time 1003.31 seconds
Started Apr 02 12:51:13 PM PDT 24
Finished Apr 02 01:07:56 PM PDT 24
Peak memory 198288 kb
Host smart-b6cd4a76-24bc-4224-86c7-4a094fd12970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3332756156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3332756156
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3496674958
Short name T231
Test name
Test status
Simulation time 20707716 ps
CPU time 0.57 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 193896 kb
Host smart-3eba7555-92e9-44bd-85f9-682e7648a768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496674958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3496674958
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3384467139
Short name T381
Test name
Test status
Simulation time 36844883 ps
CPU time 0.63 seconds
Started Apr 02 12:51:13 PM PDT 24
Finished Apr 02 12:51:14 PM PDT 24
Peak memory 193928 kb
Host smart-5c237536-8c39-4674-abab-30f54a13c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384467139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3384467139
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3325501715
Short name T622
Test name
Test status
Simulation time 618449448 ps
CPU time 15.64 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:30 PM PDT 24
Peak memory 195584 kb
Host smart-58ebc468-fa88-468e-8adf-18f6cc936c43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325501715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3325501715
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.708135914
Short name T524
Test name
Test status
Simulation time 57966802 ps
CPU time 0.69 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:15 PM PDT 24
Peak memory 195488 kb
Host smart-78147871-e699-46b4-afc1-9a2faaf012ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708135914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.708135914
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.404670516
Short name T520
Test name
Test status
Simulation time 177017928 ps
CPU time 1.16 seconds
Started Apr 02 12:51:11 PM PDT 24
Finished Apr 02 12:51:13 PM PDT 24
Peak memory 197216 kb
Host smart-93b18b66-8b5d-4d38-ac82-1ddd98b62aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404670516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.404670516
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4112810601
Short name T160
Test name
Test status
Simulation time 80393167 ps
CPU time 3.09 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 198048 kb
Host smart-11254d33-75c8-4f7d-a8a2-daf91a9d8f09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112810601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4112810601
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4594594
Short name T653
Test name
Test status
Simulation time 420307736 ps
CPU time 3.21 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 197140 kb
Host smart-e989d6f0-de99-429c-b629-84bf18cf1900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4594594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.4594594
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1823424060
Short name T551
Test name
Test status
Simulation time 15459971 ps
CPU time 0.71 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:16 PM PDT 24
Peak memory 195012 kb
Host smart-b7833c7e-9be2-465e-9b6e-9a8700d95a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823424060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1823424060
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.4077902480
Short name T343
Test name
Test status
Simulation time 65560855 ps
CPU time 0.73 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 195532 kb
Host smart-7e6e4699-6921-422a-9b79-845f2f17c7e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077902480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.4077902480
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3157599898
Short name T234
Test name
Test status
Simulation time 44158750 ps
CPU time 1.98 seconds
Started Apr 02 12:51:13 PM PDT 24
Finished Apr 02 12:51:15 PM PDT 24
Peak memory 197944 kb
Host smart-b31dfd58-7b30-4130-a023-db684f7b4b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157599898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3157599898
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.606131886
Short name T123
Test name
Test status
Simulation time 504134195 ps
CPU time 1.27 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:51:14 PM PDT 24
Peak memory 195740 kb
Host smart-03d5acf2-6e6f-469f-bf5e-6b471b0d289d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606131886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.606131886
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.141725867
Short name T304
Test name
Test status
Simulation time 66229635 ps
CPU time 1.3 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 196504 kb
Host smart-b4a670f3-f0e0-4856-9122-e4feea2e42f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141725867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.141725867
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1786451685
Short name T318
Test name
Test status
Simulation time 4292524668 ps
CPU time 30.57 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 198160 kb
Host smart-62186ee2-b10c-4354-b504-5f45068d7791
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786451685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1786451685
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3581018860
Short name T692
Test name
Test status
Simulation time 32092886 ps
CPU time 0.56 seconds
Started Apr 02 12:49:56 PM PDT 24
Finished Apr 02 12:49:57 PM PDT 24
Peak memory 193904 kb
Host smart-67be21ae-3ac7-4796-a6f6-1ce9ba6d0166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581018860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3581018860
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2614751121
Short name T139
Test name
Test status
Simulation time 57504853 ps
CPU time 0.75 seconds
Started Apr 02 12:49:58 PM PDT 24
Finished Apr 02 12:49:59 PM PDT 24
Peak memory 194840 kb
Host smart-da0a506a-df3a-4624-a46f-1c76edb711d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614751121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2614751121
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1962981892
Short name T130
Test name
Test status
Simulation time 163263926 ps
CPU time 8.07 seconds
Started Apr 02 12:49:58 PM PDT 24
Finished Apr 02 12:50:06 PM PDT 24
Peak memory 195484 kb
Host smart-6cc9f278-5650-4d2c-b278-6b4343323144
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962981892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1962981892
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2826258712
Short name T441
Test name
Test status
Simulation time 635659619 ps
CPU time 1.04 seconds
Started Apr 02 12:49:55 PM PDT 24
Finished Apr 02 12:49:56 PM PDT 24
Peak memory 196596 kb
Host smart-48c49891-f3e6-4d03-80b5-dee6f96778d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826258712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2826258712
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3878068571
Short name T325
Test name
Test status
Simulation time 111499625 ps
CPU time 0.76 seconds
Started Apr 02 12:49:56 PM PDT 24
Finished Apr 02 12:49:57 PM PDT 24
Peak memory 196124 kb
Host smart-a901aebf-7915-4e5e-b4f8-5a5a5cf37b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878068571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3878068571
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.477917183
Short name T636
Test name
Test status
Simulation time 324036478 ps
CPU time 3.53 seconds
Started Apr 02 12:49:55 PM PDT 24
Finished Apr 02 12:49:59 PM PDT 24
Peak memory 198092 kb
Host smart-4a57cc3b-7ad9-49a6-b694-30aa8eb0c71f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477917183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.477917183
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2985787802
Short name T543
Test name
Test status
Simulation time 331964786 ps
CPU time 3.23 seconds
Started Apr 02 12:49:57 PM PDT 24
Finished Apr 02 12:50:01 PM PDT 24
Peak memory 197008 kb
Host smart-500f490b-2292-4682-bbcd-648b6d2d82e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985787802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2985787802
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2890824286
Short name T168
Test name
Test status
Simulation time 26696940 ps
CPU time 1.08 seconds
Started Apr 02 12:49:55 PM PDT 24
Finished Apr 02 12:49:56 PM PDT 24
Peak memory 196548 kb
Host smart-2649caaa-9042-4e18-bd05-8e43859b5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890824286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2890824286
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2848597412
Short name T104
Test name
Test status
Simulation time 45872632 ps
CPU time 1.04 seconds
Started Apr 02 12:49:55 PM PDT 24
Finished Apr 02 12:49:56 PM PDT 24
Peak memory 196652 kb
Host smart-868c13f2-c213-4fa4-a37b-d5b4a5157683
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848597412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2848597412
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2200403834
Short name T429
Test name
Test status
Simulation time 362728343 ps
CPU time 4.35 seconds
Started Apr 02 12:49:55 PM PDT 24
Finished Apr 02 12:50:00 PM PDT 24
Peak memory 197996 kb
Host smart-eba9e93d-8e2c-4cc2-94fa-daaf971bf4bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200403834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2200403834
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2160037494
Short name T42
Test name
Test status
Simulation time 35951406 ps
CPU time 0.79 seconds
Started Apr 02 12:49:56 PM PDT 24
Finished Apr 02 12:49:57 PM PDT 24
Peak memory 213760 kb
Host smart-43930f28-c7cc-4d36-a565-00c665dd02aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160037494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2160037494
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1702450743
Short name T277
Test name
Test status
Simulation time 270978465 ps
CPU time 1.24 seconds
Started Apr 02 12:49:52 PM PDT 24
Finished Apr 02 12:49:53 PM PDT 24
Peak memory 196976 kb
Host smart-69c0e7b4-7599-4010-93eb-5267a9a502d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702450743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1702450743
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3784385066
Short name T666
Test name
Test status
Simulation time 803481890 ps
CPU time 1.5 seconds
Started Apr 02 12:49:57 PM PDT 24
Finished Apr 02 12:49:59 PM PDT 24
Peak memory 196688 kb
Host smart-4a001d78-336c-46bf-9c02-9951520418fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784385066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3784385066
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1299265699
Short name T177
Test name
Test status
Simulation time 6373225055 ps
CPU time 88.57 seconds
Started Apr 02 12:49:53 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 198092 kb
Host smart-710b3cfa-a15b-4f78-b9f0-13a37366361c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299265699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1299265699
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1291564344
Short name T96
Test name
Test status
Simulation time 19652319 ps
CPU time 0.59 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 194144 kb
Host smart-c99e5966-7548-4ef4-8fd0-fb570f700501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291564344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1291564344
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2532008478
Short name T534
Test name
Test status
Simulation time 30766685 ps
CPU time 0.93 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:16 PM PDT 24
Peak memory 196400 kb
Host smart-3493cb63-2e0a-4e06-9044-d0efad928c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532008478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2532008478
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1709209378
Short name T19
Test name
Test status
Simulation time 6449846227 ps
CPU time 26.54 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196788 kb
Host smart-bb8f0453-7afb-4836-b698-6e2db896903e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709209378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1709209378
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2074140302
Short name T248
Test name
Test status
Simulation time 146863371 ps
CPU time 0.75 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 196492 kb
Host smart-31c86d10-11c9-425a-9846-0a1cff3614a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074140302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2074140302
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2430847833
Short name T391
Test name
Test status
Simulation time 155267148 ps
CPU time 0.92 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 196780 kb
Host smart-328872b5-960e-4987-a22a-3e6117266f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430847833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2430847833
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2947016240
Short name T361
Test name
Test status
Simulation time 374543290 ps
CPU time 2.1 seconds
Started Apr 02 12:51:21 PM PDT 24
Finished Apr 02 12:51:23 PM PDT 24
Peak memory 198008 kb
Host smart-7e1d84f4-bf23-41f6-8569-ecc02dd05fec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947016240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2947016240
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1859752781
Short name T170
Test name
Test status
Simulation time 217561034 ps
CPU time 1.82 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 195764 kb
Host smart-750b7d66-c106-4b0f-9b60-19be9969087e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859752781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1859752781
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3747863182
Short name T302
Test name
Test status
Simulation time 171059625 ps
CPU time 0.79 seconds
Started Apr 02 12:51:12 PM PDT 24
Finished Apr 02 12:51:13 PM PDT 24
Peak memory 195452 kb
Host smart-918deb3e-22cd-4d7a-b25f-fb1f81a6ff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747863182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3747863182
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2908461400
Short name T327
Test name
Test status
Simulation time 282457580 ps
CPU time 1.03 seconds
Started Apr 02 12:51:10 PM PDT 24
Finished Apr 02 12:51:12 PM PDT 24
Peak memory 195848 kb
Host smart-5f10a9ec-a8a4-477d-9972-7c4913feda83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908461400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2908461400
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2453945226
Short name T266
Test name
Test status
Simulation time 58929594 ps
CPU time 1.26 seconds
Started Apr 02 12:51:19 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 197808 kb
Host smart-2f6aa424-8000-4edb-9f67-3ac99aac6b2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453945226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2453945226
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.611525592
Short name T240
Test name
Test status
Simulation time 56416639 ps
CPU time 0.88 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:16 PM PDT 24
Peak memory 195704 kb
Host smart-21b6f3b0-caba-4ae2-ace8-384f80d1b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611525592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.611525592
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2632421535
Short name T179
Test name
Test status
Simulation time 346639311 ps
CPU time 1.39 seconds
Started Apr 02 12:51:14 PM PDT 24
Finished Apr 02 12:51:15 PM PDT 24
Peak memory 196676 kb
Host smart-0c5fc697-63af-462e-8625-d12ca419f58c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632421535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2632421535
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2378765888
Short name T595
Test name
Test status
Simulation time 5472782897 ps
CPU time 18.71 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 198148 kb
Host smart-6c67f8bb-eef0-4e6a-82c6-b0e53ae48f02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378765888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2378765888
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2146487049
Short name T36
Test name
Test status
Simulation time 522253481999 ps
CPU time 872.47 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 01:05:50 PM PDT 24
Peak memory 198220 kb
Host smart-d0f868a2-e7ae-44a4-9ecf-09d8359d481d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2146487049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2146487049
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1488711480
Short name T443
Test name
Test status
Simulation time 15144127 ps
CPU time 0.57 seconds
Started Apr 02 12:51:22 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 193928 kb
Host smart-dda9b71b-be9e-4f3c-8c3f-49be9c6c744b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488711480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1488711480
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2309691598
Short name T536
Test name
Test status
Simulation time 42374355 ps
CPU time 0.81 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 195288 kb
Host smart-e203e57a-4f77-41a0-8d2d-2c3f1d2c0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309691598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2309691598
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1188196910
Short name T276
Test name
Test status
Simulation time 681029938 ps
CPU time 22.05 seconds
Started Apr 02 12:51:24 PM PDT 24
Finished Apr 02 12:51:46 PM PDT 24
Peak memory 196784 kb
Host smart-c510be01-09d2-4be5-98ab-0921bc23c82c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188196910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1188196910
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2218599819
Short name T29
Test name
Test status
Simulation time 93873758 ps
CPU time 0.76 seconds
Started Apr 02 12:51:18 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 196580 kb
Host smart-6201d9eb-2709-4972-931b-1a20a175e845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218599819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2218599819
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3283664013
Short name T484
Test name
Test status
Simulation time 92394342 ps
CPU time 0.99 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 195884 kb
Host smart-53f4ccc7-e8dc-4da5-8fc9-98ed75311d82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283664013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3283664013
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1015154414
Short name T546
Test name
Test status
Simulation time 49027264 ps
CPU time 1.89 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 198056 kb
Host smart-818358ca-d5bc-4a21-aeba-0688fa4e5aba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015154414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1015154414
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3088736753
Short name T554
Test name
Test status
Simulation time 77324725 ps
CPU time 1.51 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:19 PM PDT 24
Peak memory 196724 kb
Host smart-dea58ca6-0cc7-4d6a-95d6-6ff1fb0c34b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088736753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3088736753
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1302683267
Short name T392
Test name
Test status
Simulation time 25226625 ps
CPU time 0.96 seconds
Started Apr 02 12:51:19 PM PDT 24
Finished Apr 02 12:51:20 PM PDT 24
Peak memory 196740 kb
Host smart-7b0652a8-e30c-4ead-8fe2-d18be7d374d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302683267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1302683267
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1039871014
Short name T702
Test name
Test status
Simulation time 119319804 ps
CPU time 1.4 seconds
Started Apr 02 12:51:15 PM PDT 24
Finished Apr 02 12:51:17 PM PDT 24
Peak memory 196996 kb
Host smart-8762b1ba-1092-48d0-98fe-324c9b7eecb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039871014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1039871014
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.4117303552
Short name T679
Test name
Test status
Simulation time 1900851503 ps
CPU time 6.85 seconds
Started Apr 02 12:51:21 PM PDT 24
Finished Apr 02 12:51:28 PM PDT 24
Peak memory 197968 kb
Host smart-859034d7-56a9-4669-9522-e38a58e703d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117303552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.4117303552
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3567584902
Short name T690
Test name
Test status
Simulation time 37792804 ps
CPU time 1.08 seconds
Started Apr 02 12:51:17 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 195516 kb
Host smart-324fbb2f-592d-4df7-a574-46c06839e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567584902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3567584902
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2474644257
Short name T53
Test name
Test status
Simulation time 145022736 ps
CPU time 0.89 seconds
Started Apr 02 12:51:16 PM PDT 24
Finished Apr 02 12:51:18 PM PDT 24
Peak memory 195196 kb
Host smart-706b0672-ed93-4a81-9175-0672f79da3a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474644257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2474644257
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2060946934
Short name T474
Test name
Test status
Simulation time 14261158090 ps
CPU time 52.25 seconds
Started Apr 02 12:51:23 PM PDT 24
Finished Apr 02 12:52:16 PM PDT 24
Peak memory 198164 kb
Host smart-7e482704-af63-4bf2-a09d-56aa223109e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060946934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2060946934
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1191364695
Short name T440
Test name
Test status
Simulation time 30549448 ps
CPU time 0.55 seconds
Started Apr 02 12:51:24 PM PDT 24
Finished Apr 02 12:51:25 PM PDT 24
Peak memory 193900 kb
Host smart-14e11922-c7c1-4a00-a777-7a31945d61d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191364695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1191364695
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3995494567
Short name T671
Test name
Test status
Simulation time 30586909 ps
CPU time 0.66 seconds
Started Apr 02 12:51:21 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 194164 kb
Host smart-1fce0d79-b05c-4cff-a283-e957201dc401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995494567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3995494567
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1402203707
Short name T141
Test name
Test status
Simulation time 357374857 ps
CPU time 17.91 seconds
Started Apr 02 12:51:21 PM PDT 24
Finished Apr 02 12:51:39 PM PDT 24
Peak memory 196724 kb
Host smart-cacac0bf-a9ea-4ea3-8fc9-682969869bfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402203707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1402203707
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2292733847
Short name T280
Test name
Test status
Simulation time 475428543 ps
CPU time 0.77 seconds
Started Apr 02 12:51:20 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 196000 kb
Host smart-59bff62c-a5ef-41d6-b0ce-b09b596cbe36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292733847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2292733847
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1131493912
Short name T192
Test name
Test status
Simulation time 38843540 ps
CPU time 0.66 seconds
Started Apr 02 12:51:22 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 195052 kb
Host smart-daef6975-b1c7-4c62-b0d8-8e9b0fd8a566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131493912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1131493912
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1592279917
Short name T388
Test name
Test status
Simulation time 94569725 ps
CPU time 4.05 seconds
Started Apr 02 12:51:23 PM PDT 24
Finished Apr 02 12:51:27 PM PDT 24
Peak memory 198000 kb
Host smart-a6928982-9526-4a9a-9520-45a3a66cd0a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592279917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1592279917
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2418918922
Short name T707
Test name
Test status
Simulation time 47106400 ps
CPU time 1.3 seconds
Started Apr 02 12:51:19 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 196604 kb
Host smart-6dd5121e-f2de-4c82-a43c-f2a81917e475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418918922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2418918922
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3690990986
Short name T535
Test name
Test status
Simulation time 51732402 ps
CPU time 1.09 seconds
Started Apr 02 12:51:19 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 196084 kb
Host smart-86107a29-2b49-4fba-84a5-ac07c27af26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690990986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3690990986
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.127172189
Short name T579
Test name
Test status
Simulation time 75409108 ps
CPU time 0.81 seconds
Started Apr 02 12:51:19 PM PDT 24
Finished Apr 02 12:51:20 PM PDT 24
Peak memory 196124 kb
Host smart-b4c6a1d7-0ad0-4335-a76d-e131e89c4cc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127172189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.127172189
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2722031238
Short name T213
Test name
Test status
Simulation time 399349454 ps
CPU time 4.55 seconds
Started Apr 02 12:51:21 PM PDT 24
Finished Apr 02 12:51:26 PM PDT 24
Peak memory 197948 kb
Host smart-f8958b97-1644-468c-b88d-71277256f881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722031238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2722031238
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2177315843
Short name T553
Test name
Test status
Simulation time 46714365 ps
CPU time 0.98 seconds
Started Apr 02 12:51:20 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 196468 kb
Host smart-dd3ac3ce-fff7-4f4d-9314-c4b775be9b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177315843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2177315843
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1373152032
Short name T529
Test name
Test status
Simulation time 40260738 ps
CPU time 1.26 seconds
Started Apr 02 12:51:20 PM PDT 24
Finished Apr 02 12:51:21 PM PDT 24
Peak memory 196764 kb
Host smart-e3b379ee-3e04-4d24-ac17-51c64d63744d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373152032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1373152032
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3130838560
Short name T216
Test name
Test status
Simulation time 34136877270 ps
CPU time 127.56 seconds
Started Apr 02 12:51:26 PM PDT 24
Finished Apr 02 12:53:34 PM PDT 24
Peak memory 198256 kb
Host smart-75df0eb1-caaa-4ad4-831c-6065062aed27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130838560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3130838560
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3959591346
Short name T453
Test name
Test status
Simulation time 19328727 ps
CPU time 0.57 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:31 PM PDT 24
Peak memory 193908 kb
Host smart-4563c4fa-80e6-4444-a2a5-da9b60f4d257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959591346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3959591346
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3672575287
Short name T497
Test name
Test status
Simulation time 109394425 ps
CPU time 0.76 seconds
Started Apr 02 12:51:22 PM PDT 24
Finished Apr 02 12:51:22 PM PDT 24
Peak memory 195192 kb
Host smart-8c4af023-f3dd-4068-9f74-95d8fcf2a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672575287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3672575287
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2976875117
Short name T544
Test name
Test status
Simulation time 663729800 ps
CPU time 21.91 seconds
Started Apr 02 12:51:25 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 197940 kb
Host smart-92f2ef40-0c89-497b-9690-a89f5ab76e24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976875117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2976875117
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3418483804
Short name T348
Test name
Test status
Simulation time 90259760 ps
CPU time 0.68 seconds
Started Apr 02 12:51:28 PM PDT 24
Finished Apr 02 12:51:28 PM PDT 24
Peak memory 195428 kb
Host smart-4f2bccea-b302-4cb9-8847-739b9b059711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418483804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3418483804
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3372122869
Short name T685
Test name
Test status
Simulation time 133985173 ps
CPU time 1.09 seconds
Started Apr 02 12:51:22 PM PDT 24
Finished Apr 02 12:51:23 PM PDT 24
Peak memory 195708 kb
Host smart-de501486-14b0-4e9e-92c4-e0ca7e5aa045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372122869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3372122869
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.784588754
Short name T538
Test name
Test status
Simulation time 62044522 ps
CPU time 0.92 seconds
Started Apr 02 12:51:28 PM PDT 24
Finished Apr 02 12:51:29 PM PDT 24
Peak memory 196204 kb
Host smart-372791eb-5f87-45d5-b12a-8b3bf599533a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784588754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.784588754
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.558580585
Short name T394
Test name
Test status
Simulation time 188705061 ps
CPU time 3.1 seconds
Started Apr 02 12:51:24 PM PDT 24
Finished Apr 02 12:51:27 PM PDT 24
Peak memory 197504 kb
Host smart-ad25d1b5-59e0-4478-9225-4d5ad10ab043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558580585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
558580585
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.396746429
Short name T675
Test name
Test status
Simulation time 20228947 ps
CPU time 0.67 seconds
Started Apr 02 12:51:23 PM PDT 24
Finished Apr 02 12:51:24 PM PDT 24
Peak memory 194508 kb
Host smart-9d6094c9-3c62-499b-b65e-6ba934a4cb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396746429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.396746429
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3626036058
Short name T525
Test name
Test status
Simulation time 84707270 ps
CPU time 0.77 seconds
Started Apr 02 12:51:27 PM PDT 24
Finished Apr 02 12:51:28 PM PDT 24
Peak memory 195520 kb
Host smart-ba2e4098-045f-4064-94f9-25c54c808c93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626036058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3626036058
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3664885199
Short name T681
Test name
Test status
Simulation time 71062713 ps
CPU time 3.34 seconds
Started Apr 02 12:51:25 PM PDT 24
Finished Apr 02 12:51:28 PM PDT 24
Peak memory 197968 kb
Host smart-7a2113d6-013d-4b1c-bb20-48ce0a025967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664885199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3664885199
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3601048233
Short name T63
Test name
Test status
Simulation time 73160486 ps
CPU time 1.44 seconds
Started Apr 02 12:51:24 PM PDT 24
Finished Apr 02 12:51:25 PM PDT 24
Peak memory 196268 kb
Host smart-87acc155-633f-45c3-aded-5c81fa386c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601048233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3601048233
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.727832736
Short name T472
Test name
Test status
Simulation time 330182924 ps
CPU time 1.58 seconds
Started Apr 02 12:51:23 PM PDT 24
Finished Apr 02 12:51:24 PM PDT 24
Peak memory 198060 kb
Host smart-ede2a23a-0537-4527-be5f-d015dfa2b8f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727832736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.727832736
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1334074406
Short name T513
Test name
Test status
Simulation time 13795586374 ps
CPU time 160.58 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:54:11 PM PDT 24
Peak memory 198172 kb
Host smart-7044c838-f120-4b8d-85d5-f28c0e592507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334074406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1334074406
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1953525576
Short name T465
Test name
Test status
Simulation time 23825059 ps
CPU time 0.6 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:31 PM PDT 24
Peak memory 193816 kb
Host smart-ce6febe2-f815-47fc-8cf4-cd2b0e2d3960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953525576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1953525576
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2911327652
Short name T689
Test name
Test status
Simulation time 17106432 ps
CPU time 0.74 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 194156 kb
Host smart-56611c1f-ae2e-4c80-9c06-89160009f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911327652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2911327652
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2074271613
Short name T680
Test name
Test status
Simulation time 2514763187 ps
CPU time 21.4 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 196888 kb
Host smart-0755db56-5498-4cd9-822f-aaf204f15304
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074271613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2074271613
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2777944231
Short name T597
Test name
Test status
Simulation time 61754941 ps
CPU time 0.93 seconds
Started Apr 02 12:51:28 PM PDT 24
Finished Apr 02 12:51:29 PM PDT 24
Peak memory 196760 kb
Host smart-e8baaaa6-adcf-475a-993f-8ee10c3c798d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777944231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2777944231
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.740637359
Short name T173
Test name
Test status
Simulation time 29286166 ps
CPU time 1.03 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 196840 kb
Host smart-eb9da0e0-d8f1-442e-9ce6-52e7724ea206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740637359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.740637359
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.541781212
Short name T418
Test name
Test status
Simulation time 326998529 ps
CPU time 3.28 seconds
Started Apr 02 12:51:29 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 198064 kb
Host smart-8a38d255-70bd-4ad5-b86b-92a654bf3dad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541781212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.541781212
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1964928598
Short name T516
Test name
Test status
Simulation time 95085566 ps
CPU time 1.01 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 195720 kb
Host smart-dbb590b1-320b-4011-a916-5834cb6e7daf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964928598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1964928598
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1727311909
Short name T55
Test name
Test status
Simulation time 57751588 ps
CPU time 1.15 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:35 PM PDT 24
Peak memory 196028 kb
Host smart-dbbd5969-0892-42c9-acce-5c81af79281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727311909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1727311909
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.117320463
Short name T459
Test name
Test status
Simulation time 85181514 ps
CPU time 1.03 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 196752 kb
Host smart-85e5418d-094d-4527-8088-cd5e8c7402c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117320463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.117320463
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.417876204
Short name T110
Test name
Test status
Simulation time 1009467957 ps
CPU time 4.42 seconds
Started Apr 02 12:51:29 PM PDT 24
Finished Apr 02 12:51:34 PM PDT 24
Peak memory 197988 kb
Host smart-4a4e76f3-5ad1-4a26-8ddb-f5e10a3420ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417876204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.417876204
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2507726060
Short name T295
Test name
Test status
Simulation time 318767982 ps
CPU time 1.43 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 197124 kb
Host smart-186407cf-8631-4ba2-ba6d-3aa899c57e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507726060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2507726060
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1826873118
Short name T229
Test name
Test status
Simulation time 152075346 ps
CPU time 1.4 seconds
Started Apr 02 12:51:28 PM PDT 24
Finished Apr 02 12:51:30 PM PDT 24
Peak memory 196244 kb
Host smart-ae55571a-7a1b-4138-a27b-4a9ff7654fe8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826873118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1826873118
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.738683599
Short name T109
Test name
Test status
Simulation time 20202778219 ps
CPU time 155.13 seconds
Started Apr 02 12:51:29 PM PDT 24
Finished Apr 02 12:54:04 PM PDT 24
Peak memory 198140 kb
Host smart-0493e5bd-6eb0-4848-a06e-93d6950916bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738683599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.738683599
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1931923222
Short name T46
Test name
Test status
Simulation time 15345132 ps
CPU time 0.57 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:51:34 PM PDT 24
Peak memory 194644 kb
Host smart-1b942c91-23e4-4fb2-84ed-488555839fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931923222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1931923222
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4219858296
Short name T308
Test name
Test status
Simulation time 82805846 ps
CPU time 0.85 seconds
Started Apr 02 12:51:39 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 195340 kb
Host smart-d79d5e5e-6cf9-48e3-9ce8-5e77bfa0bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219858296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4219858296
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2742691337
Short name T569
Test name
Test status
Simulation time 6338249402 ps
CPU time 29.66 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 197064 kb
Host smart-482f492a-1191-4e3f-b61b-525dc6ae68cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742691337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2742691337
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1787866885
Short name T564
Test name
Test status
Simulation time 84273832 ps
CPU time 1 seconds
Started Apr 02 12:51:32 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 196660 kb
Host smart-e8e7d130-5058-4a4a-8798-4b47a8e631de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787866885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1787866885
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1461905835
Short name T249
Test name
Test status
Simulation time 51638170 ps
CPU time 1.51 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:56 PM PDT 24
Peak memory 198060 kb
Host smart-830328c5-cd9b-424e-a299-ec4e51588407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461905835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1461905835
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.188519200
Short name T156
Test name
Test status
Simulation time 384754053 ps
CPU time 2.69 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 197960 kb
Host smart-0fdf3b8e-b00e-47fe-aafe-8dfbd3431f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188519200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
188519200
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.329069197
Short name T463
Test name
Test status
Simulation time 29494795 ps
CPU time 0.75 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 195480 kb
Host smart-c45620d7-fc7d-4522-81b8-2ae7ff86ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329069197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.329069197
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.38852471
Short name T555
Test name
Test status
Simulation time 109160210 ps
CPU time 0.9 seconds
Started Apr 02 12:51:32 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 196652 kb
Host smart-4ad2fb38-bcc2-4246-97a2-4cd382dc9fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38852471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup_
pulldown.38852471
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.883326475
Short name T334
Test name
Test status
Simulation time 267572663 ps
CPU time 4.46 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 197992 kb
Host smart-527969db-5fa0-4c92-931e-b39e9265e72d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883326475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.883326475
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2600548656
Short name T209
Test name
Test status
Simulation time 120249148 ps
CPU time 1.06 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 195764 kb
Host smart-d43fdc58-250d-4ae0-a63d-b906dc27315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600548656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2600548656
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2385919404
Short name T376
Test name
Test status
Simulation time 321631466 ps
CPU time 1.41 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:32 PM PDT 24
Peak memory 196652 kb
Host smart-27e43e99-8f08-4970-a1d3-9f2199d1dc2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385919404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2385919404
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1353047378
Short name T461
Test name
Test status
Simulation time 22479786161 ps
CPU time 128.14 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:53:40 PM PDT 24
Peak memory 198144 kb
Host smart-e913a4eb-e07b-4ac6-bcc0-e2ca742f3e7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353047378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1353047378
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.418743533
Short name T250
Test name
Test status
Simulation time 15073346 ps
CPU time 0.59 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 193940 kb
Host smart-dc7aa417-23e4-4af2-94f9-1542330bd05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418743533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.418743533
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2612234931
Short name T508
Test name
Test status
Simulation time 32969218 ps
CPU time 0.84 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:31 PM PDT 24
Peak memory 195348 kb
Host smart-8d80e77b-58fa-48d9-b157-43939fcf1b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612234931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2612234931
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2718335858
Short name T696
Test name
Test status
Simulation time 349927529 ps
CPU time 11.58 seconds
Started Apr 02 12:51:32 PM PDT 24
Finished Apr 02 12:51:44 PM PDT 24
Peak memory 196888 kb
Host smart-1d6ddeb2-74df-4860-817c-75db5dddeca5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718335858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2718335858
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2372572118
Short name T447
Test name
Test status
Simulation time 187731802 ps
CPU time 0.82 seconds
Started Apr 02 12:51:30 PM PDT 24
Finished Apr 02 12:51:31 PM PDT 24
Peak memory 195852 kb
Host smart-1ea60d78-248d-4071-a4c5-1f87d2afd448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372572118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2372572118
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2623978192
Short name T406
Test name
Test status
Simulation time 51814999 ps
CPU time 1.46 seconds
Started Apr 02 12:51:39 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 197948 kb
Host smart-25a06ff1-1ebd-4ba2-aea9-89d2ae54b798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623978192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2623978192
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2760052179
Short name T287
Test name
Test status
Simulation time 102363520 ps
CPU time 2.43 seconds
Started Apr 02 12:51:31 PM PDT 24
Finished Apr 02 12:51:34 PM PDT 24
Peak memory 196432 kb
Host smart-31524d40-8b0b-4f60-93d7-8fd2c8c727da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760052179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2760052179
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2106553843
Short name T509
Test name
Test status
Simulation time 827606851 ps
CPU time 3.27 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 196832 kb
Host smart-b367f11c-6f59-44c0-b820-595c5288066e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106553843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2106553843
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.92802991
Short name T602
Test name
Test status
Simulation time 44912398 ps
CPU time 0.75 seconds
Started Apr 02 12:51:32 PM PDT 24
Finished Apr 02 12:51:33 PM PDT 24
Peak memory 195368 kb
Host smart-73930bc5-4582-4b60-90ad-ab53e1805b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92802991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.92802991
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4101777168
Short name T637
Test name
Test status
Simulation time 109715634 ps
CPU time 0.99 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 196436 kb
Host smart-dc9eee65-850e-4cd6-8ca5-164e51d8db02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101777168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4101777168
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3331114202
Short name T6
Test name
Test status
Simulation time 1430855202 ps
CPU time 5.06 seconds
Started Apr 02 12:51:32 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 197656 kb
Host smart-77334923-2da3-4cd0-8737-871ce04a6013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331114202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3331114202
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2912728422
Short name T687
Test name
Test status
Simulation time 72399188 ps
CPU time 1.15 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:51:35 PM PDT 24
Peak memory 195700 kb
Host smart-f1074ce4-ffe9-42b8-b939-eab9086286cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912728422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2912728422
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1535729241
Short name T432
Test name
Test status
Simulation time 120830015 ps
CPU time 0.88 seconds
Started Apr 02 12:51:35 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 195232 kb
Host smart-0f762f2b-e1c5-4e0d-a5be-dff6cf4c2d82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535729241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1535729241
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1329879255
Short name T642
Test name
Test status
Simulation time 10486463188 ps
CPU time 115.91 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:53:29 PM PDT 24
Peak memory 198100 kb
Host smart-284adb6e-43b3-49d3-aaba-b86a73b51964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329879255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1329879255
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1986494730
Short name T695
Test name
Test status
Simulation time 236862942177 ps
CPU time 882.9 seconds
Started Apr 02 12:51:38 PM PDT 24
Finished Apr 02 01:06:21 PM PDT 24
Peak memory 198272 kb
Host smart-89a087be-6ff3-43ba-a923-d7e2eedf424d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1986494730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1986494730
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2573705565
Short name T478
Test name
Test status
Simulation time 40763862 ps
CPU time 0.59 seconds
Started Apr 02 12:51:40 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 193956 kb
Host smart-c33ed179-1118-4600-b3c6-803b2e3a7498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573705565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2573705565
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.754850795
Short name T207
Test name
Test status
Simulation time 56872253 ps
CPU time 0.71 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 194816 kb
Host smart-e38edebf-246d-44ac-8527-5318c7f75366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754850795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.754850795
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1756754738
Short name T451
Test name
Test status
Simulation time 384062041 ps
CPU time 5.61 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:42 PM PDT 24
Peak memory 196788 kb
Host smart-71f9e64a-e27c-4b5a-b2d8-7eb77e4575ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756754738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1756754738
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2295780570
Short name T252
Test name
Test status
Simulation time 214364768 ps
CPU time 1.09 seconds
Started Apr 02 12:51:40 PM PDT 24
Finished Apr 02 12:51:41 PM PDT 24
Peak memory 196284 kb
Host smart-c314462b-eb7a-4385-860e-872396e5ee75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295780570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2295780570
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1078817302
Short name T436
Test name
Test status
Simulation time 129715270 ps
CPU time 1.09 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:38 PM PDT 24
Peak memory 195832 kb
Host smart-81e4d09a-14ab-4db0-9937-f7c39a5a1108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078817302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1078817302
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2971628095
Short name T158
Test name
Test status
Simulation time 294287781 ps
CPU time 3.07 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 198112 kb
Host smart-178440e5-1382-45d1-b4a7-6b7bfc274cff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971628095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2971628095
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1710777594
Short name T705
Test name
Test status
Simulation time 1564740518 ps
CPU time 2.02 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 196668 kb
Host smart-fd3532d3-ad0d-4b3c-9685-041c76e47eba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710777594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1710777594
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1422173935
Short name T526
Test name
Test status
Simulation time 19171709 ps
CPU time 0.67 seconds
Started Apr 02 12:51:35 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 194416 kb
Host smart-5b7974d7-71c2-4b1c-96f2-23a68dfb724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422173935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1422173935
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4146469436
Short name T512
Test name
Test status
Simulation time 43823837 ps
CPU time 0.89 seconds
Started Apr 02 12:51:33 PM PDT 24
Finished Apr 02 12:51:34 PM PDT 24
Peak memory 195936 kb
Host smart-f67d5793-239b-4a3b-a03d-2c114a46f568
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146469436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4146469436
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3605297013
Short name T591
Test name
Test status
Simulation time 171381738 ps
CPU time 2.18 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:36 PM PDT 24
Peak memory 197964 kb
Host smart-52603af8-842a-4a60-9376-431b5edd0219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605297013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3605297013
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.239434194
Short name T279
Test name
Test status
Simulation time 581266019 ps
CPU time 1.03 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 195724 kb
Host smart-fd07dd08-6b15-4cc8-8f3a-72138c53b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239434194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.239434194
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2116438153
Short name T200
Test name
Test status
Simulation time 263790558 ps
CPU time 0.98 seconds
Started Apr 02 12:51:34 PM PDT 24
Finished Apr 02 12:51:35 PM PDT 24
Peak memory 197264 kb
Host smart-cb6df13c-1fe6-47af-8708-1f1bcf276b0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116438153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2116438153
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1435753875
Short name T317
Test name
Test status
Simulation time 14431338922 ps
CPU time 103.58 seconds
Started Apr 02 12:51:41 PM PDT 24
Finished Apr 02 12:53:24 PM PDT 24
Peak memory 198112 kb
Host smart-f74daf83-7aba-4cb7-b964-a509d495eb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435753875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1435753875
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2104661534
Short name T333
Test name
Test status
Simulation time 93906685 ps
CPU time 0.58 seconds
Started Apr 02 12:51:39 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 193900 kb
Host smart-4089f9ff-1242-4c69-8d67-15964acc50af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104661534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2104661534
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2356788845
Short name T491
Test name
Test status
Simulation time 47242957 ps
CPU time 0.85 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 12:51:37 PM PDT 24
Peak memory 196544 kb
Host smart-62dee2f9-6a17-49e3-8045-3b2e094c516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356788845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2356788845
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3030560007
Short name T490
Test name
Test status
Simulation time 189566151 ps
CPU time 9.61 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:55 PM PDT 24
Peak memory 196712 kb
Host smart-6222d980-5975-4a11-b1b2-1de940ce3027
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030560007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3030560007
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1393489635
Short name T658
Test name
Test status
Simulation time 36412943 ps
CPU time 0.75 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:44 PM PDT 24
Peak memory 194736 kb
Host smart-1be5f2b5-0463-43c1-8aa6-83fe927f12ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393489635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1393489635
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3517516548
Short name T373
Test name
Test status
Simulation time 865303629 ps
CPU time 0.93 seconds
Started Apr 02 12:51:37 PM PDT 24
Finished Apr 02 12:51:38 PM PDT 24
Peak memory 196692 kb
Host smart-eec56551-569a-4690-824e-2efdb29a9c71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517516548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3517516548
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1025844123
Short name T184
Test name
Test status
Simulation time 307973624 ps
CPU time 3.47 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 198020 kb
Host smart-4064810d-b662-4169-a32a-99bcb5296871
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025844123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1025844123
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2724867169
Short name T661
Test name
Test status
Simulation time 759651891 ps
CPU time 1.59 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:45 PM PDT 24
Peak memory 196048 kb
Host smart-5799fc50-7849-4676-b4eb-29874bd248a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724867169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2724867169
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2844199742
Short name T355
Test name
Test status
Simulation time 28808578 ps
CPU time 0.76 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 195372 kb
Host smart-4b32db58-832f-4c0e-a609-6a2b21653798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844199742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2844199742
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1701717244
Short name T155
Test name
Test status
Simulation time 108619478 ps
CPU time 1.17 seconds
Started Apr 02 12:51:41 PM PDT 24
Finished Apr 02 12:51:42 PM PDT 24
Peak memory 197128 kb
Host smart-bad01cae-ce57-4e78-8898-a11b39106bc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701717244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1701717244
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1880247108
Short name T309
Test name
Test status
Simulation time 61612489 ps
CPU time 1.69 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 197940 kb
Host smart-69e4339d-e1dc-4f07-a26f-dc66e7f49480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880247108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1880247108
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1774759689
Short name T255
Test name
Test status
Simulation time 33326100 ps
CPU time 0.69 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 194212 kb
Host smart-2bbd2dab-f4d2-40b5-9f39-9d6daa9ef596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774759689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1774759689
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3189094814
Short name T410
Test name
Test status
Simulation time 41764677 ps
CPU time 1.01 seconds
Started Apr 02 12:51:39 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 195676 kb
Host smart-9653d3d3-286d-4106-bb7b-1d5fa1eaef47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189094814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3189094814
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1748848576
Short name T17
Test name
Test status
Simulation time 13157730492 ps
CPU time 46.72 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:52:30 PM PDT 24
Peak memory 198152 kb
Host smart-5ae30d6d-50a9-4bde-b7fc-00e11996df9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748848576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1748848576
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.984998174
Short name T241
Test name
Test status
Simulation time 16646470 ps
CPU time 0.57 seconds
Started Apr 02 12:51:44 PM PDT 24
Finished Apr 02 12:51:45 PM PDT 24
Peak memory 194928 kb
Host smart-9b3a4aeb-10cb-4775-aa79-b83385b95d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984998174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.984998174
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2469311420
Short name T515
Test name
Test status
Simulation time 40985903 ps
CPU time 0.88 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196244 kb
Host smart-54d691d7-a086-4364-9501-1e6dddd447fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469311420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2469311420
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.600516229
Short name T560
Test name
Test status
Simulation time 312475308 ps
CPU time 3.7 seconds
Started Apr 02 12:51:40 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 195900 kb
Host smart-1e8f1410-b008-4bf9-befa-a28be4fc181b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600516229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.600516229
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3961043115
Short name T700
Test name
Test status
Simulation time 62090964 ps
CPU time 0.99 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 196140 kb
Host smart-c7e90307-96bf-4373-b8b9-efcdadb6cd6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961043115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3961043115
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1654464538
Short name T409
Test name
Test status
Simulation time 99683201 ps
CPU time 0.68 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:46 PM PDT 24
Peak memory 195140 kb
Host smart-ab14cec9-580f-4acc-827e-c33820902a44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654464538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1654464538
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.824614055
Short name T433
Test name
Test status
Simulation time 44612169 ps
CPU time 1.9 seconds
Started Apr 02 12:51:38 PM PDT 24
Finished Apr 02 12:51:40 PM PDT 24
Peak memory 197872 kb
Host smart-92887f97-ae8f-48f3-b79f-16810464c20b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824614055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.824614055
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1689447055
Short name T186
Test name
Test status
Simulation time 291281207 ps
CPU time 1.22 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196780 kb
Host smart-3fcaa040-91c0-42bf-975c-4411f2779123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689447055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1689447055
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1191494766
Short name T631
Test name
Test status
Simulation time 47432212 ps
CPU time 1.43 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195844 kb
Host smart-30075877-caf2-4792-80e8-b2d9a84a8670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191494766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1191494766
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1007291223
Short name T111
Test name
Test status
Simulation time 135787141 ps
CPU time 1.05 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195852 kb
Host smart-2f3ee909-287e-4b42-b5dc-5c8ea75e06a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007291223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1007291223
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_smoke.113259358
Short name T303
Test name
Test status
Simulation time 559496320 ps
CPU time 1.38 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196720 kb
Host smart-cd681f0d-47c0-4f3c-825d-fd58ffa7341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113259358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.113259358
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1629738992
Short name T283
Test name
Test status
Simulation time 105974224 ps
CPU time 0.83 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:44 PM PDT 24
Peak memory 195404 kb
Host smart-5af3c890-86e2-4f4d-98eb-b6c793eb1fd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629738992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1629738992
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1328269796
Short name T5
Test name
Test status
Simulation time 42792875091 ps
CPU time 88.75 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:53:14 PM PDT 24
Peak memory 198156 kb
Host smart-0d25c1b6-c86b-49b3-bb93-92f206e4a248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328269796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1328269796
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.4269295901
Short name T56
Test name
Test status
Simulation time 22002760739 ps
CPU time 510.58 seconds
Started Apr 02 12:51:36 PM PDT 24
Finished Apr 02 01:00:07 PM PDT 24
Peak memory 198224 kb
Host smart-c966066d-3846-46c6-a0e5-f777758445c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4269295901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.4269295901
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2948544744
Short name T506
Test name
Test status
Simulation time 11093087 ps
CPU time 0.55 seconds
Started Apr 02 12:49:59 PM PDT 24
Finished Apr 02 12:49:59 PM PDT 24
Peak memory 193944 kb
Host smart-8d6d7e2e-e1d3-43a6-a6a7-f7ecb002a3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948544744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2948544744
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4016945354
Short name T115
Test name
Test status
Simulation time 49181688 ps
CPU time 0.61 seconds
Started Apr 02 12:50:01 PM PDT 24
Finished Apr 02 12:50:01 PM PDT 24
Peak memory 193996 kb
Host smart-0baad6d6-ada2-4b49-838e-61223a67ecdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016945354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4016945354
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1245470872
Short name T268
Test name
Test status
Simulation time 2328702196 ps
CPU time 23.83 seconds
Started Apr 02 12:50:01 PM PDT 24
Finished Apr 02 12:50:25 PM PDT 24
Peak memory 195600 kb
Host smart-24c755e1-e648-48e1-b790-03c9e82de60c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245470872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1245470872
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1591820797
Short name T243
Test name
Test status
Simulation time 56294206 ps
CPU time 0.87 seconds
Started Apr 02 12:50:08 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 195968 kb
Host smart-f772f541-221d-4ef1-b82b-1f24d149a53a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591820797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1591820797
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3442760275
Short name T13
Test name
Test status
Simulation time 55266655 ps
CPU time 1.41 seconds
Started Apr 02 12:50:00 PM PDT 24
Finished Apr 02 12:50:02 PM PDT 24
Peak memory 195800 kb
Host smart-ad1abaa0-fb79-4fd2-a38c-ba56b0188a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442760275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3442760275
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.653036850
Short name T565
Test name
Test status
Simulation time 58382759 ps
CPU time 2.65 seconds
Started Apr 02 12:50:01 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 198040 kb
Host smart-47211a2d-51de-4755-8ee7-621ead25ff47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653036850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.653036850
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2227775242
Short name T306
Test name
Test status
Simulation time 201267096 ps
CPU time 1.91 seconds
Started Apr 02 12:50:01 PM PDT 24
Finished Apr 02 12:50:03 PM PDT 24
Peak memory 196804 kb
Host smart-f6aa88cd-b358-4441-a902-686b88580d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227775242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2227775242
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2970479679
Short name T134
Test name
Test status
Simulation time 42659058 ps
CPU time 1.1 seconds
Started Apr 02 12:50:08 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 196060 kb
Host smart-7dc1f7f7-1cc6-468c-9852-ed598c5f4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970479679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2970479679
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1943674758
Short name T152
Test name
Test status
Simulation time 66898163 ps
CPU time 1.2 seconds
Started Apr 02 12:49:58 PM PDT 24
Finished Apr 02 12:49:59 PM PDT 24
Peak memory 197004 kb
Host smart-3a322255-5b66-41dd-b0c4-4b23a56b7269
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943674758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1943674758
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1040349002
Short name T365
Test name
Test status
Simulation time 394896779 ps
CPU time 2.63 seconds
Started Apr 02 12:50:05 PM PDT 24
Finished Apr 02 12:50:08 PM PDT 24
Peak memory 197996 kb
Host smart-1ab64609-f075-4270-b2e0-df907e96e5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040349002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1040349002
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.4211341852
Short name T648
Test name
Test status
Simulation time 53702358 ps
CPU time 1.13 seconds
Started Apr 02 12:49:59 PM PDT 24
Finished Apr 02 12:50:01 PM PDT 24
Peak memory 195812 kb
Host smart-bcce33a4-a598-4db3-8d12-fd4755b502fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211341852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4211341852
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.608977162
Short name T563
Test name
Test status
Simulation time 94911594 ps
CPU time 0.95 seconds
Started Apr 02 12:49:59 PM PDT 24
Finished Apr 02 12:50:00 PM PDT 24
Peak memory 197196 kb
Host smart-86fade49-09a7-424e-ac1c-f7347f0eb5a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608977162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.608977162
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3471741712
Short name T659
Test name
Test status
Simulation time 15509158198 ps
CPU time 188.27 seconds
Started Apr 02 12:49:59 PM PDT 24
Finished Apr 02 12:53:08 PM PDT 24
Peak memory 198232 kb
Host smart-73e83f95-c5fc-4e83-a434-2fe340fe81a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471741712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3471741712
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3052556915
Short name T59
Test name
Test status
Simulation time 31009308174 ps
CPU time 809.14 seconds
Started Apr 02 12:50:01 PM PDT 24
Finished Apr 02 01:03:30 PM PDT 24
Peak memory 198224 kb
Host smart-f363982d-ad03-4574-be0b-9b1347df4fab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3052556915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3052556915
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3757464013
Short name T341
Test name
Test status
Simulation time 18507683 ps
CPU time 0.57 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:42 PM PDT 24
Peak memory 194144 kb
Host smart-3def6c3e-926b-4360-96c3-357e8705c2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757464013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3757464013
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1914264171
Short name T98
Test name
Test status
Simulation time 128980514 ps
CPU time 0.86 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 196280 kb
Host smart-0d5e462b-b26c-4a2b-b82f-583947e21ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914264171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1914264171
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2760600676
Short name T103
Test name
Test status
Simulation time 699518181 ps
CPU time 18.57 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:52:01 PM PDT 24
Peak memory 196788 kb
Host smart-ad8b9610-6ece-47c4-b276-5248e9a26aa1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760600676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2760600676
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1964740022
Short name T219
Test name
Test status
Simulation time 71140236 ps
CPU time 0.94 seconds
Started Apr 02 12:51:40 PM PDT 24
Finished Apr 02 12:51:41 PM PDT 24
Peak memory 197020 kb
Host smart-54478dc5-b5e3-426a-a672-887e5464689c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964740022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1964740022
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.805059747
Short name T663
Test name
Test status
Simulation time 269101486 ps
CPU time 1.39 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 197216 kb
Host smart-ff12240a-8996-4044-a5fe-c0029cc1a16b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805059747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.805059747
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.271104326
Short name T670
Test name
Test status
Simulation time 141013299 ps
CPU time 3.01 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:45 PM PDT 24
Peak memory 198128 kb
Host smart-e81c0fbd-eb53-4255-9fdd-0e1cbb3a4f7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271104326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.271104326
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2286356581
Short name T691
Test name
Test status
Simulation time 636239991 ps
CPU time 3.2 seconds
Started Apr 02 12:51:44 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 198064 kb
Host smart-14fe0e02-978f-4748-aaff-9aee27c4876b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286356581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2286356581
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1998046641
Short name T585
Test name
Test status
Simulation time 140033358 ps
CPU time 1.22 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196812 kb
Host smart-a368cf09-1637-46b0-945a-0985e8bad954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998046641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1998046641
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3025826535
Short name T199
Test name
Test status
Simulation time 132249063 ps
CPU time 0.93 seconds
Started Apr 02 12:51:41 PM PDT 24
Finished Apr 02 12:51:42 PM PDT 24
Peak memory 196756 kb
Host smart-03dc4525-3f60-4edf-8c97-48ea6e6cc920
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025826535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3025826535
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.413427658
Short name T571
Test name
Test status
Simulation time 78849205 ps
CPU time 1.85 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:45 PM PDT 24
Peak memory 197956 kb
Host smart-8c9940e0-e418-4fe8-84a1-453d93e77101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413427658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.413427658
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.340836800
Short name T166
Test name
Test status
Simulation time 64794948 ps
CPU time 1.11 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 195452 kb
Host smart-b03cb367-2548-46f7-b3a6-c7041d921b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340836800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.340836800
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3525063788
Short name T113
Test name
Test status
Simulation time 120688400 ps
CPU time 1.07 seconds
Started Apr 02 12:51:44 PM PDT 24
Finished Apr 02 12:51:46 PM PDT 24
Peak memory 195512 kb
Host smart-bbaab53a-321c-4f10-82a7-895e961fc9a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525063788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3525063788
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.162029554
Short name T232
Test name
Test status
Simulation time 2048814503 ps
CPU time 31.77 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:52:14 PM PDT 24
Peak memory 198072 kb
Host smart-49923043-0dc9-48a9-be1b-37071a605189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162029554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.162029554
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.424391280
Short name T126
Test name
Test status
Simulation time 17450362 ps
CPU time 0.58 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 193816 kb
Host smart-7b2e2ec9-9902-4461-bdc0-01236d1d3620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424391280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.424391280
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4288394820
Short name T519
Test name
Test status
Simulation time 67585267 ps
CPU time 0.81 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 195224 kb
Host smart-ef6b20e8-a185-46ab-b1e4-1f7afcc565cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288394820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4288394820
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2951914816
Short name T260
Test name
Test status
Simulation time 473740391 ps
CPU time 14.06 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:56 PM PDT 24
Peak memory 196884 kb
Host smart-6f5737ac-913f-4f3b-b093-d389c8f2a019
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951914816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2951914816
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3516284701
Short name T144
Test name
Test status
Simulation time 84023724 ps
CPU time 0.67 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 194536 kb
Host smart-268b3401-555c-49bd-84f3-83f69fa9df50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516284701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3516284701
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.4007137169
Short name T16
Test name
Test status
Simulation time 159610366 ps
CPU time 0.96 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:43 PM PDT 24
Peak memory 196108 kb
Host smart-b5ef9d72-f6b9-4d3c-b43f-1546ea01a970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007137169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.4007137169
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3686932177
Short name T500
Test name
Test status
Simulation time 156316611 ps
CPU time 1.73 seconds
Started Apr 02 12:51:42 PM PDT 24
Finished Apr 02 12:51:44 PM PDT 24
Peak memory 198040 kb
Host smart-8c7a17d7-363d-42f6-a713-7682d632af11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686932177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3686932177
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1773587581
Short name T570
Test name
Test status
Simulation time 336770212 ps
CPU time 1.7 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:45 PM PDT 24
Peak memory 195972 kb
Host smart-77c87b42-4618-4492-a5c5-44d16dda793f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773587581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1773587581
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.505158096
Short name T641
Test name
Test status
Simulation time 76962915 ps
CPU time 0.98 seconds
Started Apr 02 12:51:57 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 196028 kb
Host smart-62bc3a2e-2a54-4143-8910-da56f8204907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505158096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.505158096
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.245674269
Short name T454
Test name
Test status
Simulation time 28880416 ps
CPU time 0.9 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 195536 kb
Host smart-ea1b0a60-a501-4f1c-a0f6-c98cbb3f0ece
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245674269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.245674269
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3684341959
Short name T403
Test name
Test status
Simulation time 982566163 ps
CPU time 5.67 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:51:51 PM PDT 24
Peak memory 197932 kb
Host smart-df7c0226-45c0-42d9-bf1a-47f4ec3400dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684341959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3684341959
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3176240154
Short name T610
Test name
Test status
Simulation time 1089804019 ps
CPU time 1.28 seconds
Started Apr 02 12:51:43 PM PDT 24
Finished Apr 02 12:51:44 PM PDT 24
Peak memory 196816 kb
Host smart-5777aa9a-2774-4055-8514-d0657dcf9756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176240154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3176240154
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2858325442
Short name T627
Test name
Test status
Simulation time 287102755 ps
CPU time 1.33 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 195844 kb
Host smart-9b3e1a3d-ec14-45d5-8516-16edb6d467e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858325442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2858325442
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2048335694
Short name T161
Test name
Test status
Simulation time 27767761842 ps
CPU time 202.03 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:55:10 PM PDT 24
Peak memory 198196 kb
Host smart-41f23173-d134-423b-8321-49c736b4aa72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048335694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2048335694
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2359667157
Short name T339
Test name
Test status
Simulation time 15052525 ps
CPU time 0.56 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 193944 kb
Host smart-62cd2d83-0318-4725-9c92-5832d99f912b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359667157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2359667157
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1118638553
Short name T698
Test name
Test status
Simulation time 97350008 ps
CPU time 0.88 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 196676 kb
Host smart-afcd756e-5cd2-432e-84fc-37dcee8593d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118638553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1118638553
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3225495687
Short name T646
Test name
Test status
Simulation time 1003600289 ps
CPU time 23.95 seconds
Started Apr 02 12:51:45 PM PDT 24
Finished Apr 02 12:52:10 PM PDT 24
Peak memory 196904 kb
Host smart-52350d3d-e4b3-4cf0-9724-995bb837d1e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225495687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3225495687
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1583345792
Short name T397
Test name
Test status
Simulation time 48950307 ps
CPU time 0.91 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:49 PM PDT 24
Peak memory 196184 kb
Host smart-7758fb54-b3dc-4e04-a52f-49caf1dc5379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583345792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1583345792
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2490487970
Short name T118
Test name
Test status
Simulation time 220226056 ps
CPU time 1.35 seconds
Started Apr 02 12:51:46 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 196932 kb
Host smart-e5e40549-a416-4ac1-9d1f-b6110903c80e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490487970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2490487970
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1145810799
Short name T125
Test name
Test status
Simulation time 346804589 ps
CPU time 3.71 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:51 PM PDT 24
Peak memory 198028 kb
Host smart-76f2611e-fb2a-48d2-8f24-baf7b0ac8980
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145810799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1145810799
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4166192026
Short name T517
Test name
Test status
Simulation time 95756058 ps
CPU time 2.43 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 197084 kb
Host smart-8df4fcb5-4cfa-4f42-b063-43bb9688bc96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166192026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4166192026
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1328350939
Short name T521
Test name
Test status
Simulation time 279235259 ps
CPU time 1.18 seconds
Started Apr 02 12:51:46 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 196980 kb
Host smart-d7a82757-27bb-4457-9d2c-ad9c1d67a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328350939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1328350939
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2284158216
Short name T412
Test name
Test status
Simulation time 23916922 ps
CPU time 0.74 seconds
Started Apr 02 12:51:49 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195492 kb
Host smart-f61d62f2-a943-4519-b167-8070d08411e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284158216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2284158216
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.244672309
Short name T630
Test name
Test status
Simulation time 782994959 ps
CPU time 2.02 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:49 PM PDT 24
Peak memory 197976 kb
Host smart-3b024488-b5de-4722-b7c3-6d68652b795c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244672309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.244672309
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3768526829
Short name T419
Test name
Test status
Simulation time 71276602 ps
CPU time 1.4 seconds
Started Apr 02 12:51:46 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 195800 kb
Host smart-2d036198-071c-4710-95d5-56aa6c0c96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768526829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3768526829
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.383713406
Short name T246
Test name
Test status
Simulation time 238618082 ps
CPU time 1.19 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195736 kb
Host smart-0c4735c0-3761-47bd-b9b6-0a2160aa2dc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383713406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.383713406
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2253478452
Short name T530
Test name
Test status
Simulation time 6788274948 ps
CPU time 171.73 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:54:39 PM PDT 24
Peak memory 198192 kb
Host smart-15bf75fa-4a5b-4802-9a4a-4f4ae8d1d342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253478452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2253478452
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1597441760
Short name T233
Test name
Test status
Simulation time 30617743 ps
CPU time 0.58 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:55 PM PDT 24
Peak memory 194748 kb
Host smart-989c7a27-129b-41db-abcb-114cf3fc5ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597441760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1597441760
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.650898637
Short name T672
Test name
Test status
Simulation time 31997013 ps
CPU time 0.67 seconds
Started Apr 02 12:51:48 PM PDT 24
Finished Apr 02 12:51:49 PM PDT 24
Peak memory 193956 kb
Host smart-4cc90d4d-ecea-42bb-98f0-8c231b653488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650898637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.650898637
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1696497484
Short name T498
Test name
Test status
Simulation time 465549114 ps
CPU time 23.82 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:52:15 PM PDT 24
Peak memory 196940 kb
Host smart-c6e02016-a624-4712-a5f9-a696c83fb3ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696497484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1696497484
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3183142450
Short name T699
Test name
Test status
Simulation time 177152403 ps
CPU time 1.02 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:51 PM PDT 24
Peak memory 196548 kb
Host smart-664b8d9a-15d4-4157-9e79-ecc02ab35ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183142450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3183142450
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.205057727
Short name T271
Test name
Test status
Simulation time 58973013 ps
CPU time 1.45 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 196884 kb
Host smart-93239386-2a70-4d9e-b712-9d6344d1599f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205057727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.205057727
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2302265121
Short name T323
Test name
Test status
Simulation time 254274916 ps
CPU time 3.56 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 198056 kb
Host smart-37f2a65c-0011-417d-ba73-0a18229302b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302265121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2302265121
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.797767718
Short name T176
Test name
Test status
Simulation time 391175395 ps
CPU time 2.12 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:53 PM PDT 24
Peak memory 195860 kb
Host smart-1794feff-0f9e-4cc8-bc5b-2628816e1a50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797767718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
797767718
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1518882166
Short name T632
Test name
Test status
Simulation time 27017711 ps
CPU time 0.78 seconds
Started Apr 02 12:51:46 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 195464 kb
Host smart-33d207ec-26f1-4e15-8000-4b0502b535c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518882166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1518882166
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.866101208
Short name T562
Test name
Test status
Simulation time 189126759 ps
CPU time 1.08 seconds
Started Apr 02 12:51:46 PM PDT 24
Finished Apr 02 12:51:47 PM PDT 24
Peak memory 196780 kb
Host smart-d5b70a77-4119-43ee-b9db-449e1a08e749
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866101208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.866101208
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1108706396
Short name T662
Test name
Test status
Simulation time 512894948 ps
CPU time 1.54 seconds
Started Apr 02 12:51:51 PM PDT 24
Finished Apr 02 12:51:53 PM PDT 24
Peak memory 197976 kb
Host smart-3ccc31aa-2b06-4e21-b73a-64d3af6e108e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108706396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1108706396
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3569929905
Short name T116
Test name
Test status
Simulation time 35246033 ps
CPU time 1.37 seconds
Started Apr 02 12:51:49 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195572 kb
Host smart-577067aa-bb23-457c-8448-d15298fbebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569929905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3569929905
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3782118782
Short name T127
Test name
Test status
Simulation time 221098695 ps
CPU time 1.07 seconds
Started Apr 02 12:51:47 PM PDT 24
Finished Apr 02 12:51:48 PM PDT 24
Peak memory 195816 kb
Host smart-910e7b68-1672-4e31-bd2d-93100650a0e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782118782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3782118782
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2467117915
Short name T208
Test name
Test status
Simulation time 15108474152 ps
CPU time 197.36 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:55:09 PM PDT 24
Peak memory 198160 kb
Host smart-b0c83a3d-29c1-4e76-8ea2-8e846c9ff8f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467117915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2467117915
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.375732019
Short name T62
Test name
Test status
Simulation time 50944889317 ps
CPU time 823.93 seconds
Started Apr 02 12:51:51 PM PDT 24
Finished Apr 02 01:05:35 PM PDT 24
Peak memory 198232 kb
Host smart-fc238cb2-cfb9-4e56-b2c8-d04abf08a171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=375732019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.375732019
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1672639608
Short name T389
Test name
Test status
Simulation time 19638197 ps
CPU time 0.55 seconds
Started Apr 02 12:51:57 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 193924 kb
Host smart-4ab9451b-e2f9-4b77-b572-52ab0d90e590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672639608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1672639608
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2565884877
Short name T345
Test name
Test status
Simulation time 30909100 ps
CPU time 0.8 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 195380 kb
Host smart-99563ce5-f4c9-47cd-a6db-a3b8f1902d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565884877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2565884877
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3326429254
Short name T357
Test name
Test status
Simulation time 531219576 ps
CPU time 16.66 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:52:14 PM PDT 24
Peak memory 197968 kb
Host smart-af977feb-e4a7-4bc3-8ec5-a77efda431d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326429254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3326429254
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.119524861
Short name T387
Test name
Test status
Simulation time 210675121 ps
CPU time 0.93 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 197220 kb
Host smart-ef0644a8-e7ce-4c09-9b18-7fee408fab14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119524861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.119524861
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2003012225
Short name T377
Test name
Test status
Simulation time 169521129 ps
CPU time 0.99 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:52 PM PDT 24
Peak memory 195920 kb
Host smart-91fb088f-c428-471b-a929-369bcc88f90f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003012225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2003012225
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1889743108
Short name T167
Test name
Test status
Simulation time 87159774 ps
CPU time 3.3 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:55 PM PDT 24
Peak memory 198068 kb
Host smart-59dc5e37-69c1-45b7-a14d-14842b85151a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889743108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1889743108
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1543888144
Short name T549
Test name
Test status
Simulation time 25619482 ps
CPU time 0.87 seconds
Started Apr 02 12:51:49 PM PDT 24
Finished Apr 02 12:51:50 PM PDT 24
Peak memory 195192 kb
Host smart-811263e4-1695-48ac-9aba-aaf23b55ad4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543888144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1543888144
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1807120640
Short name T114
Test name
Test status
Simulation time 105705416 ps
CPU time 1.17 seconds
Started Apr 02 12:51:51 PM PDT 24
Finished Apr 02 12:51:53 PM PDT 24
Peak memory 196512 kb
Host smart-0fab1641-9c61-4496-9652-a30e04078b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807120640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1807120640
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4238826254
Short name T593
Test name
Test status
Simulation time 232514701 ps
CPU time 1.3 seconds
Started Apr 02 12:51:52 PM PDT 24
Finished Apr 02 12:51:54 PM PDT 24
Peak memory 197068 kb
Host smart-fdc39fc7-ae39-41cb-b3f6-c475fc6d67e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238826254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4238826254
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2813779377
Short name T611
Test name
Test status
Simulation time 678459489 ps
CPU time 6.04 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:52:01 PM PDT 24
Peak memory 197936 kb
Host smart-88500fc3-9b15-4eaf-972f-aff66b5e6527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813779377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2813779377
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.795438935
Short name T607
Test name
Test status
Simulation time 101446216 ps
CPU time 1.56 seconds
Started Apr 02 12:51:50 PM PDT 24
Finished Apr 02 12:51:53 PM PDT 24
Peak memory 196740 kb
Host smart-c93240fe-abb4-4f47-9d88-ad2fa95121a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795438935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.795438935
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2345519833
Short name T299
Test name
Test status
Simulation time 49571963 ps
CPU time 1.38 seconds
Started Apr 02 12:51:49 PM PDT 24
Finished Apr 02 12:51:51 PM PDT 24
Peak memory 196844 kb
Host smart-16f6894f-1920-4297-b4ab-52b452b1c643
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345519833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2345519833
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.757651095
Short name T244
Test name
Test status
Simulation time 13950296136 ps
CPU time 179.02 seconds
Started Apr 02 12:51:55 PM PDT 24
Finished Apr 02 12:54:54 PM PDT 24
Peak memory 198148 kb
Host smart-292dc767-39f8-4e1a-a905-075ee9f8941a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757651095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.757651095
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2930857631
Short name T58
Test name
Test status
Simulation time 74347244001 ps
CPU time 1597.91 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 01:18:34 PM PDT 24
Peak memory 198176 kb
Host smart-570b59d2-6d63-45bf-a83e-2c53be60fb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2930857631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2930857631
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1026888708
Short name T501
Test name
Test status
Simulation time 19389647 ps
CPU time 0.58 seconds
Started Apr 02 12:51:57 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 193880 kb
Host smart-0d6bde38-64c9-43a9-bba7-09d674932f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026888708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1026888708
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2009282772
Short name T615
Test name
Test status
Simulation time 65840366 ps
CPU time 0.85 seconds
Started Apr 02 12:51:57 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 195568 kb
Host smart-4b99eacc-d0a6-4368-9bed-dbd7ce918a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009282772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2009282772
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.4135115835
Short name T30
Test name
Test status
Simulation time 123676114 ps
CPU time 4.61 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 196732 kb
Host smart-b81ecf2b-3c8b-4625-b914-317d43a68dc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135115835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.4135115835
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1025852579
Short name T8
Test name
Test status
Simulation time 74989789 ps
CPU time 0.74 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:55 PM PDT 24
Peak memory 195296 kb
Host smart-2ead9ff8-abb6-40a9-950d-aca175ea6d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025852579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1025852579
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2333620754
Short name T466
Test name
Test status
Simulation time 1273340972 ps
CPU time 1.33 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:51:57 PM PDT 24
Peak memory 197072 kb
Host smart-c7f61538-60ed-45e7-a0a7-2dbefe555cc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333620754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2333620754
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1829944968
Short name T668
Test name
Test status
Simulation time 28138190 ps
CPU time 1.23 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:56 PM PDT 24
Peak memory 196412 kb
Host smart-e1369c8a-3b88-4767-bf3e-1b7081bbf42c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829944968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1829944968
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2221934715
Short name T502
Test name
Test status
Simulation time 150616348 ps
CPU time 3.33 seconds
Started Apr 02 12:51:55 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 197992 kb
Host smart-47a2ed8d-a843-4787-8bd3-4a8f939b595e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221934715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2221934715
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.323429669
Short name T470
Test name
Test status
Simulation time 77513953 ps
CPU time 1.39 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:52:00 PM PDT 24
Peak memory 197028 kb
Host smart-304066af-5600-4be0-8403-591b551c18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323429669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.323429669
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2981042615
Short name T629
Test name
Test status
Simulation time 12945170 ps
CPU time 0.63 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 194252 kb
Host smart-c4252448-ea94-4d35-8135-82fd95438e40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981042615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2981042615
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2565189483
Short name T174
Test name
Test status
Simulation time 1270901594 ps
CPU time 5.49 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 197948 kb
Host smart-d37de4e4-fc59-4e9b-9fc8-3205fcc9ce39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565189483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2565189483
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3779410199
Short name T618
Test name
Test status
Simulation time 460692019 ps
CPU time 1.18 seconds
Started Apr 02 12:51:54 PM PDT 24
Finished Apr 02 12:51:55 PM PDT 24
Peak memory 195848 kb
Host smart-23d64014-d183-490b-bbdb-aa64f7183f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779410199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3779410199
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1422202359
Short name T354
Test name
Test status
Simulation time 92133535 ps
CPU time 1.49 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 195512 kb
Host smart-b4807c07-6cf3-4762-810b-02a73039c871
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422202359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1422202359
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2059783736
Short name T476
Test name
Test status
Simulation time 3371272807 ps
CPU time 102.76 seconds
Started Apr 02 12:51:55 PM PDT 24
Finished Apr 02 12:53:38 PM PDT 24
Peak memory 198180 kb
Host smart-811b21b1-f878-4d5b-86c3-39b79fe79358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059783736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2059783736
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.616417936
Short name T257
Test name
Test status
Simulation time 37414337 ps
CPU time 0.57 seconds
Started Apr 02 12:52:03 PM PDT 24
Finished Apr 02 12:52:04 PM PDT 24
Peak memory 194596 kb
Host smart-f9205c5c-8b99-4c96-ab79-e4bda273d729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616417936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.616417936
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1272616904
Short name T310
Test name
Test status
Simulation time 15038005 ps
CPU time 0.62 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 194844 kb
Host smart-26f3dba7-9c78-4455-8fe7-b1ac613c268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272616904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1272616904
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2455141494
Short name T94
Test name
Test status
Simulation time 3873742208 ps
CPU time 24.39 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:25 PM PDT 24
Peak memory 197032 kb
Host smart-8f914091-3694-43f5-85d6-eedf734ce5f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455141494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2455141494
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3756276925
Short name T227
Test name
Test status
Simulation time 218731902 ps
CPU time 0.87 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:51:59 PM PDT 24
Peak memory 196804 kb
Host smart-4e734b1a-0743-49ca-92d6-0deaa55d82c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756276925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3756276925
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.239137599
Short name T145
Test name
Test status
Simulation time 105462207 ps
CPU time 0.95 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:01 PM PDT 24
Peak memory 196816 kb
Host smart-64526c72-2b77-473f-9863-32376f8856a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239137599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.239137599
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3531108894
Short name T261
Test name
Test status
Simulation time 143860802 ps
CPU time 1.74 seconds
Started Apr 02 12:51:59 PM PDT 24
Finished Apr 02 12:52:01 PM PDT 24
Peak memory 198052 kb
Host smart-00184c46-1ce6-4480-b83b-51209fd90806
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531108894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3531108894
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.4089724921
Short name T460
Test name
Test status
Simulation time 1257461866 ps
CPU time 2.6 seconds
Started Apr 02 12:52:03 PM PDT 24
Finished Apr 02 12:52:05 PM PDT 24
Peak memory 197172 kb
Host smart-f569caaf-36dc-480c-91d1-12804764989e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089724921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.4089724921
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.78765210
Short name T458
Test name
Test status
Simulation time 19268786 ps
CPU time 0.79 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:51:57 PM PDT 24
Peak memory 195572 kb
Host smart-1df5072b-453b-4ff1-9173-e9dc60553ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78765210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.78765210
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2106658133
Short name T614
Test name
Test status
Simulation time 135770695 ps
CPU time 1.29 seconds
Started Apr 02 12:51:55 PM PDT 24
Finished Apr 02 12:51:56 PM PDT 24
Peak memory 196580 kb
Host smart-108250e0-dd18-468b-9161-b1b3e10181cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106658133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2106658133
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1766792959
Short name T169
Test name
Test status
Simulation time 823701506 ps
CPU time 3.98 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:04 PM PDT 24
Peak memory 196344 kb
Host smart-c10f921a-4146-468c-b0cf-defd9d93c448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766792959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1766792959
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.674385472
Short name T137
Test name
Test status
Simulation time 149378648 ps
CPU time 0.95 seconds
Started Apr 02 12:51:59 PM PDT 24
Finished Apr 02 12:52:00 PM PDT 24
Peak memory 196580 kb
Host smart-7ef9bd12-aa71-4ff4-965e-eee8e4d8c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674385472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.674385472
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4034928550
Short name T437
Test name
Test status
Simulation time 545800033 ps
CPU time 1.4 seconds
Started Apr 02 12:51:56 PM PDT 24
Finished Apr 02 12:51:58 PM PDT 24
Peak memory 196672 kb
Host smart-223bd6b2-ac09-457f-b7e3-e05e3bbe023c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034928550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4034928550
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3969313488
Short name T528
Test name
Test status
Simulation time 8978252524 ps
CPU time 120.38 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:53:59 PM PDT 24
Peak memory 198204 kb
Host smart-161e8dde-b593-405a-a70a-711037dbea9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969313488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3969313488
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3038300593
Short name T60
Test name
Test status
Simulation time 39346275801 ps
CPU time 954.77 seconds
Started Apr 02 12:51:57 PM PDT 24
Finished Apr 02 01:07:52 PM PDT 24
Peak memory 198208 kb
Host smart-7e596713-3fad-4733-81f6-a0a9acce04c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3038300593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3038300593
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1172258394
Short name T290
Test name
Test status
Simulation time 13590298 ps
CPU time 0.56 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 192788 kb
Host smart-09d6975c-5f64-4d73-9b4a-fc2c8acd8cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172258394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1172258394
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.823405969
Short name T350
Test name
Test status
Simulation time 196237314 ps
CPU time 0.64 seconds
Started Apr 02 12:51:59 PM PDT 24
Finished Apr 02 12:52:00 PM PDT 24
Peak memory 194008 kb
Host smart-070c3e86-ea4f-44b0-adcc-bfc06e644eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823405969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.823405969
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.4163962273
Short name T507
Test name
Test status
Simulation time 1463947063 ps
CPU time 24.15 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 12:52:25 PM PDT 24
Peak memory 197968 kb
Host smart-ec242247-6f99-48b0-9972-0d95e433a508
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163962273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.4163962273
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2697622209
Short name T265
Test name
Test status
Simulation time 565995562 ps
CPU time 0.89 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 12:52:02 PM PDT 24
Peak memory 196036 kb
Host smart-890f4fd8-ea75-4566-b1b2-f17eadc7efea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697622209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2697622209
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1734249152
Short name T108
Test name
Test status
Simulation time 27820981 ps
CPU time 0.85 seconds
Started Apr 02 12:52:02 PM PDT 24
Finished Apr 02 12:52:03 PM PDT 24
Peak memory 197308 kb
Host smart-5739abb7-48e4-42e2-88f7-ac63d1d230ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734249152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1734249152
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1789753997
Short name T50
Test name
Test status
Simulation time 28914616 ps
CPU time 1.23 seconds
Started Apr 02 12:52:03 PM PDT 24
Finished Apr 02 12:52:04 PM PDT 24
Peak memory 196484 kb
Host smart-a8364112-aa07-46ee-bc19-855a5d8d2ca3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789753997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1789753997
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1697744745
Short name T349
Test name
Test status
Simulation time 43179000 ps
CPU time 1.2 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 196940 kb
Host smart-2e6d28e0-8ac2-4681-9e4d-002cc81e10f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697744745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1697744745
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.58190774
Short name T617
Test name
Test status
Simulation time 43146707 ps
CPU time 0.7 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 12:52:02 PM PDT 24
Peak memory 195416 kb
Host smart-818c0dd8-24d8-4713-8fac-24200755c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58190774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.58190774
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1664141089
Short name T26
Test name
Test status
Simulation time 103893059 ps
CPU time 0.98 seconds
Started Apr 02 12:51:58 PM PDT 24
Finished Apr 02 12:52:00 PM PDT 24
Peak memory 195872 kb
Host smart-d36413aa-7fe1-45dd-9d74-6faa9cd506bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664141089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1664141089
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.992502684
Short name T625
Test name
Test status
Simulation time 1910239378 ps
CPU time 3.14 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:04 PM PDT 24
Peak memory 197956 kb
Host smart-0f7452bd-703d-4d90-8853-6748f7163c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992502684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.992502684
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3557446303
Short name T385
Test name
Test status
Simulation time 36096415 ps
CPU time 1.04 seconds
Started Apr 02 12:51:59 PM PDT 24
Finished Apr 02 12:52:00 PM PDT 24
Peak memory 196516 kb
Host smart-96bb8668-635e-4717-be56-41269bc57f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557446303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3557446303
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1742762637
Short name T99
Test name
Test status
Simulation time 71811214 ps
CPU time 1.19 seconds
Started Apr 02 12:51:59 PM PDT 24
Finished Apr 02 12:52:01 PM PDT 24
Peak memory 195532 kb
Host smart-0e21266b-50d0-4e9e-b461-cec8f68da2ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742762637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1742762637
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3344914854
Short name T131
Test name
Test status
Simulation time 24344433421 ps
CPU time 81.82 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 12:53:23 PM PDT 24
Peak memory 198096 kb
Host smart-d130d7fb-f77d-4d0e-b610-b3961c33baed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344914854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3344914854
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1461040662
Short name T523
Test name
Test status
Simulation time 143579885970 ps
CPU time 1105.85 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 01:10:27 PM PDT 24
Peak memory 198252 kb
Host smart-856203bf-1427-4c80-927e-02b9ca5ecd5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1461040662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1461040662
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2448763713
Short name T226
Test name
Test status
Simulation time 30657982 ps
CPU time 0.55 seconds
Started Apr 02 12:52:14 PM PDT 24
Finished Apr 02 12:52:15 PM PDT 24
Peak memory 193916 kb
Host smart-1ccbb31a-7365-4c5c-ac4b-917542ef98d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448763713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2448763713
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3478304607
Short name T445
Test name
Test status
Simulation time 543728428 ps
CPU time 0.87 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 196552 kb
Host smart-ec67bae2-2d3d-472b-9340-d4f74bcb4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478304607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3478304607
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2673632153
Short name T633
Test name
Test status
Simulation time 337578182 ps
CPU time 17.21 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:23 PM PDT 24
Peak memory 196948 kb
Host smart-c5c93cfe-487e-48bf-939f-c9223871c6a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673632153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2673632153
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1586357682
Short name T319
Test name
Test status
Simulation time 292205386 ps
CPU time 0.99 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 196460 kb
Host smart-79ac64b3-3020-4a10-9412-d39f2a8571aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586357682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1586357682
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.4142959651
Short name T292
Test name
Test status
Simulation time 147456926 ps
CPU time 1.01 seconds
Started Apr 02 12:52:14 PM PDT 24
Finished Apr 02 12:52:15 PM PDT 24
Peak memory 195816 kb
Host smart-09cacd0f-bfe1-46f6-8345-6f37e4af7ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142959651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.4142959651
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2014014105
Short name T178
Test name
Test status
Simulation time 213528018 ps
CPU time 2.33 seconds
Started Apr 02 12:52:03 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 196448 kb
Host smart-87edad63-0e73-4a02-958e-44a1a614413c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014014105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2014014105
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.495359068
Short name T335
Test name
Test status
Simulation time 75442395 ps
CPU time 2.38 seconds
Started Apr 02 12:52:14 PM PDT 24
Finished Apr 02 12:52:17 PM PDT 24
Peak memory 196576 kb
Host smart-1e1e16a0-20af-4454-8a2e-9beef47b84f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495359068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
495359068
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.529328110
Short name T488
Test name
Test status
Simulation time 652912158 ps
CPU time 1.39 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:02 PM PDT 24
Peak memory 198036 kb
Host smart-66e3979e-c1fd-4713-8c5c-f033316b6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529328110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.529328110
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.936576097
Short name T469
Test name
Test status
Simulation time 20910075 ps
CPU time 0.88 seconds
Started Apr 02 12:52:07 PM PDT 24
Finished Apr 02 12:52:08 PM PDT 24
Peak memory 195976 kb
Host smart-35f0d295-ca3d-41de-8e46-fdc6f786a6f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936576097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.936576097
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2473355843
Short name T683
Test name
Test status
Simulation time 66224023 ps
CPU time 2.83 seconds
Started Apr 02 12:52:04 PM PDT 24
Finished Apr 02 12:52:07 PM PDT 24
Peak memory 197936 kb
Host smart-72a549d2-c8bb-4a0f-8867-001fc2012d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473355843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2473355843
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3666081105
Short name T293
Test name
Test status
Simulation time 82817565 ps
CPU time 1.25 seconds
Started Apr 02 12:52:00 PM PDT 24
Finished Apr 02 12:52:02 PM PDT 24
Peak memory 195644 kb
Host smart-2afc6fc7-2ea0-4eef-afbd-3c30f9b8b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666081105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3666081105
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1723774852
Short name T654
Test name
Test status
Simulation time 160515472 ps
CPU time 1.27 seconds
Started Apr 02 12:52:01 PM PDT 24
Finished Apr 02 12:52:02 PM PDT 24
Peak memory 195840 kb
Host smart-5df6cda1-e820-4612-9c65-518d3c49aaf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723774852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1723774852
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.769192923
Short name T360
Test name
Test status
Simulation time 12429123580 ps
CPU time 182.29 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:55:08 PM PDT 24
Peak memory 198172 kb
Host smart-d1332840-2e74-40ca-ad04-45f3a8dd3b34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769192923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.769192923
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2511933678
Short name T45
Test name
Test status
Simulation time 15700471 ps
CPU time 0.57 seconds
Started Apr 02 12:52:09 PM PDT 24
Finished Apr 02 12:52:10 PM PDT 24
Peak memory 194116 kb
Host smart-c0105758-0250-4cf3-9305-c448b697fea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511933678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2511933678
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1815941332
Short name T23
Test name
Test status
Simulation time 85051929 ps
CPU time 0.76 seconds
Started Apr 02 12:52:11 PM PDT 24
Finished Apr 02 12:52:12 PM PDT 24
Peak memory 195268 kb
Host smart-a28e2c91-5ad1-4ec1-b94c-02f738f87bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815941332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1815941332
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1099442748
Short name T331
Test name
Test status
Simulation time 200344178 ps
CPU time 9.93 seconds
Started Apr 02 12:52:13 PM PDT 24
Finished Apr 02 12:52:23 PM PDT 24
Peak memory 196444 kb
Host smart-cb00d74f-a306-48ea-8631-fd3a25cbbcae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099442748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1099442748
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.539431608
Short name T573
Test name
Test status
Simulation time 242161988 ps
CPU time 1 seconds
Started Apr 02 12:52:06 PM PDT 24
Finished Apr 02 12:52:07 PM PDT 24
Peak memory 197012 kb
Host smart-202aba76-9a97-4db9-a715-d78ad85eb755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539431608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.539431608
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3362555636
Short name T650
Test name
Test status
Simulation time 108325575 ps
CPU time 1.1 seconds
Started Apr 02 12:52:14 PM PDT 24
Finished Apr 02 12:52:15 PM PDT 24
Peak memory 196080 kb
Host smart-d07b7d08-1692-448d-b7cb-38304a244eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362555636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3362555636
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.723311090
Short name T426
Test name
Test status
Simulation time 34583454 ps
CPU time 1.49 seconds
Started Apr 02 12:52:05 PM PDT 24
Finished Apr 02 12:52:07 PM PDT 24
Peak memory 196616 kb
Host smart-f95fe120-35c5-4d9b-9983-b0ff7b543030
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723311090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.723311090
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1123911163
Short name T542
Test name
Test status
Simulation time 48427450 ps
CPU time 1.23 seconds
Started Apr 02 12:52:11 PM PDT 24
Finished Apr 02 12:52:13 PM PDT 24
Peak memory 196352 kb
Host smart-f2593e5b-ef43-4f69-8d98-1cef024b09a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123911163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1123911163
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3375468525
Short name T613
Test name
Test status
Simulation time 81664425 ps
CPU time 1.04 seconds
Started Apr 02 12:52:04 PM PDT 24
Finished Apr 02 12:52:05 PM PDT 24
Peak memory 195812 kb
Host smart-762c33ec-1d7d-41e9-9f19-26b23254df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375468525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3375468525
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3825428710
Short name T97
Test name
Test status
Simulation time 50769084 ps
CPU time 0.77 seconds
Started Apr 02 12:52:07 PM PDT 24
Finished Apr 02 12:52:08 PM PDT 24
Peak memory 196140 kb
Host smart-d22ce292-fa1e-4128-a96b-4860e80d2e5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825428710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3825428710
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2045552545
Short name T4
Test name
Test status
Simulation time 246608949 ps
CPU time 1.96 seconds
Started Apr 02 12:52:04 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 197912 kb
Host smart-9341ffce-2176-44ba-87d0-6a526a9611a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045552545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2045552545
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3185805597
Short name T281
Test name
Test status
Simulation time 334714507 ps
CPU time 1.13 seconds
Started Apr 02 12:52:07 PM PDT 24
Finished Apr 02 12:52:08 PM PDT 24
Peak memory 195552 kb
Host smart-7f1f9c53-5beb-41f1-8ef2-96fa5f762842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185805597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3185805597
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3201850128
Short name T138
Test name
Test status
Simulation time 82789532 ps
CPU time 1.44 seconds
Started Apr 02 12:52:04 PM PDT 24
Finished Apr 02 12:52:06 PM PDT 24
Peak memory 196792 kb
Host smart-c9c25e70-eb01-49cc-9d0d-b478d2227d46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201850128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3201850128
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3898024633
Short name T384
Test name
Test status
Simulation time 30387750120 ps
CPU time 184.2 seconds
Started Apr 02 12:52:11 PM PDT 24
Finished Apr 02 12:55:16 PM PDT 24
Peak memory 198164 kb
Host smart-544f9556-60c7-48ca-abfb-ffba31521f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898024633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3898024633
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3292916911
Short name T587
Test name
Test status
Simulation time 69465058549 ps
CPU time 439.69 seconds
Started Apr 02 12:52:12 PM PDT 24
Finished Apr 02 12:59:32 PM PDT 24
Peak memory 198256 kb
Host smart-cc40443c-b194-4ecc-a756-6d8666c9a8dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3292916911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3292916911
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1211806502
Short name T245
Test name
Test status
Simulation time 12345097 ps
CPU time 0.63 seconds
Started Apr 02 12:50:06 PM PDT 24
Finished Apr 02 12:50:07 PM PDT 24
Peak memory 194652 kb
Host smart-c9fb3555-9bc5-4aa2-b4f2-5dcd480d4d75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211806502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1211806502
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1387834412
Short name T594
Test name
Test status
Simulation time 281762967 ps
CPU time 0.73 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 195120 kb
Host smart-2befeb52-cbfd-4c6c-bef0-97818c9990e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387834412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1387834412
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1254837045
Short name T533
Test name
Test status
Simulation time 297204023 ps
CPU time 14.15 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 196988 kb
Host smart-86ffbbcc-f46b-4788-a5fd-1c7aab10b2c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254837045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1254837045
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.886792257
Short name T532
Test name
Test status
Simulation time 61393823 ps
CPU time 0.91 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 197200 kb
Host smart-45dce0b6-ce28-4258-a92b-82bc2e94c346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886792257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.886792257
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.590393819
Short name T314
Test name
Test status
Simulation time 552806100 ps
CPU time 1.11 seconds
Started Apr 02 12:50:02 PM PDT 24
Finished Apr 02 12:50:03 PM PDT 24
Peak memory 195636 kb
Host smart-a65eae39-fb59-4fd7-a338-7ebbb32f13d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590393819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.590393819
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.280736869
Short name T305
Test name
Test status
Simulation time 20926548 ps
CPU time 0.96 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 196088 kb
Host smart-d1831ba5-2589-47f3-bcab-387b7332b570
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280736869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.280736869
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2175328156
Short name T400
Test name
Test status
Simulation time 39999135 ps
CPU time 1.07 seconds
Started Apr 02 12:50:04 PM PDT 24
Finished Apr 02 12:50:05 PM PDT 24
Peak memory 196336 kb
Host smart-d7088654-f0ee-49e1-ab97-e6a15c058234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175328156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2175328156
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.234136632
Short name T494
Test name
Test status
Simulation time 27394304 ps
CPU time 0.75 seconds
Started Apr 02 12:50:04 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 196208 kb
Host smart-71c816b9-fb2d-4517-b1fb-3ea83aed61e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234136632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.234136632
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.490120058
Short name T328
Test name
Test status
Simulation time 14482904 ps
CPU time 0.66 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 12:50:04 PM PDT 24
Peak memory 194340 kb
Host smart-aa76ab5e-900e-45bd-b055-9cf0d5393715
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490120058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.490120058
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1221465324
Short name T181
Test name
Test status
Simulation time 115834247 ps
CPU time 1.63 seconds
Started Apr 02 12:50:04 PM PDT 24
Finished Apr 02 12:50:06 PM PDT 24
Peak memory 198016 kb
Host smart-40376a61-59bc-4f53-85d2-d4a4689092ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221465324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1221465324
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2185520354
Short name T496
Test name
Test status
Simulation time 379239424 ps
CPU time 1.22 seconds
Started Apr 02 12:50:08 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 195852 kb
Host smart-06f11fb3-aba9-4b41-8616-4e9c743c9482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185520354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2185520354
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.723446026
Short name T413
Test name
Test status
Simulation time 61247741 ps
CPU time 1.06 seconds
Started Apr 02 12:50:08 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 195752 kb
Host smart-8689b487-2a93-471a-87ea-41df2233adb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723446026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.723446026
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2124830750
Short name T187
Test name
Test status
Simulation time 2802633540 ps
CPU time 32.11 seconds
Started Apr 02 12:50:06 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 198172 kb
Host smart-3a1ac480-6d30-4165-9aa1-195188812c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124830750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2124830750
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2855260223
Short name T674
Test name
Test status
Simulation time 363553972232 ps
CPU time 1870.39 seconds
Started Apr 02 12:50:03 PM PDT 24
Finished Apr 02 01:21:13 PM PDT 24
Peak memory 198240 kb
Host smart-e49f0024-20e9-4831-8162-86ddf383acd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2855260223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2855260223
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1077251067
Short name T44
Test name
Test status
Simulation time 26737736 ps
CPU time 0.63 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:11 PM PDT 24
Peak memory 194076 kb
Host smart-cec0e7f6-8047-4e5a-9ca8-30dede422b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077251067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1077251067
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3230473130
Short name T148
Test name
Test status
Simulation time 86854868 ps
CPU time 0.75 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:11 PM PDT 24
Peak memory 195404 kb
Host smart-7ba81825-dd97-4d3e-9760-e0a6275c7987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230473130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3230473130
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1373527399
Short name T251
Test name
Test status
Simulation time 443139141 ps
CPU time 14.78 seconds
Started Apr 02 12:50:07 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 195500 kb
Host smart-5775497b-ca04-49a0-a03e-7bdcbe6c79ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373527399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1373527399
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.368207745
Short name T9
Test name
Test status
Simulation time 93495991 ps
CPU time 1.11 seconds
Started Apr 02 12:50:07 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 196596 kb
Host smart-6eebc6e1-1947-4d87-8e8d-857133ea1ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368207745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.368207745
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4108877979
Short name T159
Test name
Test status
Simulation time 47647242 ps
CPU time 1.22 seconds
Started Apr 02 12:50:06 PM PDT 24
Finished Apr 02 12:50:07 PM PDT 24
Peak memory 197012 kb
Host smart-779e4376-207e-4ba9-9ac0-d6049886d4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108877979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4108877979
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2980638723
Short name T588
Test name
Test status
Simulation time 418883008 ps
CPU time 3.89 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:14 PM PDT 24
Peak memory 198060 kb
Host smart-e91e8bc4-ac8f-495c-9604-318c9a306426
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980638723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2980638723
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4034997404
Short name T324
Test name
Test status
Simulation time 534006568 ps
CPU time 3.19 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:13 PM PDT 24
Peak memory 198064 kb
Host smart-1c5542cc-20f1-41c2-bab3-fa20af763af9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034997404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4034997404
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2850366296
Short name T619
Test name
Test status
Simulation time 56700078 ps
CPU time 1.13 seconds
Started Apr 02 12:50:05 PM PDT 24
Finished Apr 02 12:50:06 PM PDT 24
Peak memory 196516 kb
Host smart-d8ee38e9-851f-4de5-9762-d29d30e48712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850366296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2850366296
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.550715164
Short name T421
Test name
Test status
Simulation time 120620055 ps
CPU time 1.22 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:11 PM PDT 24
Peak memory 196956 kb
Host smart-047d7314-e01c-4247-8762-da7e39cfbc8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550715164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.550715164
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1879720409
Short name T274
Test name
Test status
Simulation time 118425019 ps
CPU time 2.79 seconds
Started Apr 02 12:50:09 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 197996 kb
Host smart-98553b2d-5313-4f36-a7ad-6ac6a1b3801e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879720409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1879720409
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2118614973
Short name T651
Test name
Test status
Simulation time 110383018 ps
CPU time 1.3 seconds
Started Apr 02 12:50:07 PM PDT 24
Finished Apr 02 12:50:09 PM PDT 24
Peak memory 197928 kb
Host smart-c0308960-d7ec-4a3b-8d20-0ed3c77a4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118614973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2118614973
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1108418174
Short name T518
Test name
Test status
Simulation time 104455298 ps
CPU time 1.19 seconds
Started Apr 02 12:50:07 PM PDT 24
Finished Apr 02 12:50:08 PM PDT 24
Peak memory 195668 kb
Host smart-90a39db2-f6f0-42e0-a0fb-eb6f9acaa933
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108418174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1108418174
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2248544991
Short name T558
Test name
Test status
Simulation time 11144577617 ps
CPU time 84.6 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:51:35 PM PDT 24
Peak memory 198128 kb
Host smart-827d0bca-3fbb-46c5-b14e-5f80b89ae138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248544991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2248544991
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4235163934
Short name T119
Test name
Test status
Simulation time 14326523 ps
CPU time 0.59 seconds
Started Apr 02 12:50:13 PM PDT 24
Finished Apr 02 12:50:14 PM PDT 24
Peak memory 194604 kb
Host smart-d60f46e4-285f-4426-a490-1ab419a75073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235163934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4235163934
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.869060541
Short name T165
Test name
Test status
Simulation time 25162451 ps
CPU time 0.73 seconds
Started Apr 02 12:50:11 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 194908 kb
Host smart-f2cd558c-a976-488b-8052-0aff63f7316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869060541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.869060541
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1952237688
Short name T149
Test name
Test status
Simulation time 2524887573 ps
CPU time 21.17 seconds
Started Apr 02 12:50:17 PM PDT 24
Finished Apr 02 12:50:38 PM PDT 24
Peak memory 196716 kb
Host smart-ab9d3172-f73e-4331-8147-2022eeb6b631
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952237688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1952237688
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2732976892
Short name T635
Test name
Test status
Simulation time 105154986 ps
CPU time 0.63 seconds
Started Apr 02 12:50:16 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 194396 kb
Host smart-c0f7ab44-12a8-470b-be05-c9c67b7fa547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732976892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2732976892
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3953333743
Short name T312
Test name
Test status
Simulation time 28260313 ps
CPU time 0.78 seconds
Started Apr 02 12:50:11 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 195508 kb
Host smart-0a1c2df6-39dc-4b37-830d-700179a99990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953333743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3953333743
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.431888162
Short name T218
Test name
Test status
Simulation time 125817472 ps
CPU time 2.49 seconds
Started Apr 02 12:50:14 PM PDT 24
Finished Apr 02 12:50:16 PM PDT 24
Peak memory 197844 kb
Host smart-4954a6c0-5b90-4505-8866-5bcbc8e82f42
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431888162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.431888162
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.524924247
Short name T586
Test name
Test status
Simulation time 352556093 ps
CPU time 1.82 seconds
Started Apr 02 12:50:11 PM PDT 24
Finished Apr 02 12:50:15 PM PDT 24
Peak memory 195760 kb
Host smart-332a4962-ea06-4f09-ab04-2a8a25ca1cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524924247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.524924247
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.261785071
Short name T393
Test name
Test status
Simulation time 42699772 ps
CPU time 1.07 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:12 PM PDT 24
Peak memory 195760 kb
Host smart-0660dc65-948e-4648-a324-bf701d384958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261785071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.261785071
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2185893891
Short name T701
Test name
Test status
Simulation time 415811188 ps
CPU time 0.96 seconds
Started Apr 02 12:50:12 PM PDT 24
Finished Apr 02 12:50:15 PM PDT 24
Peak memory 195980 kb
Host smart-fa1ae825-aa01-4bb6-af96-858187d88f79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185893891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2185893891
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3115750874
Short name T684
Test name
Test status
Simulation time 2215092628 ps
CPU time 3.05 seconds
Started Apr 02 12:50:17 PM PDT 24
Finished Apr 02 12:50:20 PM PDT 24
Peak memory 198044 kb
Host smart-e8b7ff65-67b8-4222-87c4-a3a8e46bf453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115750874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3115750874
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3422316471
Short name T539
Test name
Test status
Simulation time 36378566 ps
CPU time 1 seconds
Started Apr 02 12:50:10 PM PDT 24
Finished Apr 02 12:50:11 PM PDT 24
Peak memory 195820 kb
Host smart-6067d608-2593-4f72-9e59-3d6d17d479a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422316471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3422316471
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.912585693
Short name T423
Test name
Test status
Simulation time 161500567 ps
CPU time 0.97 seconds
Started Apr 02 12:50:12 PM PDT 24
Finished Apr 02 12:50:15 PM PDT 24
Peak memory 196364 kb
Host smart-f6786a9d-a477-4773-9968-961e4bb43393
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912585693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.912585693
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3270551772
Short name T639
Test name
Test status
Simulation time 5605735417 ps
CPU time 153.65 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:52:54 PM PDT 24
Peak memory 198148 kb
Host smart-c49295bb-75d5-42fb-bece-240d946d36d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270551772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3270551772
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1125049354
Short name T372
Test name
Test status
Simulation time 21717259 ps
CPU time 0.58 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 193808 kb
Host smart-a0d76018-b925-4b61-8152-cd94d79711f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125049354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1125049354
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2605543091
Short name T238
Test name
Test status
Simulation time 20335611 ps
CPU time 0.67 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:16 PM PDT 24
Peak memory 194720 kb
Host smart-99f3d873-28f2-4438-b782-fc6fc0ed3c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605543091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2605543091
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2867970766
Short name T379
Test name
Test status
Simulation time 976400279 ps
CPU time 5.08 seconds
Started Apr 02 12:50:18 PM PDT 24
Finished Apr 02 12:50:23 PM PDT 24
Peak memory 197056 kb
Host smart-396a6ddd-740a-4550-9205-1c8ea111f11a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867970766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2867970766
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.7095620
Short name T289
Test name
Test status
Simulation time 95043318 ps
CPU time 0.86 seconds
Started Apr 02 12:50:18 PM PDT 24
Finished Apr 02 12:50:19 PM PDT 24
Peak memory 196780 kb
Host smart-68254335-ee1a-4963-a283-fb5355bd8439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7095620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.7095620
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.4228903681
Short name T201
Test name
Test status
Simulation time 104960080 ps
CPU time 0.87 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:16 PM PDT 24
Peak memory 196448 kb
Host smart-ae94aeb0-c2b4-44d9-9481-6cb58a0deaee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228903681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.4228903681
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1339296263
Short name T442
Test name
Test status
Simulation time 215702283 ps
CPU time 1.87 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 198048 kb
Host smart-169b598d-c850-4c51-a7d5-8b00130cd2b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339296263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1339296263
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.4022541028
Short name T32
Test name
Test status
Simulation time 132901421 ps
CPU time 2.16 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:23 PM PDT 24
Peak memory 197900 kb
Host smart-153985d4-a570-4603-80f4-424db0a605b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022541028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
4022541028
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3650186044
Short name T467
Test name
Test status
Simulation time 66820374 ps
CPU time 1.33 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 198032 kb
Host smart-451cf275-75b7-4c35-91d0-f30e8d1de2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650186044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3650186044
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3040797475
Short name T547
Test name
Test status
Simulation time 104694452 ps
CPU time 1.27 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 197972 kb
Host smart-471f2de8-ef98-46ce-accc-de2ff7337751
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040797475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3040797475
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2624630965
Short name T315
Test name
Test status
Simulation time 439972930 ps
CPU time 4.22 seconds
Started Apr 02 12:50:24 PM PDT 24
Finished Apr 02 12:50:29 PM PDT 24
Peak memory 198020 kb
Host smart-3b3f2675-9dd7-4faf-bf83-2aa7c0dc805f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624630965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2624630965
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3926584941
Short name T222
Test name
Test status
Simulation time 133495813 ps
CPU time 1.21 seconds
Started Apr 02 12:50:15 PM PDT 24
Finished Apr 02 12:50:17 PM PDT 24
Peak memory 195632 kb
Host smart-f69fff6b-d782-4ac1-8b30-a00f8422a9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926584941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3926584941
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1304661617
Short name T242
Test name
Test status
Simulation time 153135665 ps
CPU time 1.46 seconds
Started Apr 02 12:50:14 PM PDT 24
Finished Apr 02 12:50:16 PM PDT 24
Peak memory 196880 kb
Host smart-348d878c-9bf7-43a0-9931-cc7095136bce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304661617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1304661617
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.245563683
Short name T367
Test name
Test status
Simulation time 53200613915 ps
CPU time 114.12 seconds
Started Apr 02 12:50:18 PM PDT 24
Finished Apr 02 12:52:13 PM PDT 24
Peak memory 198100 kb
Host smart-2fc31d41-1e1a-4198-a364-f128a73cfd89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245563683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.245563683
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1646780649
Short name T211
Test name
Test status
Simulation time 46462084 ps
CPU time 0.56 seconds
Started Apr 02 12:50:22 PM PDT 24
Finished Apr 02 12:50:24 PM PDT 24
Peak memory 194128 kb
Host smart-2b769735-9bad-422e-ae07-1ac6f767e313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646780649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1646780649
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3117569383
Short name T93
Test name
Test status
Simulation time 19141190 ps
CPU time 0.66 seconds
Started Apr 02 12:50:23 PM PDT 24
Finished Apr 02 12:50:25 PM PDT 24
Peak memory 194084 kb
Host smart-54130df8-31c3-4fe4-9435-08d667709ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117569383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3117569383
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1883737362
Short name T645
Test name
Test status
Simulation time 534464427 ps
CPU time 14.75 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:35 PM PDT 24
Peak memory 196920 kb
Host smart-17020101-ed3c-431c-890c-8a49d518fa03
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883737362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1883737362
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1622662416
Short name T322
Test name
Test status
Simulation time 104839583 ps
CPU time 0.99 seconds
Started Apr 02 12:50:20 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 196568 kb
Host smart-9060b716-46a1-4efd-a215-e7548599875b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622662416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1622662416
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1260773122
Short name T221
Test name
Test status
Simulation time 251995369 ps
CPU time 1.01 seconds
Started Apr 02 12:50:20 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 195732 kb
Host smart-5d8ce3ff-9a36-43cc-b880-e70faca17ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260773122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1260773122
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1696546704
Short name T435
Test name
Test status
Simulation time 48967948 ps
CPU time 2 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 197944 kb
Host smart-2979b64f-b372-4111-8804-a631d61013cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696546704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1696546704
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3533565701
Short name T455
Test name
Test status
Simulation time 487978519 ps
CPU time 3.36 seconds
Started Apr 02 12:50:18 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 197168 kb
Host smart-23d19723-96e6-462e-96af-d24826d4ae71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533565701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3533565701
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.801806280
Short name T598
Test name
Test status
Simulation time 44998165 ps
CPU time 0.99 seconds
Started Apr 02 12:50:20 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 195856 kb
Host smart-a38ad700-a81e-4df6-985d-b884372d54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801806280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.801806280
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2928388849
Short name T449
Test name
Test status
Simulation time 35170243 ps
CPU time 1.28 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 198056 kb
Host smart-80ffcefb-38df-4ab8-b9b0-3d2d7a9c74a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928388849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2928388849
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3987704655
Short name T640
Test name
Test status
Simulation time 2076822603 ps
CPU time 5.98 seconds
Started Apr 02 12:50:21 PM PDT 24
Finished Apr 02 12:50:28 PM PDT 24
Peak memory 197992 kb
Host smart-163f9722-2929-486e-82de-3ea17c90b85a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987704655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3987704655
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.388205859
Short name T375
Test name
Test status
Simulation time 69682429 ps
CPU time 1.27 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:22 PM PDT 24
Peak memory 196824 kb
Host smart-fc0c0faf-91c1-4fc9-a7b5-711e9be1c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388205859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.388205859
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3161451485
Short name T669
Test name
Test status
Simulation time 54250301 ps
CPU time 0.85 seconds
Started Apr 02 12:50:19 PM PDT 24
Finished Apr 02 12:50:21 PM PDT 24
Peak memory 195260 kb
Host smart-4c572bd3-4b4c-47ae-88ce-8a14ee26c547
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161451485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3161451485
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.732855171
Short name T267
Test name
Test status
Simulation time 33539361435 ps
CPU time 249.88 seconds
Started Apr 02 12:50:20 PM PDT 24
Finished Apr 02 12:54:31 PM PDT 24
Peak memory 198164 kb
Host smart-55b238fb-01d9-4ab3-9fb9-cddef431c355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732855171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.732855171
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.804708304
Short name T845
Test name
Test status
Simulation time 44536414 ps
CPU time 0.81 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 191988 kb
Host smart-423b6768-129f-48a5-bf72-74422e52652c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=804708304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.804708304
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2570137129
Short name T842
Test name
Test status
Simulation time 192133149 ps
CPU time 1.39 seconds
Started Apr 02 12:25:51 PM PDT 24
Finished Apr 02 12:25:52 PM PDT 24
Peak memory 192132 kb
Host smart-e423982b-5b0f-4b8e-9d33-feb4994c28cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570137129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2570137129
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1190086871
Short name T850
Test name
Test status
Simulation time 84816433 ps
CPU time 1.55 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 198444 kb
Host smart-719fa604-2cf4-4bc4-add4-6fdf7cd44c9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1190086871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1190086871
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923001223
Short name T882
Test name
Test status
Simulation time 135317444 ps
CPU time 1.27 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:04 PM PDT 24
Peak memory 198452 kb
Host smart-56994a38-342b-42e1-af45-217fb65b7f96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923001223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1923001223
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.514044367
Short name T908
Test name
Test status
Simulation time 112071410 ps
CPU time 1.14 seconds
Started Apr 02 12:25:56 PM PDT 24
Finished Apr 02 12:25:58 PM PDT 24
Peak memory 196988 kb
Host smart-74d79c02-5478-42c5-9174-779ce7cf77d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=514044367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.514044367
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3442345643
Short name T852
Test name
Test status
Simulation time 78176897 ps
CPU time 0.66 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 191948 kb
Host smart-b3c4ee7c-b74b-4784-85df-34d76a0e8464
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442345643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3442345643
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2710320057
Short name T903
Test name
Test status
Simulation time 134405744 ps
CPU time 1.2 seconds
Started Apr 02 12:25:59 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 198364 kb
Host smart-9f13a482-4bae-414b-8889-a6c2d5240591
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2710320057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2710320057
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761725640
Short name T902
Test name
Test status
Simulation time 84715479 ps
CPU time 1.26 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 198448 kb
Host smart-1ebb8647-369e-4baf-a13b-b79580004737
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761725640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2761725640
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2424169998
Short name T885
Test name
Test status
Simulation time 37854591 ps
CPU time 0.86 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 196592 kb
Host smart-ef446c18-b509-4ac2-ad03-434dc13169ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2424169998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2424169998
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.553884117
Short name T865
Test name
Test status
Simulation time 82490359 ps
CPU time 1.18 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 196864 kb
Host smart-0ee73799-b69e-47f1-8902-1a14d5ca519b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553884117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.553884117
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1928360994
Short name T854
Test name
Test status
Simulation time 164385217 ps
CPU time 0.93 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 192116 kb
Host smart-4e7fbd41-1552-492e-bf05-c93ca34cf448
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1928360994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1928360994
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1428609137
Short name T920
Test name
Test status
Simulation time 75135809 ps
CPU time 0.98 seconds
Started Apr 02 12:25:49 PM PDT 24
Finished Apr 02 12:25:51 PM PDT 24
Peak memory 192104 kb
Host smart-111ab858-f697-447f-a22c-a22c834d8cf5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428609137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1428609137
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2719188378
Short name T895
Test name
Test status
Simulation time 156199095 ps
CPU time 1.02 seconds
Started Apr 02 12:25:54 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 192084 kb
Host smart-c152929d-9c3e-4fb1-8f1b-e585f6259202
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2719188378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2719188378
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2912811401
Short name T906
Test name
Test status
Simulation time 369541305 ps
CPU time 1.46 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 196912 kb
Host smart-c5f18a68-27d8-4b01-8c25-64312c4c0ee2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912811401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2912811401
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3550862580
Short name T915
Test name
Test status
Simulation time 112587683 ps
CPU time 0.9 seconds
Started Apr 02 12:26:00 PM PDT 24
Finished Apr 02 12:26:01 PM PDT 24
Peak memory 191924 kb
Host smart-58e8a199-828c-49ed-8a14-d983e6ded7b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3550862580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3550862580
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4076660633
Short name T929
Test name
Test status
Simulation time 40085809 ps
CPU time 1.01 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:02 PM PDT 24
Peak memory 197828 kb
Host smart-7b55ceb4-975a-4726-a071-7f25ca64f116
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076660633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4076660633
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3790877481
Short name T860
Test name
Test status
Simulation time 150945326 ps
CPU time 1.1 seconds
Started Apr 02 12:25:46 PM PDT 24
Finished Apr 02 12:25:47 PM PDT 24
Peak memory 192492 kb
Host smart-8058aa19-0a1a-486f-a178-b0d247776924
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3790877481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3790877481
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.270304310
Short name T924
Test name
Test status
Simulation time 420683725 ps
CPU time 1.47 seconds
Started Apr 02 12:25:53 PM PDT 24
Finished Apr 02 12:25:55 PM PDT 24
Peak memory 192072 kb
Host smart-39621c76-1ba2-4028-8ef1-a4709d89aaa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270304310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.270304310
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4274605085
Short name T917
Test name
Test status
Simulation time 302032562 ps
CPU time 1.19 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 192084 kb
Host smart-d971902d-792e-4274-bce2-55b8baa92154
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4274605085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4274605085
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3810020428
Short name T878
Test name
Test status
Simulation time 554152471 ps
CPU time 1.37 seconds
Started Apr 02 12:25:55 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 198460 kb
Host smart-551d8b60-a63f-4747-91a4-dad4682d8c11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810020428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3810020428
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2165966087
Short name T847
Test name
Test status
Simulation time 958979387 ps
CPU time 1.11 seconds
Started Apr 02 12:25:57 PM PDT 24
Finished Apr 02 12:25:58 PM PDT 24
Peak memory 192136 kb
Host smart-059f6725-9996-42ce-8cfa-08f418b182c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2165966087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2165966087
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1330195489
Short name T888
Test name
Test status
Simulation time 90646138 ps
CPU time 0.89 seconds
Started Apr 02 12:25:55 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 191948 kb
Host smart-cdf6bdd4-51f6-43a9-8fff-05bbd710a806
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330195489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1330195489
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2509789991
Short name T839
Test name
Test status
Simulation time 202115842 ps
CPU time 1.16 seconds
Started Apr 02 12:26:44 PM PDT 24
Finished Apr 02 12:26:46 PM PDT 24
Peak memory 192108 kb
Host smart-4d69021f-2f89-415b-a2cf-2d695a06f4ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2509789991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2509789991
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.929850709
Short name T896
Test name
Test status
Simulation time 38070302 ps
CPU time 0.92 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 191960 kb
Host smart-394b30a3-b81b-4149-9fa8-d17a691b4a26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929850709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.929850709
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.565452899
Short name T900
Test name
Test status
Simulation time 396478923 ps
CPU time 1.5 seconds
Started Apr 02 12:25:53 PM PDT 24
Finished Apr 02 12:25:55 PM PDT 24
Peak memory 192132 kb
Host smart-9e078ae2-9e14-4d7b-985e-8d902efa6dde
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=565452899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.565452899
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1059911328
Short name T856
Test name
Test status
Simulation time 41739887 ps
CPU time 0.89 seconds
Started Apr 02 12:25:51 PM PDT 24
Finished Apr 02 12:25:52 PM PDT 24
Peak memory 197888 kb
Host smart-dd44f866-2b7c-4109-8ee8-1bb71eb1fe75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059911328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1059911328
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1699097430
Short name T932
Test name
Test status
Simulation time 93185587 ps
CPU time 1.27 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 198456 kb
Host smart-f7b0f1b7-fb04-4b6d-b779-9ccff02c4d53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1699097430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1699097430
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1511664175
Short name T881
Test name
Test status
Simulation time 139341128 ps
CPU time 1.33 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 192104 kb
Host smart-b65c4c03-0787-4893-9b7d-a808a2a20eaf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511664175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1511664175
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.596618354
Short name T890
Test name
Test status
Simulation time 257255712 ps
CPU time 1.33 seconds
Started Apr 02 12:25:57 PM PDT 24
Finished Apr 02 12:25:58 PM PDT 24
Peak memory 196924 kb
Host smart-43cdfbfa-2358-452c-b462-01718f4565af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=596618354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.596618354
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2212541534
Short name T887
Test name
Test status
Simulation time 101739264 ps
CPU time 0.99 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 192140 kb
Host smart-e5892baa-4979-4442-9de9-171688f941b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212541534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2212541534
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1095459889
Short name T931
Test name
Test status
Simulation time 34437474 ps
CPU time 1.01 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 197068 kb
Host smart-43621e81-6af5-4d1c-ba67-0a71241391cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1095459889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1095459889
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1971630612
Short name T921
Test name
Test status
Simulation time 177008367 ps
CPU time 0.82 seconds
Started Apr 02 12:25:59 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 191880 kb
Host smart-17adf20c-11d9-4bc7-9385-e95a0406b310
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971630612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1971630612
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.775993546
Short name T869
Test name
Test status
Simulation time 42813362 ps
CPU time 0.96 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:02 PM PDT 24
Peak memory 191888 kb
Host smart-bf72674e-e394-42f6-88ca-c81468589b4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=775993546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.775993546
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.357314804
Short name T841
Test name
Test status
Simulation time 39344269 ps
CPU time 0.73 seconds
Started Apr 02 12:26:34 PM PDT 24
Finished Apr 02 12:26:35 PM PDT 24
Peak memory 191928 kb
Host smart-094f6fb7-e20b-4219-9d3d-ccb143227c8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357314804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.357314804
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1747329527
Short name T919
Test name
Test status
Simulation time 89003877 ps
CPU time 1.28 seconds
Started Apr 02 12:25:55 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 196912 kb
Host smart-23618565-6ec9-460d-adac-f23e37d1b245
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1747329527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1747329527
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735898487
Short name T843
Test name
Test status
Simulation time 136343912 ps
CPU time 0.81 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 191992 kb
Host smart-e369339b-1456-4916-951f-d694117cf4b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735898487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.735898487
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.567522674
Short name T901
Test name
Test status
Simulation time 48740657 ps
CPU time 0.94 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 198316 kb
Host smart-1c1ec38a-869b-4742-96a7-791518115784
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=567522674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.567522674
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.545159837
Short name T879
Test name
Test status
Simulation time 83009371 ps
CPU time 1.01 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 192228 kb
Host smart-41d03b97-d1a6-44e9-8a11-ef98bd52b612
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545159837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.545159837
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1792664906
Short name T861
Test name
Test status
Simulation time 138924956 ps
CPU time 1.3 seconds
Started Apr 02 12:25:58 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 198412 kb
Host smart-2f7044c9-8cf4-49e6-b064-6011ebdf2c8c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1792664906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1792664906
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1042060542
Short name T873
Test name
Test status
Simulation time 56205687 ps
CPU time 1.13 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192112 kb
Host smart-12bb3154-4a58-47f3-a32e-519f9102072f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042060542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1042060542
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2030119289
Short name T875
Test name
Test status
Simulation time 96802683 ps
CPU time 1.16 seconds
Started Apr 02 12:25:54 PM PDT 24
Finished Apr 02 12:25:56 PM PDT 24
Peak memory 192132 kb
Host smart-4e998110-72c2-4da5-96f7-b8b3f00a96a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2030119289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2030119289
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625119976
Short name T863
Test name
Test status
Simulation time 44823715 ps
CPU time 1.15 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 196852 kb
Host smart-e82daa07-d45d-48a5-b7ea-cbcf3aca9fcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625119976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1625119976
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1187302106
Short name T883
Test name
Test status
Simulation time 26733554 ps
CPU time 0.8 seconds
Started Apr 02 12:26:20 PM PDT 24
Finished Apr 02 12:26:21 PM PDT 24
Peak memory 192080 kb
Host smart-fbde7bd3-df73-4a8b-99d4-59e091e3fd35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1187302106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1187302106
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2559356213
Short name T923
Test name
Test status
Simulation time 46119960 ps
CPU time 1 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 192112 kb
Host smart-5be25a37-568e-4455-b279-1969969cdd12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559356213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2559356213
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1177347611
Short name T884
Test name
Test status
Simulation time 135172263 ps
CPU time 0.97 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 192152 kb
Host smart-7c4d5840-80f4-457f-be77-4fbfacf6289c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1177347611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1177347611
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4123202071
Short name T905
Test name
Test status
Simulation time 176247338 ps
CPU time 0.98 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 198432 kb
Host smart-56e81682-ad94-4862-a6d4-4501e42e880d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123202071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4123202071
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1726855491
Short name T870
Test name
Test status
Simulation time 54869060 ps
CPU time 1.23 seconds
Started Apr 02 12:25:51 PM PDT 24
Finished Apr 02 12:25:53 PM PDT 24
Peak memory 192080 kb
Host smart-315540b8-8587-482e-ae2e-757eed15d8ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1726855491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1726855491
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527440499
Short name T904
Test name
Test status
Simulation time 230613164 ps
CPU time 1.19 seconds
Started Apr 02 12:26:00 PM PDT 24
Finished Apr 02 12:26:01 PM PDT 24
Peak memory 192124 kb
Host smart-2f3f5600-cdd5-4180-8e5f-382dcf4ffdde
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527440499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3527440499
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.4157315495
Short name T893
Test name
Test status
Simulation time 624917270 ps
CPU time 1.32 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 192128 kb
Host smart-684493c6-b358-4cea-890c-17f7a5229ea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4157315495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.4157315495
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3807703009
Short name T876
Test name
Test status
Simulation time 211429266 ps
CPU time 1.1 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 198496 kb
Host smart-424563df-8183-4549-875c-40f4c5d2560d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807703009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3807703009
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2612924936
Short name T846
Test name
Test status
Simulation time 369234090 ps
CPU time 1.02 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 196780 kb
Host smart-77dc1431-5d4e-419a-9fdd-b46f60b5babd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2612924936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2612924936
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.589390122
Short name T880
Test name
Test status
Simulation time 62361563 ps
CPU time 0.96 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 192080 kb
Host smart-cf243cbb-3f21-4ebe-b631-6f4554106e49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589390122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.589390122
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3978614809
Short name T910
Test name
Test status
Simulation time 54613947 ps
CPU time 1.07 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 197040 kb
Host smart-1df7f6c1-4b0d-4d0c-9bce-78b19fde3c5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3978614809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3978614809
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.740072474
Short name T848
Test name
Test status
Simulation time 68819575 ps
CPU time 1.18 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 192120 kb
Host smart-4e97572e-a809-4c46-bdb3-56d8e922b1e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740072474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.740072474
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3004424304
Short name T855
Test name
Test status
Simulation time 116444744 ps
CPU time 1.35 seconds
Started Apr 02 12:25:55 PM PDT 24
Finished Apr 02 12:25:57 PM PDT 24
Peak memory 192112 kb
Host smart-5e55210b-f2ee-4922-842d-ecadf24ae33c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3004424304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3004424304
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3794625743
Short name T886
Test name
Test status
Simulation time 46423015 ps
CPU time 0.95 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 197876 kb
Host smart-e9c54183-05ed-4d09-8e46-eca2030f3315
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794625743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3794625743
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.888325320
Short name T891
Test name
Test status
Simulation time 77876511 ps
CPU time 1.03 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192136 kb
Host smart-e7239722-e0aa-4bbf-a953-c9b473da237c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=888325320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.888325320
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.652895979
Short name T926
Test name
Test status
Simulation time 48047431 ps
CPU time 0.97 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 191952 kb
Host smart-9e9848ef-a0eb-4e59-a8b7-e676bafaae7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652895979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.652895979
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3416340146
Short name T894
Test name
Test status
Simulation time 62333520 ps
CPU time 1.2 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192132 kb
Host smart-2ccadb56-fb5d-409a-ad24-e7790e040c3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3416340146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3416340146
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1233303463
Short name T864
Test name
Test status
Simulation time 84127068 ps
CPU time 0.84 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 191948 kb
Host smart-af17907a-3a6f-4e35-a6d3-1d29e03d03ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233303463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1233303463
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1544191299
Short name T933
Test name
Test status
Simulation time 43268153 ps
CPU time 1.31 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 192092 kb
Host smart-8e20f571-d3fa-4d70-b64d-c0fe168b8293
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1544191299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1544191299
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2810155338
Short name T858
Test name
Test status
Simulation time 134752075 ps
CPU time 1.18 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 192140 kb
Host smart-0393c946-45e8-4c04-8a41-1d93b0218d78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810155338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2810155338
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.967821819
Short name T857
Test name
Test status
Simulation time 202897007 ps
CPU time 0.85 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 191968 kb
Host smart-d4c86a87-a0e6-4687-9386-f95cd860f3e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=967821819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.967821819
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3272024928
Short name T922
Test name
Test status
Simulation time 269907807 ps
CPU time 0.95 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192016 kb
Host smart-a6148381-bf41-4228-95c4-fab6ee51fe03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272024928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3272024928
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3272818722
Short name T838
Test name
Test status
Simulation time 55897119 ps
CPU time 1.1 seconds
Started Apr 02 12:25:58 PM PDT 24
Finished Apr 02 12:25:59 PM PDT 24
Peak memory 192140 kb
Host smart-1a0c1932-630d-494c-9e01-1328dc388064
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3272818722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3272818722
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2221483922
Short name T930
Test name
Test status
Simulation time 91208649 ps
CPU time 1.24 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 192112 kb
Host smart-4763aae6-24e3-419b-990d-d511de9f0f4f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221483922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2221483922
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2445348654
Short name T844
Test name
Test status
Simulation time 102467212 ps
CPU time 1.36 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 192144 kb
Host smart-20e3b8b7-1550-44dc-83c6-8ce75433ffdf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2445348654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2445348654
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.329251912
Short name T907
Test name
Test status
Simulation time 26190923 ps
CPU time 0.8 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 196516 kb
Host smart-e07e5a07-51e1-46ea-80b3-afc02db3c518
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329251912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.329251912
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.920844569
Short name T866
Test name
Test status
Simulation time 89415191 ps
CPU time 1.01 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 197028 kb
Host smart-95920dd4-e41d-453d-923e-90209c35c6d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=920844569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.920844569
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765457000
Short name T912
Test name
Test status
Simulation time 75545064 ps
CPU time 1.23 seconds
Started Apr 02 12:25:43 PM PDT 24
Finished Apr 02 12:25:45 PM PDT 24
Peak memory 196800 kb
Host smart-e9dd86ba-dac4-418b-90d3-1d0e175c9d2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765457000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2765457000
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2708275698
Short name T862
Test name
Test status
Simulation time 117865396 ps
CPU time 0.99 seconds
Started Apr 02 12:25:57 PM PDT 24
Finished Apr 02 12:25:58 PM PDT 24
Peak memory 192156 kb
Host smart-83a3b0f6-d9ba-4435-9af6-bebaf4e82c9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2708275698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2708275698
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3691781743
Short name T867
Test name
Test status
Simulation time 58711797 ps
CPU time 1.06 seconds
Started Apr 02 12:25:59 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 191916 kb
Host smart-f2b06607-069c-4b75-a286-0d4e4baad2d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691781743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3691781743
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4275175886
Short name T892
Test name
Test status
Simulation time 74012350 ps
CPU time 1.26 seconds
Started Apr 02 12:25:59 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 192068 kb
Host smart-bc4195c2-ae64-4dc8-9b89-6ce97cb6f208
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4275175886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4275175886
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60791811
Short name T909
Test name
Test status
Simulation time 55735907 ps
CPU time 1.08 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:04 PM PDT 24
Peak memory 192060 kb
Host smart-30308018-be8d-405a-8ec9-647ace509fb8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60791811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.60791811
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1060856571
Short name T936
Test name
Test status
Simulation time 46437845 ps
CPU time 0.77 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 196616 kb
Host smart-332f435b-b142-4dd4-b123-d56563813dad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1060856571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1060856571
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946435100
Short name T918
Test name
Test status
Simulation time 93086160 ps
CPU time 0.95 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192196 kb
Host smart-0ce3d2ac-e817-4a81-b0ae-4b9c151890d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946435100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3946435100
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.343266126
Short name T851
Test name
Test status
Simulation time 214495061 ps
CPU time 1.52 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 192124 kb
Host smart-2200821b-a9ae-4a05-812f-3ce000f90117
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=343266126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.343266126
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.679483501
Short name T928
Test name
Test status
Simulation time 123188943 ps
CPU time 1.06 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 192208 kb
Host smart-2639e033-054e-4620-a304-8f61d5346e49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679483501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.679483501
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.433945068
Short name T871
Test name
Test status
Simulation time 66802234 ps
CPU time 0.93 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:04 PM PDT 24
Peak memory 191908 kb
Host smart-67f1c2fa-5cfa-4cca-a3f8-025f9879f3b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=433945068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.433945068
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.252733284
Short name T868
Test name
Test status
Simulation time 163782736 ps
CPU time 0.95 seconds
Started Apr 02 12:25:58 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 197604 kb
Host smart-d5564352-ba96-4bac-baa7-2fecfc786364
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252733284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.252733284
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4275140772
Short name T911
Test name
Test status
Simulation time 72556565 ps
CPU time 1.19 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 192100 kb
Host smart-2e01609c-3027-41d1-973c-19fd7fcd81bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4275140772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4275140772
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006312174
Short name T877
Test name
Test status
Simulation time 46055543 ps
CPU time 0.86 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 192148 kb
Host smart-fbd8bce3-4e01-42d0-b168-1b792954949b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006312174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2006312174
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.957323013
Short name T916
Test name
Test status
Simulation time 77763092 ps
CPU time 0.87 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 196652 kb
Host smart-034749f5-bad3-4ff1-8eff-091ad86de9e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=957323013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.957323013
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.631087899
Short name T849
Test name
Test status
Simulation time 304904959 ps
CPU time 1.43 seconds
Started Apr 02 12:25:57 PM PDT 24
Finished Apr 02 12:25:59 PM PDT 24
Peak memory 198388 kb
Host smart-2c83bda3-5e88-4a34-a372-febc1a9203e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631087899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.631087899
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2443001902
Short name T935
Test name
Test status
Simulation time 34632751 ps
CPU time 0.81 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 191884 kb
Host smart-ba824006-c30f-4f36-9fbf-9e05d02acedb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2443001902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2443001902
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388759395
Short name T899
Test name
Test status
Simulation time 152438048 ps
CPU time 0.86 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 191980 kb
Host smart-59205024-8c80-4349-b617-64cdb287633e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388759395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1388759395
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1584650139
Short name T840
Test name
Test status
Simulation time 508698920 ps
CPU time 0.92 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198268 kb
Host smart-d67942bb-df0a-49a7-827a-3f6899023439
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1584650139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1584650139
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3056996779
Short name T934
Test name
Test status
Simulation time 1051129492 ps
CPU time 1.38 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 192100 kb
Host smart-d5547a27-ee64-470b-8117-137d72f6a480
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056996779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3056996779
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2972631406
Short name T914
Test name
Test status
Simulation time 52204011 ps
CPU time 0.69 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 191908 kb
Host smart-336e43ad-df59-4203-a9eb-7bab09260243
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2972631406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2972631406
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.646017167
Short name T897
Test name
Test status
Simulation time 185819329 ps
CPU time 1.03 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 192164 kb
Host smart-4099b715-d94a-4328-9689-a1c6f0521990
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646017167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.646017167
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1482313533
Short name T889
Test name
Test status
Simulation time 88268364 ps
CPU time 1.24 seconds
Started Apr 02 12:25:58 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 192136 kb
Host smart-05cbec48-2f3a-4088-baa4-2401f162ffa8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1482313533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1482313533
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1491078779
Short name T913
Test name
Test status
Simulation time 80093988 ps
CPU time 0.96 seconds
Started Apr 02 12:26:00 PM PDT 24
Finished Apr 02 12:26:01 PM PDT 24
Peak memory 191980 kb
Host smart-c62f7694-2844-47c4-b958-7177c90cc8e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491078779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1491078779
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3662315702
Short name T898
Test name
Test status
Simulation time 322410597 ps
CPU time 1.31 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:02 PM PDT 24
Peak memory 192100 kb
Host smart-775ffdd2-0da9-4ef4-8452-42aca595b75f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3662315702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3662315702
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1945845651
Short name T859
Test name
Test status
Simulation time 78389996 ps
CPU time 0.94 seconds
Started Apr 02 12:25:51 PM PDT 24
Finished Apr 02 12:25:52 PM PDT 24
Peak memory 191960 kb
Host smart-203c2773-0ff6-447e-b040-6c2b0bcafaa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945845651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1945845651
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.836798165
Short name T853
Test name
Test status
Simulation time 243555838 ps
CPU time 1.3 seconds
Started Apr 02 12:25:53 PM PDT 24
Finished Apr 02 12:25:55 PM PDT 24
Peak memory 192152 kb
Host smart-9620b3d7-cce7-4d6c-9a68-172a73303544
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=836798165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.836798165
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4052801314
Short name T874
Test name
Test status
Simulation time 158644211 ps
CPU time 1.13 seconds
Started Apr 02 12:25:51 PM PDT 24
Finished Apr 02 12:25:52 PM PDT 24
Peak memory 196740 kb
Host smart-8bb95cdb-b042-4768-bedb-94b4a2232968
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052801314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4052801314
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3577639590
Short name T927
Test name
Test status
Simulation time 218399142 ps
CPU time 1.2 seconds
Started Apr 02 12:26:03 PM PDT 24
Finished Apr 02 12:26:04 PM PDT 24
Peak memory 198432 kb
Host smart-db8c5990-b62c-4dd3-8f83-57bc538292d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3577639590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3577639590
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.166398863
Short name T872
Test name
Test status
Simulation time 41905831 ps
CPU time 1.14 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 198376 kb
Host smart-572014b5-b997-42ee-a2a7-274ba734fdb2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166398863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.166398863
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2268458602
Short name T925
Test name
Test status
Simulation time 73836306 ps
CPU time 0.96 seconds
Started Apr 02 12:25:58 PM PDT 24
Finished Apr 02 12:25:59 PM PDT 24
Peak memory 198412 kb
Host smart-f79191b8-a220-43ad-a09c-2f6138b947fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2268458602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2268458602
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2583945577
Short name T937
Test name
Test status
Simulation time 334036205 ps
CPU time 1.1 seconds
Started Apr 02 12:25:54 PM PDT 24
Finished Apr 02 12:25:55 PM PDT 24
Peak memory 192132 kb
Host smart-42551104-3389-4c6e-95b7-2512f6a58955
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583945577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2583945577
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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