Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4810634	1			T25	660		T26	91		T1	36
all_pins[1]	4810634	1			T25	660		T26	91		T1	36
all_pins[2]	4810634	1			T25	660		T26	91		T1	36
all_pins[3]	4810634	1			T25	660		T26	91		T1	36
all_pins[4]	4810634	1			T25	660		T26	91		T1	36
all_pins[5]	4810634	1			T25	660		T26	91		T1	36
all_pins[6]	4810634	1			T25	660		T26	91		T1	36
all_pins[7]	4810634	1			T25	660		T26	91		T1	36
all_pins[8]	4810634	1			T25	660		T26	91		T1	36
all_pins[9]	4810634	1			T25	660		T26	91		T1	36
all_pins[10]	4810634	1			T25	660		T26	91		T1	36
all_pins[11]	4810634	1			T25	660		T26	91		T1	36
all_pins[12]	4810634	1			T25	660		T26	91		T1	36
all_pins[13]	4810634	1			T25	660		T26	91		T1	36
all_pins[14]	4810634	1			T25	660		T26	91		T1	36
all_pins[15]	4810634	1			T25	660		T26	91		T1	36
all_pins[16]	4810634	1			T25	660		T26	91		T1	36
all_pins[17]	4810634	1			T25	660		T26	91		T1	36
all_pins[18]	4810634	1			T25	660		T26	91		T1	36
all_pins[19]	4810634	1			T25	660		T26	91		T1	36
all_pins[20]	4810634	1			T25	660		T26	91		T1	36
all_pins[21]	4810634	1			T25	660		T26	91		T1	36
all_pins[22]	4810634	1			T25	660		T26	91		T1	36
all_pins[23]	4810634	1			T25	660		T26	91		T1	36
all_pins[24]	4810634	1			T25	660		T26	91		T1	36
all_pins[25]	4810634	1			T25	660		T26	91		T1	36
all_pins[26]	4810634	1			T25	660		T26	91		T1	36
all_pins[27]	4810634	1			T25	660		T26	91		T1	36
all_pins[28]	4810634	1			T25	660		T26	91		T1	36
all_pins[29]	4810634	1			T25	660		T26	91		T1	36
all_pins[30]	4810634	1			T25	660		T26	91		T1	36
all_pins[31]	4810634	1			T25	660		T26	91		T1	36

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	95640898	1			T25	12789		T26	1568		T1	866
values[0x1]	58299390	1			T25	8331		T26	1344		T1	286
transitions[0x0=>0x1]	34940565	1			T25	4869		T26	698		T1	171
transitions[0x1=>0x0]	34940416	1			T25	4868		T26	698		T1	171

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2992440	1			T25	325		T26	50		T1	36
all_pins[0]	values[0x1]	1818194	1			T25	335		T26	41		T11	1673
all_pins[0]	transitions[0x0=>0x1]	1126093	1			T25	220		T26	19		T11	962
all_pins[0]	transitions[0x1=>0x0]	1123324	1			T25	119		T26	17		T11	1145
all_pins[1]	values[0x0]	2987671	1			T25	373		T26	40		T1	30
all_pins[1]	values[0x1]	1822963	1			T25	287		T26	51		T1	6
all_pins[1]	transitions[0x0=>0x1]	1093237	1			T25	108		T26	26		T1	6
all_pins[1]	transitions[0x1=>0x0]	1088468	1			T25	156		T26	16		T11	933
all_pins[2]	values[0x0]	2993207	1			T25	417		T26	51		T1	33
all_pins[2]	values[0x1]	1817427	1			T25	243		T26	40		T1	3
all_pins[2]	transitions[0x0=>0x1]	1089062	1			T25	124		T26	15		T1	3
all_pins[2]	transitions[0x1=>0x0]	1094598	1			T25	168		T26	26		T1	6
all_pins[3]	values[0x0]	2987646	1			T25	386		T26	52		T1	25
all_pins[3]	values[0x1]	1822988	1			T25	274		T26	39		T1	11
all_pins[3]	transitions[0x0=>0x1]	1091835	1			T25	164		T26	19		T1	11
all_pins[3]	transitions[0x1=>0x0]	1086274	1			T25	133		T26	20		T1	3
all_pins[4]	values[0x0]	2983069	1			T25	406		T26	42		T1	20
all_pins[4]	values[0x1]	1827565	1			T25	254		T26	49		T1	16
all_pins[4]	transitions[0x0=>0x1]	1092493	1			T25	150		T26	27		T1	9
all_pins[4]	transitions[0x1=>0x0]	1087916	1			T25	170		T26	17		T1	4
all_pins[5]	values[0x0]	2987710	1			T25	419		T26	41		T1	28
all_pins[5]	values[0x1]	1822924	1			T25	241		T26	50		T1	8
all_pins[5]	transitions[0x0=>0x1]	1087883	1			T25	135		T26	22		T1	2
all_pins[5]	transitions[0x1=>0x0]	1092524	1			T25	148		T26	21		T1	10
all_pins[6]	values[0x0]	2987754	1			T25	389		T26	54		T1	36
all_pins[6]	values[0x1]	1822880	1			T25	271		T26	37		T11	1801
all_pins[6]	transitions[0x0=>0x1]	1090423	1			T25	155		T26	20		T11	1073
all_pins[6]	transitions[0x1=>0x0]	1090467	1			T25	125		T26	33		T1	8
all_pins[7]	values[0x0]	2984807	1			T25	452		T26	46		T1	33
all_pins[7]	values[0x1]	1825827	1			T25	208		T26	45		T1	3
all_pins[7]	transitions[0x0=>0x1]	1092032	1			T25	102		T26	23		T1	3
all_pins[7]	transitions[0x1=>0x0]	1089085	1			T25	165		T26	15		T11	1114
all_pins[8]	values[0x0]	2991621	1			T25	403		T26	45		T1	20
all_pins[8]	values[0x1]	1819013	1			T25	257		T26	46		T1	16
all_pins[8]	transitions[0x0=>0x1]	1088537	1			T25	185		T26	27		T1	13
all_pins[8]	transitions[0x1=>0x0]	1095351	1			T25	136		T26	26		T11	1146
all_pins[9]	values[0x0]	2989719	1			T25	485		T26	56		T1	20
all_pins[9]	values[0x1]	1820915	1			T25	175		T26	35		T1	16
all_pins[9]	transitions[0x0=>0x1]	1092686	1			T25	123		T26	14		T1	8
all_pins[9]	transitions[0x1=>0x0]	1090784	1			T25	205		T26	25		T1	8
all_pins[10]	values[0x0]	2986395	1			T25	399		T26	46		T1	25
all_pins[10]	values[0x1]	1824239	1			T25	261		T26	45		T1	11
all_pins[10]	transitions[0x0=>0x1]	1094423	1			T25	195		T26	29		T1	3
all_pins[10]	transitions[0x1=>0x0]	1091099	1			T25	109		T26	19		T1	8
all_pins[11]	values[0x0]	2986012	1			T25	407		T26	53		T1	21
all_pins[11]	values[0x1]	1824622	1			T25	253		T26	38		T1	15
all_pins[11]	transitions[0x0=>0x1]	1091850	1			T25	134		T26	20		T1	8
all_pins[11]	transitions[0x1=>0x0]	1091467	1			T25	142		T26	27		T1	4
all_pins[12]	values[0x0]	2987423	1			T25	419		T26	50		T1	25
all_pins[12]	values[0x1]	1823211	1			T25	241		T26	41		T1	11
all_pins[12]	transitions[0x0=>0x1]	1088383	1			T25	141		T26	25		T1	5
all_pins[12]	transitions[0x1=>0x0]	1089794	1			T25	153		T26	22		T1	9
all_pins[13]	values[0x0]	2987779	1			T25	447		T26	59		T1	29
all_pins[13]	values[0x1]	1822855	1			T25	213		T26	32		T1	7
all_pins[13]	transitions[0x0=>0x1]	1090930	1			T25	130		T26	21		T1	2
all_pins[13]	transitions[0x1=>0x0]	1091286	1			T25	158		T26	30		T1	6
all_pins[14]	values[0x0]	2993547	1			T25	380		T26	48		T1	25
all_pins[14]	values[0x1]	1817087	1			T25	280		T26	43		T1	11
all_pins[14]	transitions[0x0=>0x1]	1086249	1			T25	185		T26	24		T1	11
all_pins[14]	transitions[0x1=>0x0]	1092017	1			T25	118		T26	13		T1	7
all_pins[15]	values[0x0]	2994715	1			T25	413		T26	52		T1	13
all_pins[15]	values[0x1]	1815919	1			T25	247		T26	39		T1	23
all_pins[15]	transitions[0x0=>0x1]	1090048	1			T25	112		T26	17		T1	12
all_pins[15]	transitions[0x1=>0x0]	1091216	1			T25	145		T26	21		T11	1124
all_pins[16]	values[0x0]	2986162	1			T25	396		T26	48		T1	21
all_pins[16]	values[0x1]	1824472	1			T25	264		T26	43		T1	15
all_pins[16]	transitions[0x0=>0x1]	1094459	1			T25	201		T26	22		T1	3
all_pins[16]	transitions[0x1=>0x0]	1085906	1			T25	184		T26	18		T1	11
all_pins[17]	values[0x0]	2988022	1			T25	398		T26	49		T1	29
all_pins[17]	values[0x1]	1822612	1			T25	262		T26	42		T1	7
all_pins[17]	transitions[0x0=>0x1]	1091043	1			T25	145		T26	24		T1	4
all_pins[17]	transitions[0x1=>0x0]	1092903	1			T25	147		T26	25		T1	12
all_pins[18]	values[0x0]	2986576	1			T25	367		T26	48		T1	17
all_pins[18]	values[0x1]	1824058	1			T25	293		T26	43		T1	19
all_pins[18]	transitions[0x0=>0x1]	1090805	1			T25	175		T26	24		T1	12
all_pins[18]	transitions[0x1=>0x0]	1089359	1			T25	144		T26	23		T11	1052
all_pins[19]	values[0x0]	2987793	1			T25	389		T26	51		T1	32
all_pins[19]	values[0x1]	1822841	1			T25	271		T26	40		T1	4
all_pins[19]	transitions[0x0=>0x1]	1090114	1			T25	150		T26	23		T1	4
all_pins[19]	transitions[0x1=>0x0]	1091331	1			T25	172		T26	26		T1	19
all_pins[20]	values[0x0]	2987565	1			T25	392		T26	51		T1	33
all_pins[20]	values[0x1]	1823069	1			T25	268		T26	40		T1	3
all_pins[20]	transitions[0x0=>0x1]	1091592	1			T25	150		T26	21		T11	1151
all_pins[20]	transitions[0x1=>0x0]	1091364	1			T25	153		T26	21		T1	1
all_pins[21]	values[0x0]	2981701	1			T25	457		T26	45		T1	28
all_pins[21]	values[0x1]	1828933	1			T25	203		T26	46		T1	8
all_pins[21]	transitions[0x0=>0x1]	1094406	1			T25	125		T26	26		T1	6
all_pins[21]	transitions[0x1=>0x0]	1088542	1			T25	190		T26	20		T1	1
all_pins[22]	values[0x0]	2993318	1			T25	454		T26	58		T1	27
all_pins[22]	values[0x1]	1817316	1			T25	206		T26	33		T1	9
all_pins[22]	transitions[0x0=>0x1]	1085448	1			T25	156		T26	15		T1	8
all_pins[22]	transitions[0x1=>0x0]	1097065	1			T25	153		T26	28		T1	7
all_pins[23]	values[0x0]	2987789	1			T25	377		T26	52		T1	36
all_pins[23]	values[0x1]	1822845	1			T25	283		T26	39		T11	1818
all_pins[23]	transitions[0x0=>0x1]	1092937	1			T25	198		T26	22		T11	1048
all_pins[23]	transitions[0x1=>0x0]	1087408	1			T25	121		T26	16		T1	9
all_pins[24]	values[0x0]	2993325	1			T25	367		T26	43		T1	26
all_pins[24]	values[0x1]	1817309	1			T25	293		T26	48		T1	10
all_pins[24]	transitions[0x0=>0x1]	1088202	1			T25	168		T26	30		T1	10
all_pins[24]	transitions[0x1=>0x0]	1093738	1			T25	158		T26	21		T11	1044
all_pins[25]	values[0x0]	2991209	1			T25	423		T26	42		T1	36
all_pins[25]	values[0x1]	1819425	1			T25	237		T26	49		T11	1742
all_pins[25]	transitions[0x0=>0x1]	1094088	1			T25	105		T26	23		T11	1044
all_pins[25]	transitions[0x1=>0x0]	1091972	1			T25	161		T26	22		T1	10
all_pins[26]	values[0x0]	2991351	1			T25	321		T26	45		T1	30
all_pins[26]	values[0x1]	1819283	1			T25	339		T26	46		T1	6
all_pins[26]	transitions[0x0=>0x1]	1088981	1			T25	202		T26	18		T1	6
all_pins[26]	transitions[0x1=>0x0]	1089123	1			T25	100		T26	21		T11	1054
all_pins[27]	values[0x0]	2984856	1			T25	381		T26	45		T1	23
all_pins[27]	values[0x1]	1825778	1			T25	279		T26	46		T1	13
all_pins[27]	transitions[0x0=>0x1]	1095019	1			T25	133		T26	20		T1	7
all_pins[27]	transitions[0x1=>0x0]	1088524	1			T25	193		T26	20		T11	1109
all_pins[28]	values[0x0]	2991259	1			T25	335		T26	53		T1	25
all_pins[28]	values[0x1]	1819375	1			T25	325		T26	38		T1	11
all_pins[28]	transitions[0x0=>0x1]	1086195	1			T25	170		T26	22		T1	2
all_pins[28]	transitions[0x1=>0x0]	1092598	1			T25	124		T26	30		T1	4
all_pins[29]	values[0x0]	2984742	1			T25	369		T26	52		T1	25
all_pins[29]	values[0x1]	1825892	1			T25	291		T26	39		T1	11
all_pins[29]	transitions[0x0=>0x1]	1093595	1			T25	137		T26	20		T11	1013
all_pins[29]	transitions[0x1=>0x0]	1087078	1			T25	171		T26	19		T11	1125
all_pins[30]	values[0x0]	2988655	1			T25	418		T26	49		T1	23
all_pins[30]	values[0x1]	1821979	1			T25	242		T26	42		T1	13
all_pins[30]	transitions[0x0=>0x1]	1089332	1			T25	130		T26	23		T1	13
all_pins[30]	transitions[0x1=>0x0]	1093245	1			T25	179		T26	20		T1	11
all_pins[31]	values[0x0]	2995060	1			T25	425		T26	52		T1	36
all_pins[31]	values[0x1]	1815574	1			T25	235		T26	39		T11	1857
all_pins[31]	transitions[0x0=>0x1]	1088185	1			T25	161		T26	17		T11	1131
all_pins[31]	transitions[0x1=>0x0]	1094590	1			T25	168		T26	20		T1	13