Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	15816952	1			T25	1967		T26	49508		T1	54
all_values[1]	15816952	1			T25	1967		T26	49508		T1	54
all_values[2]	15816952	1			T25	1967		T26	49508		T1	54
all_values[3]	15816952	1			T25	1967		T26	49508		T1	54
all_values[4]	15816952	1			T25	1967		T26	49508		T1	54
all_values[5]	15816952	1			T25	1967		T26	49508		T1	54
all_values[6]	15816952	1			T25	1967		T26	49508		T1	54
all_values[7]	15816952	1			T25	1967		T26	49508		T1	54
all_values[8]	15816952	1			T25	1967		T26	49508		T1	54
all_values[9]	15816952	1			T25	1967		T26	49508		T1	54
all_values[10]	15816952	1			T25	1967		T26	49508		T1	54
all_values[11]	15816952	1			T25	1967		T26	49508		T1	54
all_values[12]	15816952	1			T25	1967		T26	49508		T1	54
all_values[13]	15816952	1			T25	1967		T26	49508		T1	54
all_values[14]	15816952	1			T25	1967		T26	49508		T1	54
all_values[15]	15816952	1			T25	1967		T26	49508		T1	54
all_values[16]	15816952	1			T25	1967		T26	49508		T1	54
all_values[17]	15816952	1			T25	1967		T26	49508		T1	54
all_values[18]	15816952	1			T25	1967		T26	49508		T1	54
all_values[19]	15816952	1			T25	1967		T26	49508		T1	54
all_values[20]	15816952	1			T25	1967		T26	49508		T1	54
all_values[21]	15816952	1			T25	1967		T26	49508		T1	54
all_values[22]	15816952	1			T25	1967		T26	49508		T1	54
all_values[23]	15816952	1			T25	1967		T26	49508		T1	54
all_values[24]	15816952	1			T25	1967		T26	49508		T1	54
all_values[25]	15816952	1			T25	1967		T26	49508		T1	54
all_values[26]	15816952	1			T25	1967		T26	49508		T1	54
all_values[27]	15816952	1			T25	1967		T26	49508		T1	54
all_values[28]	15816952	1			T25	1967		T26	49508		T1	54
all_values[29]	15816952	1			T25	1967		T26	49508		T1	54
all_values[30]	15816952	1			T25	1967		T26	49508		T1	54
all_values[31]	15816952	1			T25	1967		T26	49508		T1	54

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

285884778

1

T25

31553

T26

158425

T1

1266

auto[1]

220257686

1

T25

31391

T1

462

T11

211656

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107520455

1

T25

5296

T26

158425

T1

760

auto[1]

398622009

1

T25

57648

T1

968

T11

383398

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

500324876

1

T25

62944

T26

158425

T1

1663

auto[1]

5817588

1

T1

65

T11

6804

T2

1126

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2700803	1			T25	120		T26	49508		T1	27
all_values[0]	auto[0]	auto[0]	auto[1]	6152293	1			T25	683		T1	24		T11	6205
all_values[0]	auto[0]	auto[1]	auto[0]	662545	1			T25	60		T11	662		T2	73
all_values[0]	auto[0]	auto[1]	auto[1]	6119688	1			T25	1104		T11	5499		T2	302
all_values[0]	auto[1]	auto[0]	auto[1]	90889	1			T1	3		T11	121		T2	23
all_values[0]	auto[1]	auto[1]	auto[1]	90734	1			T11	107		T2	13		T13	1
all_values[1]	auto[0]	auto[0]	auto[0]	2695200	1			T25	71		T26	49508		T1	18
all_values[1]	auto[0]	auto[0]	auto[1]	6181071	1			T25	893		T1	21		T11	5933
all_values[1]	auto[0]	auto[1]	auto[0]	661149	1			T25	73		T1	4		T11	602
all_values[1]	auto[0]	auto[1]	auto[1]	6097674	1			T25	930		T1	8		T11	5934
all_values[1]	auto[1]	auto[0]	auto[1]	90853	1			T1	2		T11	93		T2	9
all_values[1]	auto[1]	auto[1]	auto[1]	91005	1			T1	1		T11	102		T2	29
all_values[2]	auto[0]	auto[0]	auto[0]	2685567	1			T25	121		T26	49508		T1	16
all_values[2]	auto[0]	auto[0]	auto[1]	6154348	1			T25	935		T1	25		T11	5128
all_values[2]	auto[0]	auto[1]	auto[0]	667027	1			T25	55		T1	8		T11	758
all_values[2]	auto[0]	auto[1]	auto[1]	6128334	1			T25	856		T1	3		T11	6542
all_values[2]	auto[1]	auto[0]	auto[1]	91352	1			T1	2		T11	94		T2	23
all_values[2]	auto[1]	auto[1]	auto[1]	90324	1			T11	108		T2	14		T13	5
all_values[3]	auto[0]	auto[0]	auto[0]	2699228	1			T25	119		T26	49508		T1	26
all_values[3]	auto[0]	auto[0]	auto[1]	6138390	1			T25	835		T1	14		T11	5643
all_values[3]	auto[0]	auto[1]	auto[0]	667068	1			T25	47		T11	680		T2	47
all_values[3]	auto[0]	auto[1]	auto[1]	6130717	1			T25	966		T1	12		T11	6040
all_values[3]	auto[1]	auto[0]	auto[1]	91426	1			T1	1		T11	124		T2	23
all_values[3]	auto[1]	auto[1]	auto[1]	90123	1			T1	1		T11	102		T2	21
all_values[4]	auto[0]	auto[0]	auto[0]	2696934	1			T25	86		T26	49508		T1	21
all_values[4]	auto[0]	auto[0]	auto[1]	6121190	1			T25	747		T1	12		T11	5912
all_values[4]	auto[0]	auto[1]	auto[0]	673781	1			T25	126		T11	631		T2	18
all_values[4]	auto[0]	auto[1]	auto[1]	6143231	1			T25	1008		T1	19		T11	5777
all_values[4]	auto[1]	auto[0]	auto[1]	90710	1			T1	1		T11	118		T2	12
all_values[4]	auto[1]	auto[1]	auto[1]	91106	1			T1	1		T11	86		T2	24
all_values[5]	auto[0]	auto[0]	auto[0]	2695890	1			T25	48		T26	49508		T1	23
all_values[5]	auto[0]	auto[0]	auto[1]	6149066	1			T25	1039		T1	9		T11	5623
all_values[5]	auto[0]	auto[1]	auto[0]	662180	1			T25	84		T1	11		T11	588
all_values[5]	auto[0]	auto[1]	auto[1]	6127981	1			T25	796		T1	8		T11	6233
all_values[5]	auto[1]	auto[0]	auto[1]	91104	1			T1	2		T11	116		T2	25
all_values[5]	auto[1]	auto[1]	auto[1]	90731	1			T1	1		T11	103		T2	11
all_values[6]	auto[0]	auto[0]	auto[0]	2693629	1			T25	62		T26	49508		T1	16
all_values[6]	auto[0]	auto[0]	auto[1]	6149249	1			T25	1009		T1	37		T11	6086
all_values[6]	auto[0]	auto[1]	auto[0]	663494	1			T25	36		T11	610		T2	33
all_values[6]	auto[0]	auto[1]	auto[1]	6128899	1			T25	860		T11	5737		T2	282
all_values[6]	auto[1]	auto[0]	auto[1]	90589	1			T1	1		T11	113		T2	19
all_values[6]	auto[1]	auto[1]	auto[1]	91092	1			T11	93		T2	13		T13	3
all_values[7]	auto[0]	auto[0]	auto[0]	2691719	1			T25	104		T26	49508		T1	36
all_values[7]	auto[0]	auto[0]	auto[1]	6121563	1			T25	936		T1	9		T11	6081
all_values[7]	auto[0]	auto[1]	auto[0]	661581	1			T25	162		T1	5		T11	532
all_values[7]	auto[0]	auto[1]	auto[1]	6160178	1			T25	765		T1	3		T11	5761
all_values[7]	auto[1]	auto[0]	auto[1]	90569	1			T1	1		T11	128		T2	26
all_values[7]	auto[1]	auto[1]	auto[1]	91342	1			T11	93		T2	7		T18	441
all_values[8]	auto[0]	auto[0]	auto[0]	2699981	1			T25	95		T26	49508		T1	18
all_values[8]	auto[0]	auto[0]	auto[1]	6150685	1			T25	886		T1	13		T11	6158
all_values[8]	auto[0]	auto[1]	auto[0]	664240	1			T25	60		T11	588		T2	28
all_values[8]	auto[0]	auto[1]	auto[1]	6120206	1			T25	926		T1	19		T11	5531
all_values[8]	auto[1]	auto[0]	auto[1]	91453	1			T1	2		T11	113		T2	13
all_values[8]	auto[1]	auto[1]	auto[1]	90387	1			T1	2		T11	97		T2	21
all_values[9]	auto[0]	auto[0]	auto[0]	2699480	1			T25	97		T26	49508		T1	16
all_values[9]	auto[0]	auto[0]	auto[1]	6185677	1			T25	1210		T1	16		T11	6772
all_values[9]	auto[0]	auto[1]	auto[0]	657063	1			T25	59		T11	635		T2	48
all_values[9]	auto[0]	auto[1]	auto[1]	6092410	1			T25	601		T1	18		T11	5004
all_values[9]	auto[1]	auto[0]	auto[1]	91436	1			T1	2		T11	83		T2	20
all_values[9]	auto[1]	auto[1]	auto[1]	90886	1			T1	2		T11	124		T2	5
all_values[10]	auto[0]	auto[0]	auto[0]	2692304	1			T25	49		T26	49508		T1	18
all_values[10]	auto[0]	auto[0]	auto[1]	6126456	1			T25	777		T1	23		T11	5716
all_values[10]	auto[0]	auto[1]	auto[0]	662014	1			T25	118		T11	764		T2	32
all_values[10]	auto[0]	auto[1]	auto[1]	6153912	1			T25	1023		T1	13		T11	5963
all_values[10]	auto[1]	auto[0]	auto[1]	91589	1			T11	129		T2	22		T13	8
all_values[10]	auto[1]	auto[1]	auto[1]	90677	1			T11	99		T2	14		T18	413
all_values[11]	auto[0]	auto[0]	auto[0]	2699817	1			T25	86		T26	49508		T1	13
all_values[11]	auto[0]	auto[0]	auto[1]	6124440	1			T25	1023		T1	20		T11	6062
all_values[11]	auto[0]	auto[1]	auto[0]	660501	1			T25	69		T11	713		T2	47
all_values[11]	auto[0]	auto[1]	auto[1]	6150578	1			T25	789		T1	20		T11	5536
all_values[11]	auto[1]	auto[0]	auto[1]	91280	1			T1	1		T11	124		T2	10
all_values[11]	auto[1]	auto[1]	auto[1]	90336	1			T11	102		T2	25		T13	1
all_values[12]	auto[0]	auto[0]	auto[0]	2706597	1			T25	27		T26	49508		T1	20
all_values[12]	auto[0]	auto[0]	auto[1]	6137816	1			T25	1060		T1	10		T11	6355
all_values[12]	auto[0]	auto[1]	auto[0]	656116	1			T25	68		T1	11		T11	731
all_values[12]	auto[0]	auto[1]	auto[1]	6134455	1			T25	812		T1	10		T11	5430
all_values[12]	auto[1]	auto[0]	auto[1]	91295	1			T1	1		T11	84		T2	21
all_values[12]	auto[1]	auto[1]	auto[1]	90673	1			T1	2		T11	111		T2	15
all_values[13]	auto[0]	auto[0]	auto[0]	2701094	1			T25	179		T26	49508		T1	18
all_values[13]	auto[0]	auto[0]	auto[1]	6156251	1			T25	964		T1	20		T11	5361
all_values[13]	auto[0]	auto[1]	auto[0]	664915	1			T25	77		T1	8		T11	727
all_values[13]	auto[0]	auto[1]	auto[1]	6112887	1			T25	747		T1	6		T11	6274
all_values[13]	auto[1]	auto[0]	auto[1]	91005	1			T1	1		T11	102		T2	8
all_values[13]	auto[1]	auto[1]	auto[1]	90800	1			T1	1		T11	109		T2	23
all_values[14]	auto[0]	auto[0]	auto[0]	2699728	1			T25	69		T26	49508		T1	25
all_values[14]	auto[0]	auto[0]	auto[1]	6165498	1			T25	792		T1	10		T11	5524
all_values[14]	auto[0]	auto[1]	auto[0]	664027	1			T25	121		T1	2		T11	647
all_values[14]	auto[0]	auto[1]	auto[1]	6105772	1			T25	985		T1	14		T11	6301
all_values[14]	auto[1]	auto[0]	auto[1]	91754	1			T1	2		T11	125		T2	17
all_values[14]	auto[1]	auto[1]	auto[1]	90173	1			T1	1		T11	109		T2	18
all_values[15]	auto[0]	auto[0]	auto[0]	2686587	1			T25	73		T26	49508		T1	21
all_values[15]	auto[0]	auto[0]	auto[1]	6160561	1			T25	922		T1	5		T11	6332
all_values[15]	auto[0]	auto[1]	auto[0]	658824	1			T25	45		T1	2		T11	625
all_values[15]	auto[0]	auto[1]	auto[1]	6129426	1			T25	927		T1	25		T11	5466
all_values[15]	auto[1]	auto[0]	auto[1]	90384	1			T11	103		T2	22		T13	3
all_values[15]	auto[1]	auto[1]	auto[1]	91170	1			T1	1		T11	100		T2	15
all_values[16]	auto[0]	auto[0]	auto[0]	2695053	1			T25	109		T26	49508		T1	17
all_values[16]	auto[0]	auto[0]	auto[1]	6091621	1			T25	858		T1	15		T11	5217
all_values[16]	auto[0]	auto[1]	auto[0]	666362	1			T25	92		T11	552		T2	34
all_values[16]	auto[0]	auto[1]	auto[1]	6182286	1			T25	908		T1	21		T11	6661
all_values[16]	auto[1]	auto[0]	auto[1]	90764	1			T1	1		T11	107		T2	19
all_values[16]	auto[1]	auto[1]	auto[1]	90866	1			T11	107		T2	17		T13	1
all_values[17]	auto[0]	auto[0]	auto[0]	2700018	1			T25	122		T26	49508		T1	15
all_values[17]	auto[0]	auto[0]	auto[1]	6151198	1			T25	849		T1	18		T11	6378
all_values[17]	auto[0]	auto[1]	auto[0]	664901	1			T25	41		T1	10		T11	678
all_values[17]	auto[0]	auto[1]	auto[1]	6119101	1			T25	955		T1	10		T11	5328
all_values[17]	auto[1]	auto[0]	auto[1]	91296	1			T1	1		T11	119		T2	20
all_values[17]	auto[1]	auto[1]	auto[1]	90438	1			T11	89		T2	11		T13	3
all_values[18]	auto[0]	auto[0]	auto[0]	2698268	1			T25	73		T26	49508		T1	22
all_values[18]	auto[0]	auto[0]	auto[1]	6121543	1			T25	838		T1	12		T11	5435
all_values[18]	auto[0]	auto[1]	auto[0]	665801	1			T25	108		T11	677		T2	55
all_values[18]	auto[0]	auto[1]	auto[1]	6149375	1			T25	948		T1	18		T11	6323
all_values[18]	auto[1]	auto[0]	auto[1]	90746	1			T11	101		T2	13		T13	3
all_values[18]	auto[1]	auto[1]	auto[1]	91219	1			T1	2		T11	103		T2	18
all_values[19]	auto[0]	auto[0]	auto[0]	2694506	1			T25	97		T26	49508		T1	13
all_values[19]	auto[0]	auto[0]	auto[1]	6144892	1			T25	826		T1	27		T11	5566
all_values[19]	auto[0]	auto[1]	auto[0]	665364	1			T25	117		T1	5		T11	720
all_values[19]	auto[0]	auto[1]	auto[1]	6130440	1			T25	927		T1	7		T11	6209
all_values[19]	auto[1]	auto[0]	auto[1]	90908	1			T1	2		T11	102		T2	15
all_values[19]	auto[1]	auto[1]	auto[1]	90842	1			T11	113		T2	13		T13	2
all_values[20]	auto[0]	auto[0]	auto[0]	2695595	1			T25	65		T26	49508		T1	17
all_values[20]	auto[0]	auto[0]	auto[1]	6135603	1			T25	889		T1	32		T11	5908
all_values[20]	auto[0]	auto[1]	auto[0]	657929	1			T25	73		T11	594		T2	7
all_values[20]	auto[0]	auto[1]	auto[1]	6146218	1			T25	940		T1	4		T11	5832
all_values[20]	auto[1]	auto[0]	auto[1]	90768	1			T1	1		T11	118		T2	28
all_values[20]	auto[1]	auto[1]	auto[1]	90839	1			T11	105		T2	11		T18	417
all_values[21]	auto[0]	auto[0]	auto[0]	2693300	1			T25	100		T26	49508		T1	24
all_values[21]	auto[0]	auto[0]	auto[1]	6124423	1			T25	1136		T1	15		T11	5527
all_values[21]	auto[0]	auto[1]	auto[0]	671678	1			T25	49		T1	2		T11	602
all_values[21]	auto[0]	auto[1]	auto[1]	6145725	1			T25	682		T1	10		T11	6327
all_values[21]	auto[1]	auto[0]	auto[1]	90764	1			T1	3		T11	102		T2	27
all_values[21]	auto[1]	auto[1]	auto[1]	91062	1			T11	101		T2	15		T13	3
all_values[22]	auto[0]	auto[0]	auto[0]	2699308	1			T25	78		T26	49508		T1	16
all_values[22]	auto[0]	auto[0]	auto[1]	6128516	1			T25	1043		T1	24		T11	5872
all_values[22]	auto[0]	auto[1]	auto[0]	667208	1			T25	133		T1	3		T11	535
all_values[22]	auto[0]	auto[1]	auto[1]	6140004	1			T25	713		T1	9		T11	5975
all_values[22]	auto[1]	auto[0]	auto[1]	91242	1			T1	1		T11	110		T2	14
all_values[22]	auto[1]	auto[1]	auto[1]	90674	1			T1	1		T11	121		T2	20
all_values[23]	auto[0]	auto[0]	auto[0]	2690984	1			T25	62		T26	49508		T1	36
all_values[23]	auto[0]	auto[0]	auto[1]	6155665	1			T25	881		T1	16		T11	5676
all_values[23]	auto[0]	auto[1]	auto[0]	671510	1			T25	74		T11	706		T2	13
all_values[23]	auto[0]	auto[1]	auto[1]	6116772	1			T25	950		T11	6108		T2	354
all_values[23]	auto[1]	auto[0]	auto[1]	91138	1			T1	2		T11	102		T2	25
all_values[23]	auto[1]	auto[1]	auto[1]	90883	1			T11	104		T2	14		T13	2
all_values[24]	auto[0]	auto[0]	auto[0]	2695864	1			T25	82		T26	49508		T1	23
all_values[24]	auto[0]	auto[0]	auto[1]	6181978	1			T25	822		T1	15		T11	5720
all_values[24]	auto[0]	auto[1]	auto[0]	660601	1			T25	99		T1	5		T11	688
all_values[24]	auto[0]	auto[1]	auto[1]	6096938	1			T25	964		T1	9		T11	5834
all_values[24]	auto[1]	auto[0]	auto[1]	90993	1			T1	1		T11	113		T2	20
all_values[24]	auto[1]	auto[1]	auto[1]	90578	1			T1	1		T11	91		T2	13
all_values[25]	auto[0]	auto[0]	auto[0]	2698827	1			T25	107		T26	49508		T1	19
all_values[25]	auto[0]	auto[0]	auto[1]	6165337	1			T25	895		T1	32		T11	6079
all_values[25]	auto[0]	auto[1]	auto[0]	660350	1			T25	99		T11	686		T2	60
all_values[25]	auto[0]	auto[1]	auto[1]	6110616	1			T25	866		T11	5610		T2	427
all_values[25]	auto[1]	auto[0]	auto[1]	91404	1			T1	3		T11	115		T2	12
all_values[25]	auto[1]	auto[1]	auto[1]	90418	1			T11	113		T2	24		T13	4
all_values[26]	auto[0]	auto[0]	auto[0]	2697348	1			T25	41		T26	49508		T1	17
all_values[26]	auto[0]	auto[0]	auto[1]	6138627	1			T25	718		T1	24		T11	6308
all_values[26]	auto[0]	auto[1]	auto[0]	660029	1			T25	52		T1	3		T11	604
all_values[26]	auto[0]	auto[1]	auto[1]	6139054	1			T25	1156		T1	8		T11	5566
all_values[26]	auto[1]	auto[0]	auto[1]	91575	1			T11	113		T2	11		T13	2
all_values[26]	auto[1]	auto[1]	auto[1]	90319	1			T1	2		T11	101		T2	26
all_values[27]	auto[0]	auto[0]	auto[0]	2696422	1			T25	101		T26	49508		T1	17
all_values[27]	auto[0]	auto[0]	auto[1]	6111571	1			T25	784		T1	5		T11	6418
all_values[27]	auto[0]	auto[1]	auto[0]	668849	1			T25	87		T1	14		T11	613
all_values[27]	auto[0]	auto[1]	auto[1]	6158214	1			T25	995		T1	17		T11	5346
all_values[27]	auto[1]	auto[0]	auto[1]	91016	1			T11	109		T2	11		T13	2
all_values[27]	auto[1]	auto[1]	auto[1]	90880	1			T1	1		T11	97		T2	14
all_values[28]	auto[0]	auto[0]	auto[0]	2698244	1			T25	31		T26	49508		T1	17
all_values[28]	auto[0]	auto[0]	auto[1]	6154781	1			T25	783		T1	18		T11	6079
all_values[28]	auto[0]	auto[1]	auto[0]	663175	1			T25	69		T1	1		T11	635
all_values[28]	auto[0]	auto[1]	auto[1]	6118783	1			T25	1084		T1	16		T11	5878
all_values[28]	auto[1]	auto[0]	auto[1]	91639	1			T1	2		T11	105		T2	19
all_values[28]	auto[1]	auto[1]	auto[1]	90330	1			T11	93		T2	20		T13	5
all_values[29]	auto[0]	auto[0]	auto[0]	2701163	1			T25	69		T26	49508		T1	22
all_values[29]	auto[0]	auto[0]	auto[1]	6157761	1			T25	771		T1	13		T11	6301
all_values[29]	auto[0]	auto[1]	auto[0]	658179	1			T25	57		T1	1		T11	614
all_values[29]	auto[0]	auto[1]	auto[1]	6118224	1			T25	1070		T1	16		T11	5559
all_values[29]	auto[1]	auto[0]	auto[1]	91206	1			T1	2		T11	123		T2	22
all_values[29]	auto[1]	auto[1]	auto[1]	90419	1			T11	98		T2	18		T13	2
all_values[30]	auto[0]	auto[0]	auto[0]	2688278	1			T25	119		T26	49508		T1	18
all_values[30]	auto[0]	auto[0]	auto[1]	6159769	1			T25	1005		T1	19		T11	6094
all_values[30]	auto[0]	auto[1]	auto[0]	664057	1			T25	108		T11	475		T2	41
all_values[30]	auto[0]	auto[1]	auto[1]	6123152	1			T25	735		T1	13		T11	5882
all_values[30]	auto[1]	auto[0]	auto[1]	91374	1			T1	2		T11	111		T2	11
all_values[30]	auto[1]	auto[1]	auto[1]	90322	1			T1	2		T11	86		T2	26
all_values[31]	auto[0]	auto[0]	auto[0]	2698916	1			T25	79		T26	49508		T1	31
all_values[31]	auto[0]	auto[0]	auto[1]	6184687	1			T25	1003		T1	14		T11	5343
all_values[31]	auto[0]	auto[1]	auto[0]	661285	1			T25	37		T1	9		T11	723
all_values[31]	auto[0]	auto[1]	auto[1]	6090645	1			T25	848		T11	6316		T2	461
all_values[31]	auto[1]	auto[0]	auto[1]	91079	1			T11	105		T2	10		T13	5
all_values[31]	auto[1]	auto[1]	auto[1]	90340	1			T11	112		T2	28		T13	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal