Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[1]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[2]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[3]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[4]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[5]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[6]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[7]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[8]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[9]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[10]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[11]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[12]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[13]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[14]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[15]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[16]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[17]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[18]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[19]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[20]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[21]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[22]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[23]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[24]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[25]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[26]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[27]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[28]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[29]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[30]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[31]	15621137	1			T25	1492		T26	49508		T1	47

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304560894

1

T25

23897

T26

780927

T1

827

auto[1]

195315490

1

T25

23847

T26

803329

T1

677

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

397458994

1

T25

47744

T26

158425

T1

1404

auto[1]

102417390

1

T1

100

T11

105891

T12

1719

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367555854

1

T25

47744

T26

158425

T1

1262

auto[1]

132320530

1

T1

242

T11

132593

T12

1716

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5806214	1			T25	745		T26	23993		T1	21
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4072797	1			T25	747		T26	25515		T1	10
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1608160	1			T1	6		T11	1632		T12	39
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2106512	1			T1	5		T11	163		T12	30
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	432330	1			T1	3		T11	2342		T2	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1595124	1			T1	2		T11	1678		T12	14
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5795655	1			T25	775		T26	24490		T1	15
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4072116	1			T25	717		T26	25018		T1	14
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1614159	1			T11	1675		T12	23		T2	247
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2106941	1			T1	5		T11	138		T12	34
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	433401	1			T1	5		T11	2256		T2	10
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1598865	1			T1	8		T11	1498		T12	26
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5800500	1			T25	715		T26	22928		T1	23
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4079661	1			T25	777		T26	26580		T1	18
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1614191	1			T11	1530		T12	22		T2	212
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2101002	1			T1	6		T11	149		T12	49
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	432598	1			T11	2439		T2	14		T13	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1593185	1			T11	1879		T12	30		T2	132
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5799881	1			T25	769		T26	24865		T1	13
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4072062	1			T25	723		T26	24643		T1	20
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1609805	1			T1	4		T11	1677		T12	29
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2109700	1			T1	5		T11	167		T12	28
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	437002	1			T1	2		T11	2408		T2	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1592687	1			T1	3		T11	1430		T12	16
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5800306	1			T25	775		T26	25106		T1	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4079269	1			T25	717		T26	24402		T1	17
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1610101	1			T11	1710		T12	18		T2	190
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2103591	1			T1	6		T11	116		T12	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	432823	1			T1	5		T11	2411		T2	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1595047	1			T1	5		T11	1566		T12	35
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5801365	1			T25	742		T26	26264		T1	13
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4075571	1			T25	750		T26	23244		T1	28
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1608504	1			T11	1580		T12	30		T2	175
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2107213	1			T1	1		T11	164		T12	25
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	432062	1			T1	3		T11	2560		T2	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1596422	1			T1	2		T11	1548		T12	46
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5808750	1			T25	721		T26	24871		T1	14
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4063833	1			T25	771		T26	24637		T1	17
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1607904	1			T11	1701		T12	35		T2	230
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2103990	1			T1	11		T11	133		T12	30
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	434218	1			T1	2		T11	2249		T2	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1602442	1			T1	3		T11	1490		T12	22
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5798649	1			T25	743		T26	24242		T1	24
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4078741	1			T25	749		T26	25266		T1	13
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1608276	1			T11	1751		T12	22		T2	157
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2106561	1			T1	5		T11	158		T12	36
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	433180	1			T1	3		T11	2254		T2	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1595730	1			T1	2		T11	1649		T12	15
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5790561	1			T25	750		T26	22685		T1	7
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4081731	1			T25	742		T26	26823		T1	30
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1612686	1			T11	1729		T12	23		T2	168
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2105869	1			T1	5		T11	159		T12	26
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	434752	1			T1	3		T11	2227		T2	7
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1595538	1			T1	2		T11	1692		T12	30
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5800103	1			T25	759		T26	25167		T1	15
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4071485	1			T25	733		T26	24341		T1	26
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1609877	1			T11	1858		T12	25		T2	174
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2105457	1			T1	1		T11	148		T12	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	432275	1			T1	3		T11	2319		T2	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1601940	1			T1	2		T11	1611		T12	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5790535	1			T25	765		T26	24228		T1	22
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4074839	1			T25	727		T26	25280		T1	17
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1608767	1			T1	2		T11	1644		T12	24
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2110987	1			T1	5		T11	142		T12	31
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	434429	1			T1	1		T11	2294		T2	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1601580	1			T11	1794		T12	32		T2	103
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5802038	1			T25	747		T26	25216		T1	32
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4073193	1			T25	745		T26	24292		T1	5
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1612190	1			T1	6		T11	1586		T12	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2104885	1			T1	4		T11	153		T12	34
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	433545	1			T11	2449		T2	1		T13	14
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1595286	1			T11	1658		T12	34		T2	199
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5798709	1			T25	761		T26	24918		T1	22
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4079959	1			T25	731		T26	24590		T1	16
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1605970	1			T1	3		T11	1635		T12	38
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2111571	1			T1	6		T11	173		T12	17
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	429419	1			T11	2314		T2	7		T13	18
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1595509	1			T11	1837		T12	30		T2	123
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5799995	1			T25	744		T26	23117		T1	12
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4078563	1			T25	748		T26	26391		T1	19
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1610926	1			T11	1590		T12	30		T2	168
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2102920	1			T1	11		T11	148		T12	29
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	430945	1			T1	3		T11	2457		T2	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1597788	1			T1	2		T11	1597		T12	30
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5793433	1			T25	756		T26	23856		T1	27
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4086232	1			T25	736		T26	25652		T1	8
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1607432	1			T1	2		T11	1611		T12	32
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2108558	1			T1	6		T11	126		T12	16
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	432913	1			T1	1		T11	2328		T2	13
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1592569	1			T1	3		T11	1605		T12	28
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5800245	1			T25	762		T26	25592		T1	24
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4080588	1			T25	730		T26	23916		T1	23
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1617379	1			T11	1629		T12	25		T2	172
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2100862	1			T11	137		T12	20		T2	180
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	430729	1			T11	2189		T2	8		T13	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1591334	1			T11	1330		T12	20		T2	188
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5813093	1			T25	747		T26	23560		T1	21
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4070018	1			T25	745		T26	25948		T1	14
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1605307	1			T1	6		T11	1580		T12	14
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2104896	1			T1	5		T11	144		T12	46
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	437377	1			T1	1		T11	2553		T2	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1590446	1			T11	1801		T12	22		T2	204
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5801834	1			T25	749		T26	26160		T1	21
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4079491	1			T25	743		T26	23348		T1	18
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1603555	1			T11	1795		T12	31		T2	202
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2109792	1			T1	1		T11	177		T12	26
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	432560	1			T1	3		T11	2184		T2	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1593905	1			T1	4		T11	1679		T12	34
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5811904	1			T25	729		T26	22937		T1	33
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4077056	1			T25	763		T26	26571		T1	11
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1604330	1			T1	2		T11	1597		T12	18
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2109064	1			T11	166		T12	28		T2	203
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	431737	1			T1	1		T11	2391		T2	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1587046	1			T11	1677		T12	43		T2	193
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5794815	1			T25	726		T26	23194		T1	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4078087	1			T25	766		T26	26314		T1	30
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1601450	1			T1	3		T11	1601		T12	20
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2119174	1			T11	203		T12	19		T2	196
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	433218	1			T1	1		T11	2509		T2	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1594393	1			T11	1697		T12	32		T2	104
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5792593	1			T25	751		T26	25362		T1	26
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4085695	1			T25	741		T26	24146		T1	2
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1603522	1			T1	3		T11	1541		T12	28
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2112990	1			T1	16		T11	193		T12	15
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	434553	1			T11	2553		T2	1		T13	20
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1591784	1			T11	1574		T12	40		T2	116
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5799765	1			T25	762		T26	24717		T1	18
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4086145	1			T25	730		T26	24791		T1	22
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1604649	1			T11	1857		T12	42		T2	159
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2105532	1			T1	1		T11	153		T12	24
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	432627	1			T1	4		T11	2303		T2	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1592419	1			T1	2		T11	1600		T12	19
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5802940	1			T25	741		T26	24222		T1	16
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4076451	1			T25	751		T26	25286		T1	21
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1602625	1			T11	1538		T12	34		T2	144
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2111851	1			T1	5		T11	161		T12	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	433729	1			T1	2		T11	2381		T2	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1593541	1			T1	3		T11	1679		T12	14
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5811583	1			T25	718		T26	24974		T1	9
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4070714	1			T25	774		T26	24534		T1	27
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1608716	1			T11	1627		T12	28		T2	126
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2109695	1			T1	5		T11	151		T12	31
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	433915	1			T1	4		T11	2315		T2	12
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1586514	1			T1	2		T11	1572		T12	24
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5808471	1			T25	747		T26	23805		T1	15
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4075473	1			T25	745		T26	25703		T1	22
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1603888	1			T11	1684		T12	26		T2	146
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2111831	1			T1	10		T11	130		T12	24
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	432558	1			T11	2313		T2	5		T13	22
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1588916	1			T11	1628		T12	27		T2	202
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5812652	1			T25	736		T26	25274		T1	21
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4065684	1			T25	756		T26	24234		T1	11
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1601634	1			T1	4		T11	1764		T12	22
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2114055	1			T1	11		T11	159		T12	41
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	434361	1			T11	2219		T2	16		T13	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1592751	1			T11	1522		T12	18		T2	129
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5793567	1			T25	747		T26	23543		T1	30
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4092281	1			T25	745		T26	25965		T1	16
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1606773	1			T11	1859		T12	18		T2	131
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2106153	1			T11	153		T12	21		T2	236
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	433756	1			T1	1		T11	2414		T2	11
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1588607	1			T11	1614		T12	10		T2	146
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5818465	1			T25	720		T26	26463		T1	34
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4070375	1			T25	772		T26	23045		T1	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1602325	1			T1	6		T11	1831		T12	41
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2110285	1			T1	1		T11	137		T12	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	431446	1			T1	1		T11	2237		T2	5
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1588241	1			T11	1569		T12	36		T2	197
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5800732	1			T25	757		T26	24771		T1	12
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4079263	1			T25	735		T26	24737		T1	34
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1600547	1			T11	1825		T12	24		T2	181
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2112890	1			T11	176		T12	20		T2	165
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	434060	1			T1	1		T11	2431		T2	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1593645	1			T11	1607		T12	24		T2	183
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5808554	1			T25	723		T26	23110		T1	22
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4072936	1			T25	769		T26	26398		T1	16
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1605961	1			T1	3		T11	1777		T12	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2110458	1			T1	5		T11	175		T12	30
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	432191	1			T1	1		T11	2346		T2	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1591037	1			T11	1648		T12	30		T2	220
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5798775	1			T25	783		T26	23342		T1	25
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4083612	1			T25	709		T26	26166		T1	22
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1600176	1			T11	1695		T12	24		T2	119
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2114297	1			T11	149		T12	28		T2	234
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	433022	1			T11	2341		T2	22		T13	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1591255	1			T11	1697		T12	24		T2	216
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5813931	1			T25	732		T26	23955		T1	15
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4076700	1			T25	760		T26	25553		T1	26
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1602835	1			T1	5		T11	1664		T12	30
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2106079	1			T1	1		T11	189		T12	32
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	434368	1			T11	2499		T2	15		T13	20
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1587224	1			T11	1692		T12	11		T2	207

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal