Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[1]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[2]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[3]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[4]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[5]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[6]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[7]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[8]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[9]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[10]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[11]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[12]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[13]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[14]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[15]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[16]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[17]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[18]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[19]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[20]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[21]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[22]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[23]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[24]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[25]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[26]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[27]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[28]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[29]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[30]	15621137	1			T25	1492		T26	49508		T1	47
bins_for_gpio_bits[31]	15621137	1			T25	1492		T26	49508		T1	47

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304560894

1

T25

23897

T26

780927

T1

827

auto[1]

195315490

1

T25

23847

T26

803329

T1

677

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304553826

1

T25

23897

T26

780927

T1

827

auto[1]

195322558

1

T25

23847

T26

803329

T1

677

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9235318	1			T25	745		T26	23993		T1	32
bins_for_gpio_bits[0]	auto[0]	auto[1]	285361	1			T11	302		T12	6		T2	21
bins_for_gpio_bits[0]	auto[1]	auto[0]	285568	1			T11	301		T12	6		T2	22
bins_for_gpio_bits[0]	auto[1]	auto[1]	5814890	1			T25	747		T26	25515		T1	15
bins_for_gpio_bits[1]	auto[0]	auto[0]	9230405	1			T25	775		T26	24490		T1	20
bins_for_gpio_bits[1]	auto[0]	auto[1]	286132	1			T11	308		T12	7		T2	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	286350	1			T11	307		T12	7		T2	22
bins_for_gpio_bits[1]	auto[1]	auto[1]	5818250	1			T25	717		T26	25018		T1	27
bins_for_gpio_bits[2]	auto[0]	auto[0]	9229915	1			T25	715		T26	22928		T1	29
bins_for_gpio_bits[2]	auto[0]	auto[1]	285548	1			T11	281		T12	9		T2	19
bins_for_gpio_bits[2]	auto[1]	auto[0]	285778	1			T11	281		T12	9		T2	19
bins_for_gpio_bits[2]	auto[1]	auto[1]	5819896	1			T25	777		T26	26580		T1	18
bins_for_gpio_bits[3]	auto[0]	auto[0]	9234114	1			T25	769		T26	24865		T1	22
bins_for_gpio_bits[3]	auto[0]	auto[1]	285035	1			T11	294		T12	7		T2	19
bins_for_gpio_bits[3]	auto[1]	auto[0]	285272	1			T11	293		T12	7		T2	19
bins_for_gpio_bits[3]	auto[1]	auto[1]	5816716	1			T25	723		T26	24643		T1	25
bins_for_gpio_bits[4]	auto[0]	auto[0]	9228133	1			T25	775		T26	25106		T1	20
bins_for_gpio_bits[4]	auto[0]	auto[1]	285622	1			T11	294		T12	6		T2	25
bins_for_gpio_bits[4]	auto[1]	auto[0]	285865	1			T11	292		T12	7		T2	25
bins_for_gpio_bits[4]	auto[1]	auto[1]	5821517	1			T25	717		T26	24402		T1	27
bins_for_gpio_bits[5]	auto[0]	auto[0]	9231815	1			T25	742		T26	26264		T1	14
bins_for_gpio_bits[5]	auto[0]	auto[1]	285053	1			T11	287		T12	10		T2	24
bins_for_gpio_bits[5]	auto[1]	auto[0]	285267	1			T11	285		T12	10		T2	24
bins_for_gpio_bits[5]	auto[1]	auto[1]	5819002	1			T25	750		T26	23244		T1	33
bins_for_gpio_bits[6]	auto[0]	auto[0]	9234292	1			T25	721		T26	24871		T1	25
bins_for_gpio_bits[6]	auto[0]	auto[1]	286108	1			T11	314		T12	5		T2	28
bins_for_gpio_bits[6]	auto[1]	auto[0]	286352	1			T11	313		T12	5		T2	28
bins_for_gpio_bits[6]	auto[1]	auto[1]	5814385	1			T25	771		T26	24637		T1	22
bins_for_gpio_bits[7]	auto[0]	auto[0]	9227900	1			T25	743		T26	24242		T1	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	285387	1			T11	301		T12	5		T2	22
bins_for_gpio_bits[7]	auto[1]	auto[0]	285586	1			T11	299		T12	6		T2	23
bins_for_gpio_bits[7]	auto[1]	auto[1]	5822264	1			T25	749		T26	25266		T1	18
bins_for_gpio_bits[8]	auto[0]	auto[0]	9223461	1			T25	750		T26	22685		T1	12
bins_for_gpio_bits[8]	auto[0]	auto[1]	285440	1			T11	300		T12	9		T2	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	285655	1			T11	298		T12	9		T2	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	5826581	1			T25	742		T26	26823		T1	35
bins_for_gpio_bits[9]	auto[0]	auto[0]	9230086	1			T25	759		T26	25167		T1	16
bins_for_gpio_bits[9]	auto[0]	auto[1]	285155	1			T11	289		T12	8		T2	22
bins_for_gpio_bits[9]	auto[1]	auto[0]	285351	1			T11	288		T12	8		T2	22
bins_for_gpio_bits[9]	auto[1]	auto[1]	5820545	1			T25	733		T26	24341		T1	31
bins_for_gpio_bits[10]	auto[0]	auto[0]	9224234	1			T25	765		T26	24228		T1	29
bins_for_gpio_bits[10]	auto[0]	auto[1]	285827	1			T11	284		T12	6		T2	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	286055	1			T11	282		T12	6		T2	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	5825021	1			T25	727		T26	25280		T1	18
bins_for_gpio_bits[11]	auto[0]	auto[0]	9233080	1			T25	747		T26	25216		T1	42
bins_for_gpio_bits[11]	auto[0]	auto[1]	285829	1			T11	297		T12	7		T2	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	286033	1			T11	294		T12	7		T2	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	5816195	1			T25	745		T26	24292		T1	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	9230076	1			T25	761		T26	24918		T1	31
bins_for_gpio_bits[12]	auto[0]	auto[1]	285958	1			T11	299		T12	5		T2	21
bins_for_gpio_bits[12]	auto[1]	auto[0]	286174	1			T11	294		T12	5		T2	21
bins_for_gpio_bits[12]	auto[1]	auto[1]	5818929	1			T25	731		T26	24590		T1	16
bins_for_gpio_bits[13]	auto[0]	auto[0]	9228178	1			T25	744		T26	23117		T1	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	285457	1			T11	290		T12	10		T2	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	285663	1			T11	290		T12	10		T2	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	5821839	1			T25	748		T26	26391		T1	24
bins_for_gpio_bits[14]	auto[0]	auto[0]	9223509	1			T25	756		T26	23856		T1	35
bins_for_gpio_bits[14]	auto[0]	auto[1]	285669	1			T11	303		T12	6		T2	24
bins_for_gpio_bits[14]	auto[1]	auto[0]	285914	1			T11	302		T12	6		T2	24
bins_for_gpio_bits[14]	auto[1]	auto[1]	5826045	1			T25	736		T26	25652		T1	12
bins_for_gpio_bits[15]	auto[0]	auto[0]	9232615	1			T25	762		T26	25592		T1	24
bins_for_gpio_bits[15]	auto[0]	auto[1]	285664	1			T11	276		T12	6		T2	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	285871	1			T11	275		T12	6		T2	23
bins_for_gpio_bits[15]	auto[1]	auto[1]	5816987	1			T25	730		T26	23916		T1	23
bins_for_gpio_bits[16]	auto[0]	auto[0]	9238025	1			T25	747		T26	23560		T1	32
bins_for_gpio_bits[16]	auto[0]	auto[1]	285079	1			T11	293		T12	7		T2	18
bins_for_gpio_bits[16]	auto[1]	auto[0]	285271	1			T11	291		T12	7		T2	19
bins_for_gpio_bits[16]	auto[1]	auto[1]	5812762	1			T25	745		T26	25948		T1	15
bins_for_gpio_bits[17]	auto[0]	auto[0]	9229604	1			T25	749		T26	26160		T1	22
bins_for_gpio_bits[17]	auto[0]	auto[1]	285376	1			T11	298		T12	8		T2	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	285577	1			T11	296		T12	8		T2	18
bins_for_gpio_bits[17]	auto[1]	auto[1]	5820580	1			T25	743		T26	23348		T1	25
bins_for_gpio_bits[18]	auto[0]	auto[0]	9239122	1			T25	729		T26	22937		T1	35
bins_for_gpio_bits[18]	auto[0]	auto[1]	285903	1			T11	298		T12	9		T2	25
bins_for_gpio_bits[18]	auto[1]	auto[0]	286176	1			T11	298		T12	10		T2	25
bins_for_gpio_bits[18]	auto[1]	auto[1]	5809936	1			T25	763		T26	26571		T1	12
bins_for_gpio_bits[19]	auto[0]	auto[0]	9229072	1			T25	726		T26	23194		T1	16
bins_for_gpio_bits[19]	auto[0]	auto[1]	286160	1			T11	296		T12	7		T2	19
bins_for_gpio_bits[19]	auto[1]	auto[0]	286367	1			T11	295		T12	7		T2	19
bins_for_gpio_bits[19]	auto[1]	auto[1]	5819538	1			T25	766		T26	26314		T1	31
bins_for_gpio_bits[20]	auto[0]	auto[0]	9223072	1			T25	751		T26	25362		T1	45
bins_for_gpio_bits[20]	auto[0]	auto[1]	285816	1			T11	282		T12	5		T2	22
bins_for_gpio_bits[20]	auto[1]	auto[0]	286033	1			T11	280		T12	5		T2	22
bins_for_gpio_bits[20]	auto[1]	auto[1]	5826216	1			T25	741		T26	24146		T1	2
bins_for_gpio_bits[21]	auto[0]	auto[0]	9224155	1			T25	762		T26	24717		T1	19
bins_for_gpio_bits[21]	auto[0]	auto[1]	285546	1			T11	296		T12	7		T2	21
bins_for_gpio_bits[21]	auto[1]	auto[0]	285791	1			T11	295		T12	8		T2	21
bins_for_gpio_bits[21]	auto[1]	auto[1]	5825645	1			T25	730		T26	24791		T1	28
bins_for_gpio_bits[22]	auto[0]	auto[0]	9231581	1			T25	741		T26	24222		T1	21
bins_for_gpio_bits[22]	auto[0]	auto[1]	285590	1			T11	279		T12	5		T2	24
bins_for_gpio_bits[22]	auto[1]	auto[0]	285835	1			T11	276		T12	5		T2	24
bins_for_gpio_bits[22]	auto[1]	auto[1]	5818131	1			T25	751		T26	25286		T1	26
bins_for_gpio_bits[23]	auto[0]	auto[0]	9244452	1			T25	718		T26	24974		T1	14
bins_for_gpio_bits[23]	auto[0]	auto[1]	285293	1			T11	297		T12	9		T2	23
bins_for_gpio_bits[23]	auto[1]	auto[0]	285542	1			T11	295		T12	9		T2	23
bins_for_gpio_bits[23]	auto[1]	auto[1]	5805850	1			T25	774		T26	24534		T1	33
bins_for_gpio_bits[24]	auto[0]	auto[0]	9238650	1			T25	747		T26	23805		T1	25
bins_for_gpio_bits[24]	auto[0]	auto[1]	285340	1			T11	298		T12	7		T2	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	285540	1			T11	297		T12	8		T2	26
bins_for_gpio_bits[24]	auto[1]	auto[1]	5811607	1			T25	745		T26	25703		T1	22
bins_for_gpio_bits[25]	auto[0]	auto[0]	9242714	1			T25	736		T26	25274		T1	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	285411	1			T11	297		T12	6		T2	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	285627	1			T11	294		T12	6		T2	21
bins_for_gpio_bits[25]	auto[1]	auto[1]	5807385	1			T25	756		T26	24234		T1	11
bins_for_gpio_bits[26]	auto[0]	auto[0]	9221163	1			T25	747		T26	23543		T1	30
bins_for_gpio_bits[26]	auto[0]	auto[1]	285112	1			T11	317		T12	2		T2	21
bins_for_gpio_bits[26]	auto[1]	auto[0]	285330	1			T11	315		T12	2		T2	21
bins_for_gpio_bits[26]	auto[1]	auto[1]	5829532	1			T25	745		T26	25965		T1	17
bins_for_gpio_bits[27]	auto[0]	auto[0]	9245879	1			T25	720		T26	26463		T1	41
bins_for_gpio_bits[27]	auto[0]	auto[1]	284974	1			T11	316		T12	5		T2	27
bins_for_gpio_bits[27]	auto[1]	auto[0]	285196	1			T11	313		T12	5		T2	27
bins_for_gpio_bits[27]	auto[1]	auto[1]	5805088	1			T25	772		T26	23045		T1	6
bins_for_gpio_bits[28]	auto[0]	auto[0]	9228576	1			T25	757		T26	24771		T1	12
bins_for_gpio_bits[28]	auto[0]	auto[1]	285387	1			T11	300		T12	4		T2	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	285593	1			T11	299		T12	4		T2	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	5821581	1			T25	735		T26	24737		T1	35
bins_for_gpio_bits[29]	auto[0]	auto[0]	9239091	1			T25	723		T26	23110		T1	30
bins_for_gpio_bits[29]	auto[0]	auto[1]	285673	1			T11	310		T12	8		T2	24
bins_for_gpio_bits[29]	auto[1]	auto[0]	285882	1			T11	309		T12	8		T2	24
bins_for_gpio_bits[29]	auto[1]	auto[1]	5810491	1			T25	769		T26	26398		T1	17
bins_for_gpio_bits[30]	auto[0]	auto[0]	9227140	1			T25	783		T26	23342		T1	25
bins_for_gpio_bits[30]	auto[0]	auto[1]	285884	1			T11	293		T12	7		T2	28
bins_for_gpio_bits[30]	auto[1]	auto[0]	286108	1			T11	293		T12	7		T2	28
bins_for_gpio_bits[30]	auto[1]	auto[1]	5822005	1			T25	709		T26	26166		T1	22
bins_for_gpio_bits[31]	auto[0]	auto[0]	9237031	1			T25	732		T26	23955		T1	21
bins_for_gpio_bits[31]	auto[0]	auto[1]	285579	1			T11	290		T12	4		T2	24
bins_for_gpio_bits[31]	auto[1]	auto[0]	285814	1			T11	289		T12	5		T2	24
bins_for_gpio_bits[31]	auto[1]	auto[1]	5812713	1			T25	760		T26	25553		T1	26