Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8943985 |
1 |
|
|
T25 |
803 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6872967 |
1 |
|
|
T25 |
1164 |
|
T11 |
6268 |
|
T2 |
388 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14939122 |
1 |
|
|
T25 |
1771 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
877830 |
1 |
|
|
T25 |
196 |
|
T1 |
1 |
|
T11 |
739 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8913128 |
1 |
|
|
T25 |
934 |
|
T26 |
49508 |
|
T1 |
35 |
| auto[1] |
6903824 |
1 |
|
|
T25 |
1033 |
|
T1 |
19 |
|
T11 |
6201 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3018322 |
1 |
|
|
T25 |
319 |
|
T1 |
18 |
|
T11 |
2900 |
| auto[1] |
auto[0] |
auto[1] |
439163 |
1 |
|
|
T25 |
73 |
|
T1 |
1 |
|
T11 |
373 |
| auto[1] |
auto[1] |
auto[0] |
3007672 |
1 |
|
|
T25 |
518 |
|
T11 |
2562 |
|
T2 |
188 |
| auto[1] |
auto[1] |
auto[1] |
438667 |
1 |
|
|
T25 |
123 |
|
T11 |
366 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8967124 |
1 |
|
|
T25 |
964 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6849828 |
1 |
|
|
T25 |
1003 |
|
T1 |
13 |
|
T11 |
6638 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14944361 |
1 |
|
|
T25 |
1811 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
872591 |
1 |
|
|
T25 |
156 |
|
T1 |
2 |
|
T11 |
698 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8938752 |
1 |
|
|
T25 |
1126 |
|
T26 |
49508 |
|
T1 |
11 |
| auto[1] |
6878200 |
1 |
|
|
T25 |
841 |
|
T1 |
43 |
|
T11 |
6242 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3019168 |
1 |
|
|
T25 |
345 |
|
T1 |
33 |
|
T11 |
2804 |
| auto[1] |
auto[0] |
auto[1] |
439284 |
1 |
|
|
T25 |
86 |
|
T1 |
1 |
|
T11 |
342 |
| auto[1] |
auto[1] |
auto[0] |
2986441 |
1 |
|
|
T25 |
340 |
|
T1 |
8 |
|
T11 |
2740 |
| auto[1] |
auto[1] |
auto[1] |
433307 |
1 |
|
|
T25 |
70 |
|
T1 |
1 |
|
T11 |
356 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910349 |
1 |
|
|
T25 |
826 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6906603 |
1 |
|
|
T25 |
1141 |
|
T1 |
13 |
|
T11 |
6826 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942625 |
1 |
|
|
T25 |
1771 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
874327 |
1 |
|
|
T25 |
196 |
|
T1 |
2 |
|
T11 |
824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8927262 |
1 |
|
|
T25 |
914 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6889690 |
1 |
|
|
T25 |
1053 |
|
T1 |
21 |
|
T11 |
6762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3002156 |
1 |
|
|
T25 |
411 |
|
T1 |
10 |
|
T11 |
3027 |
| auto[1] |
auto[0] |
auto[1] |
435588 |
1 |
|
|
T25 |
103 |
|
T1 |
2 |
|
T11 |
444 |
| auto[1] |
auto[1] |
auto[0] |
3013207 |
1 |
|
|
T25 |
446 |
|
T1 |
9 |
|
T11 |
2911 |
| auto[1] |
auto[1] |
auto[1] |
438739 |
1 |
|
|
T25 |
93 |
|
T11 |
380 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8915537 |
1 |
|
|
T25 |
1109 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6901415 |
1 |
|
|
T25 |
858 |
|
T1 |
20 |
|
T11 |
6351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14948446 |
1 |
|
|
T25 |
1820 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
868506 |
1 |
|
|
T25 |
147 |
|
T1 |
1 |
|
T11 |
815 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8969166 |
1 |
|
|
T25 |
1172 |
|
T26 |
49508 |
|
T1 |
7 |
| auto[1] |
6847786 |
1 |
|
|
T25 |
795 |
|
T1 |
47 |
|
T11 |
6855 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2991548 |
1 |
|
|
T25 |
299 |
|
T1 |
26 |
|
T11 |
3247 |
| auto[1] |
auto[0] |
auto[1] |
433759 |
1 |
|
|
T25 |
68 |
|
T1 |
1 |
|
T11 |
457 |
| auto[1] |
auto[1] |
auto[0] |
2987732 |
1 |
|
|
T25 |
349 |
|
T1 |
20 |
|
T11 |
2793 |
| auto[1] |
auto[1] |
auto[1] |
434747 |
1 |
|
|
T25 |
79 |
|
T11 |
358 |
|
T2 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8935708 |
1 |
|
|
T25 |
1087 |
|
T26 |
49508 |
|
T1 |
31 |
| auto[1] |
6881244 |
1 |
|
|
T25 |
880 |
|
T1 |
23 |
|
T11 |
6272 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14932663 |
1 |
|
|
T25 |
1745 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
884289 |
1 |
|
|
T25 |
222 |
|
T11 |
728 |
|
T2 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8879331 |
1 |
|
|
T25 |
774 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6937621 |
1 |
|
|
T25 |
1193 |
|
T1 |
17 |
|
T11 |
6476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3013744 |
1 |
|
|
T25 |
540 |
|
T1 |
9 |
|
T11 |
3007 |
| auto[1] |
auto[0] |
auto[1] |
439984 |
1 |
|
|
T25 |
131 |
|
T11 |
412 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[0] |
3039588 |
1 |
|
|
T25 |
431 |
|
T1 |
8 |
|
T11 |
2741 |
| auto[1] |
auto[1] |
auto[1] |
444305 |
1 |
|
|
T25 |
91 |
|
T11 |
316 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8948350 |
1 |
|
|
T25 |
1143 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6868602 |
1 |
|
|
T25 |
824 |
|
T1 |
15 |
|
T11 |
7110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14945807 |
1 |
|
|
T25 |
1756 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
871145 |
1 |
|
|
T25 |
211 |
|
T1 |
1 |
|
T11 |
813 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8955652 |
1 |
|
|
T25 |
833 |
|
T26 |
49508 |
|
T1 |
36 |
| auto[1] |
6861300 |
1 |
|
|
T25 |
1134 |
|
T1 |
18 |
|
T11 |
7117 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2998672 |
1 |
|
|
T25 |
558 |
|
T1 |
16 |
|
T11 |
2878 |
| auto[1] |
auto[0] |
auto[1] |
436740 |
1 |
|
|
T25 |
128 |
|
T1 |
1 |
|
T11 |
400 |
| auto[1] |
auto[1] |
auto[0] |
2991483 |
1 |
|
|
T25 |
365 |
|
T1 |
1 |
|
T11 |
3426 |
| auto[1] |
auto[1] |
auto[1] |
434405 |
1 |
|
|
T25 |
83 |
|
T11 |
413 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956980 |
1 |
|
|
T25 |
861 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6859972 |
1 |
|
|
T25 |
1106 |
|
T1 |
17 |
|
T11 |
7057 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942958 |
1 |
|
|
T25 |
1721 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
873994 |
1 |
|
|
T25 |
246 |
|
T1 |
1 |
|
T11 |
783 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928373 |
1 |
|
|
T25 |
675 |
|
T26 |
49508 |
|
T1 |
22 |
| auto[1] |
6888579 |
1 |
|
|
T25 |
1292 |
|
T1 |
32 |
|
T11 |
6736 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3008521 |
1 |
|
|
T25 |
524 |
|
T1 |
19 |
|
T11 |
2760 |
| auto[1] |
auto[0] |
auto[1] |
436638 |
1 |
|
|
T25 |
122 |
|
T1 |
1 |
|
T11 |
363 |
| auto[1] |
auto[1] |
auto[0] |
3006064 |
1 |
|
|
T25 |
522 |
|
T1 |
12 |
|
T11 |
3193 |
| auto[1] |
auto[1] |
auto[1] |
437356 |
1 |
|
|
T25 |
124 |
|
T11 |
420 |
|
T2 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8937532 |
1 |
|
|
T25 |
995 |
|
T26 |
49508 |
|
T1 |
26 |
| auto[1] |
6879420 |
1 |
|
|
T25 |
972 |
|
T1 |
28 |
|
T11 |
6191 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14941136 |
1 |
|
|
T25 |
1786 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
875816 |
1 |
|
|
T25 |
181 |
|
T1 |
2 |
|
T11 |
647 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8924798 |
1 |
|
|
T25 |
1027 |
|
T26 |
49508 |
|
T1 |
25 |
| auto[1] |
6892154 |
1 |
|
|
T25 |
940 |
|
T1 |
29 |
|
T11 |
6065 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3003965 |
1 |
|
|
T25 |
362 |
|
T1 |
8 |
|
T11 |
2841 |
| auto[1] |
auto[0] |
auto[1] |
437754 |
1 |
|
|
T25 |
86 |
|
T1 |
1 |
|
T11 |
316 |
| auto[1] |
auto[1] |
auto[0] |
3012373 |
1 |
|
|
T25 |
397 |
|
T1 |
19 |
|
T11 |
2577 |
| auto[1] |
auto[1] |
auto[1] |
438062 |
1 |
|
|
T25 |
95 |
|
T1 |
1 |
|
T11 |
331 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8877438 |
1 |
|
|
T25 |
967 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6939514 |
1 |
|
|
T25 |
1000 |
|
T1 |
21 |
|
T11 |
7320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14944023 |
1 |
|
|
T25 |
1780 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
872929 |
1 |
|
|
T25 |
187 |
|
T1 |
1 |
|
T11 |
807 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8945089 |
1 |
|
|
T25 |
954 |
|
T26 |
49508 |
|
T1 |
31 |
| auto[1] |
6871863 |
1 |
|
|
T25 |
1013 |
|
T1 |
23 |
|
T11 |
6436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2964828 |
1 |
|
|
T25 |
387 |
|
T1 |
10 |
|
T11 |
2582 |
| auto[1] |
auto[0] |
auto[1] |
429814 |
1 |
|
|
T25 |
88 |
|
T1 |
1 |
|
T11 |
332 |
| auto[1] |
auto[1] |
auto[0] |
3034106 |
1 |
|
|
T25 |
439 |
|
T1 |
12 |
|
T11 |
3047 |
| auto[1] |
auto[1] |
auto[1] |
443115 |
1 |
|
|
T25 |
99 |
|
T11 |
475 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942512 |
1 |
|
|
T25 |
971 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6874440 |
1 |
|
|
T25 |
996 |
|
T1 |
20 |
|
T11 |
6095 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942571 |
1 |
|
|
T25 |
1766 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
874381 |
1 |
|
|
T25 |
201 |
|
T1 |
2 |
|
T11 |
824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8932098 |
1 |
|
|
T25 |
891 |
|
T26 |
49508 |
|
T1 |
25 |
| auto[1] |
6884854 |
1 |
|
|
T25 |
1076 |
|
T1 |
29 |
|
T11 |
6798 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3009426 |
1 |
|
|
T25 |
422 |
|
T1 |
9 |
|
T11 |
3291 |
| auto[1] |
auto[0] |
auto[1] |
437022 |
1 |
|
|
T25 |
99 |
|
T1 |
1 |
|
T11 |
464 |
| auto[1] |
auto[1] |
auto[0] |
3001047 |
1 |
|
|
T25 |
453 |
|
T1 |
18 |
|
T11 |
2683 |
| auto[1] |
auto[1] |
auto[1] |
437359 |
1 |
|
|
T25 |
102 |
|
T1 |
1 |
|
T11 |
360 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910557 |
1 |
|
|
T25 |
911 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6906395 |
1 |
|
|
T25 |
1056 |
|
T1 |
20 |
|
T11 |
7103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14941716 |
1 |
|
|
T25 |
1780 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
875236 |
1 |
|
|
T25 |
187 |
|
T11 |
711 |
|
T2 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930926 |
1 |
|
|
T25 |
999 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6886026 |
1 |
|
|
T25 |
968 |
|
T1 |
17 |
|
T11 |
6323 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2986999 |
1 |
|
|
T25 |
308 |
|
T1 |
13 |
|
T11 |
2435 |
| auto[1] |
auto[0] |
auto[1] |
434104 |
1 |
|
|
T25 |
77 |
|
T11 |
273 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3023791 |
1 |
|
|
T25 |
473 |
|
T1 |
4 |
|
T11 |
3177 |
| auto[1] |
auto[1] |
auto[1] |
441132 |
1 |
|
|
T25 |
110 |
|
T11 |
438 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930306 |
1 |
|
|
T25 |
923 |
|
T26 |
49508 |
|
T1 |
42 |
| auto[1] |
6886646 |
1 |
|
|
T25 |
1044 |
|
T1 |
12 |
|
T11 |
7042 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14941428 |
1 |
|
|
T25 |
1817 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
875524 |
1 |
|
|
T25 |
150 |
|
T1 |
1 |
|
T11 |
748 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8925471 |
1 |
|
|
T25 |
1128 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6891481 |
1 |
|
|
T25 |
839 |
|
T1 |
21 |
|
T11 |
6730 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3002736 |
1 |
|
|
T25 |
244 |
|
T1 |
16 |
|
T11 |
2686 |
| auto[1] |
auto[0] |
auto[1] |
436428 |
1 |
|
|
T25 |
54 |
|
T1 |
1 |
|
T11 |
333 |
| auto[1] |
auto[1] |
auto[0] |
3013221 |
1 |
|
|
T25 |
445 |
|
T1 |
4 |
|
T11 |
3296 |
| auto[1] |
auto[1] |
auto[1] |
439096 |
1 |
|
|
T25 |
96 |
|
T11 |
415 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931267 |
1 |
|
|
T25 |
1056 |
|
T26 |
49508 |
|
T1 |
43 |
| auto[1] |
6885685 |
1 |
|
|
T25 |
911 |
|
T1 |
11 |
|
T11 |
7408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14937383 |
1 |
|
|
T25 |
1772 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
879569 |
1 |
|
|
T25 |
195 |
|
T11 |
731 |
|
T2 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8906624 |
1 |
|
|
T25 |
1021 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6910328 |
1 |
|
|
T25 |
946 |
|
T1 |
17 |
|
T11 |
6322 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3013443 |
1 |
|
|
T25 |
428 |
|
T1 |
13 |
|
T11 |
2660 |
| auto[1] |
auto[0] |
auto[1] |
438716 |
1 |
|
|
T25 |
109 |
|
T11 |
341 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
3017316 |
1 |
|
|
T25 |
323 |
|
T1 |
4 |
|
T11 |
2931 |
| auto[1] |
auto[1] |
auto[1] |
440853 |
1 |
|
|
T25 |
86 |
|
T11 |
390 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8921966 |
1 |
|
|
T25 |
954 |
|
T26 |
49508 |
|
T1 |
50 |
| auto[1] |
6894986 |
1 |
|
|
T25 |
1013 |
|
T1 |
4 |
|
T11 |
6531 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942152 |
1 |
|
|
T25 |
1780 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
874800 |
1 |
|
|
T25 |
187 |
|
T1 |
1 |
|
T11 |
705 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8939679 |
1 |
|
|
T25 |
993 |
|
T26 |
49508 |
|
T1 |
27 |
| auto[1] |
6877273 |
1 |
|
|
T25 |
974 |
|
T1 |
27 |
|
T11 |
6430 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3002044 |
1 |
|
|
T25 |
389 |
|
T1 |
22 |
|
T11 |
2705 |
| auto[1] |
auto[0] |
auto[1] |
438129 |
1 |
|
|
T25 |
89 |
|
T1 |
1 |
|
T11 |
330 |
| auto[1] |
auto[1] |
auto[0] |
3000429 |
1 |
|
|
T25 |
398 |
|
T1 |
4 |
|
T11 |
3020 |
| auto[1] |
auto[1] |
auto[1] |
436671 |
1 |
|
|
T25 |
98 |
|
T11 |
375 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908487 |
1 |
|
|
T25 |
1236 |
|
T26 |
49508 |
|
T1 |
42 |
| auto[1] |
6908465 |
1 |
|
|
T25 |
731 |
|
T1 |
12 |
|
T11 |
7030 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14947607 |
1 |
|
|
T25 |
1820 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
869345 |
1 |
|
|
T25 |
147 |
|
T11 |
965 |
|
T2 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8965336 |
1 |
|
|
T25 |
1132 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6851616 |
1 |
|
|
T25 |
835 |
|
T1 |
13 |
|
T11 |
7561 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2966630 |
1 |
|
|
T25 |
401 |
|
T1 |
13 |
|
T11 |
2985 |
| auto[1] |
auto[0] |
auto[1] |
429986 |
1 |
|
|
T25 |
90 |
|
T11 |
436 |
|
T2 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3015641 |
1 |
|
|
T25 |
287 |
|
T11 |
3611 |
|
T2 |
177 |
| auto[1] |
auto[1] |
auto[1] |
439359 |
1 |
|
|
T25 |
57 |
|
T11 |
529 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919066 |
1 |
|
|
T25 |
1121 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6897886 |
1 |
|
|
T25 |
846 |
|
T1 |
13 |
|
T11 |
6631 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14937557 |
1 |
|
|
T25 |
1779 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
879395 |
1 |
|
|
T25 |
188 |
|
T11 |
743 |
|
T2 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8896750 |
1 |
|
|
T25 |
1008 |
|
T26 |
49508 |
|
T1 |
28 |
| auto[1] |
6920202 |
1 |
|
|
T25 |
959 |
|
T1 |
26 |
|
T11 |
6547 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3027269 |
1 |
|
|
T25 |
438 |
|
T1 |
17 |
|
T11 |
2943 |
| auto[1] |
auto[0] |
auto[1] |
440253 |
1 |
|
|
T25 |
111 |
|
T11 |
364 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[0] |
3013538 |
1 |
|
|
T25 |
333 |
|
T1 |
9 |
|
T11 |
2861 |
| auto[1] |
auto[1] |
auto[1] |
439142 |
1 |
|
|
T25 |
77 |
|
T11 |
379 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8937787 |
1 |
|
|
T25 |
943 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6879165 |
1 |
|
|
T25 |
1024 |
|
T11 |
6918 |
|
T2 |
381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14941189 |
1 |
|
|
T25 |
1794 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
875763 |
1 |
|
|
T25 |
173 |
|
T11 |
876 |
|
T2 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8929681 |
1 |
|
|
T25 |
1043 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6887271 |
1 |
|
|
T25 |
924 |
|
T1 |
17 |
|
T11 |
6863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3002570 |
1 |
|
|
T25 |
384 |
|
T1 |
17 |
|
T11 |
2898 |
| auto[1] |
auto[0] |
auto[1] |
437321 |
1 |
|
|
T25 |
92 |
|
T11 |
446 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[0] |
3008938 |
1 |
|
|
T25 |
367 |
|
T11 |
3089 |
|
T2 |
219 |
| auto[1] |
auto[1] |
auto[1] |
438442 |
1 |
|
|
T25 |
81 |
|
T11 |
430 |
|
T2 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8968835 |
1 |
|
|
T25 |
904 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6848117 |
1 |
|
|
T25 |
1063 |
|
T1 |
15 |
|
T11 |
6613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14946746 |
1 |
|
|
T25 |
1789 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
870206 |
1 |
|
|
T25 |
178 |
|
T11 |
828 |
|
T2 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8946562 |
1 |
|
|
T25 |
1013 |
|
T26 |
49508 |
|
T1 |
46 |
| auto[1] |
6870390 |
1 |
|
|
T25 |
954 |
|
T1 |
8 |
|
T11 |
7006 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3022591 |
1 |
|
|
T25 |
372 |
|
T1 |
4 |
|
T11 |
2929 |
| auto[1] |
auto[0] |
auto[1] |
439466 |
1 |
|
|
T25 |
82 |
|
T11 |
353 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2977593 |
1 |
|
|
T25 |
404 |
|
T1 |
4 |
|
T11 |
3249 |
| auto[1] |
auto[1] |
auto[1] |
430740 |
1 |
|
|
T25 |
96 |
|
T11 |
475 |
|
T2 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8955568 |
1 |
|
|
T25 |
1002 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6861384 |
1 |
|
|
T25 |
965 |
|
T11 |
6409 |
|
T2 |
511 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14939790 |
1 |
|
|
T25 |
1770 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
877162 |
1 |
|
|
T25 |
197 |
|
T1 |
2 |
|
T11 |
941 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8916905 |
1 |
|
|
T25 |
917 |
|
T26 |
49508 |
|
T1 |
20 |
| auto[1] |
6900047 |
1 |
|
|
T25 |
1050 |
|
T1 |
34 |
|
T11 |
7421 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3035884 |
1 |
|
|
T25 |
437 |
|
T1 |
32 |
|
T11 |
3178 |
| auto[1] |
auto[0] |
auto[1] |
442471 |
1 |
|
|
T25 |
104 |
|
T1 |
2 |
|
T11 |
470 |
| auto[1] |
auto[1] |
auto[0] |
2987001 |
1 |
|
|
T25 |
416 |
|
T11 |
3302 |
|
T2 |
306 |
| auto[1] |
auto[1] |
auto[1] |
434691 |
1 |
|
|
T25 |
93 |
|
T11 |
471 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8927550 |
1 |
|
|
T25 |
759 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6889402 |
1 |
|
|
T25 |
1208 |
|
T1 |
13 |
|
T11 |
6271 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14945524 |
1 |
|
|
T25 |
1787 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
871428 |
1 |
|
|
T25 |
180 |
|
T1 |
2 |
|
T11 |
809 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8959194 |
1 |
|
|
T25 |
902 |
|
T26 |
49508 |
|
T1 |
21 |
| auto[1] |
6857758 |
1 |
|
|
T25 |
1065 |
|
T1 |
33 |
|
T11 |
6814 |