Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8936060 |
1 |
|
|
T25 |
1087 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6880892 |
1 |
|
|
T25 |
880 |
|
T1 |
20 |
|
T11 |
6924 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14940642 |
1 |
|
|
T25 |
1751 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
876310 |
1 |
|
|
T25 |
216 |
|
T11 |
750 |
|
T2 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8920873 |
1 |
|
|
T25 |
812 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6896079 |
1 |
|
|
T25 |
1155 |
|
T1 |
17 |
|
T11 |
6494 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3017273 |
1 |
|
|
T25 |
547 |
|
T1 |
13 |
|
T11 |
2897 |
| auto[1] |
auto[0] |
auto[1] |
439399 |
1 |
|
|
T25 |
126 |
|
T11 |
406 |
|
T2 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3002496 |
1 |
|
|
T25 |
392 |
|
T1 |
4 |
|
T11 |
2847 |
| auto[1] |
auto[1] |
auto[1] |
436911 |
1 |
|
|
T25 |
90 |
|
T11 |
344 |
|
T2 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |