Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933467 |
1 |
|
|
T25 |
1071 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6883485 |
1 |
|
|
T25 |
896 |
|
T11 |
6440 |
|
T2 |
328 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14935449 |
1 |
|
|
T25 |
1781 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
881503 |
1 |
|
|
T25 |
186 |
|
T1 |
1 |
|
T11 |
693 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8891831 |
1 |
|
|
T25 |
1045 |
|
T26 |
49508 |
|
T1 |
18 |
| auto[1] |
6925121 |
1 |
|
|
T25 |
922 |
|
T1 |
36 |
|
T11 |
6149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3024842 |
1 |
|
|
T25 |
358 |
|
T1 |
35 |
|
T11 |
2695 |
| auto[1] |
auto[0] |
auto[1] |
441487 |
1 |
|
|
T25 |
91 |
|
T1 |
1 |
|
T11 |
317 |
| auto[1] |
auto[1] |
auto[0] |
3018776 |
1 |
|
|
T25 |
378 |
|
T11 |
2761 |
|
T2 |
79 |
| auto[1] |
auto[1] |
auto[1] |
440016 |
1 |
|
|
T25 |
95 |
|
T11 |
376 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |