Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8903851 |
1 |
|
|
T25 |
1040 |
|
T26 |
49508 |
|
T1 |
46 |
| auto[1] |
6913101 |
1 |
|
|
T25 |
927 |
|
T1 |
8 |
|
T11 |
6386 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14939372 |
1 |
|
|
T25 |
1768 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
877580 |
1 |
|
|
T25 |
199 |
|
T11 |
938 |
|
T2 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8912147 |
1 |
|
|
T25 |
924 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6904805 |
1 |
|
|
T25 |
1043 |
|
T11 |
7306 |
|
T2 |
488 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3009004 |
1 |
|
|
T25 |
507 |
|
T11 |
3276 |
|
T2 |
321 |
| auto[1] |
auto[0] |
auto[1] |
438461 |
1 |
|
|
T25 |
123 |
|
T11 |
482 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[0] |
3018221 |
1 |
|
|
T25 |
337 |
|
T11 |
3092 |
|
T2 |
151 |
| auto[1] |
auto[1] |
auto[1] |
439119 |
1 |
|
|
T25 |
76 |
|
T11 |
456 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |