Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8942119 |
1 |
|
|
T25 |
981 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6874833 |
1 |
|
|
T25 |
986 |
|
T1 |
21 |
|
T11 |
6216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14943543 |
1 |
|
|
T25 |
1763 |
|
T26 |
49508 |
|
T1 |
52 |
| auto[1] |
873409 |
1 |
|
|
T25 |
204 |
|
T1 |
2 |
|
T11 |
716 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930231 |
1 |
|
|
T25 |
857 |
|
T26 |
49508 |
|
T1 |
7 |
| auto[1] |
6886721 |
1 |
|
|
T25 |
1110 |
|
T1 |
47 |
|
T11 |
6233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3013793 |
1 |
|
|
T25 |
406 |
|
T1 |
24 |
|
T11 |
3151 |
| auto[1] |
auto[0] |
auto[1] |
437524 |
1 |
|
|
T25 |
96 |
|
T1 |
2 |
|
T11 |
420 |
| auto[1] |
auto[1] |
auto[0] |
2999519 |
1 |
|
|
T25 |
500 |
|
T1 |
21 |
|
T11 |
2366 |
| auto[1] |
auto[1] |
auto[1] |
435885 |
1 |
|
|
T25 |
108 |
|
T11 |
296 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |