Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8976593 |
1 |
|
|
T25 |
1307 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6840359 |
1 |
|
|
T25 |
660 |
|
T1 |
20 |
|
T11 |
5763 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14946163 |
1 |
|
|
T25 |
1814 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
870789 |
1 |
|
|
T25 |
153 |
|
T11 |
796 |
|
T2 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8958423 |
1 |
|
|
T25 |
1141 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6858529 |
1 |
|
|
T25 |
826 |
|
T11 |
6828 |
|
T2 |
461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3009906 |
1 |
|
|
T25 |
376 |
|
T11 |
3342 |
|
T2 |
339 |
| auto[1] |
auto[0] |
auto[1] |
439383 |
1 |
|
|
T25 |
85 |
|
T11 |
486 |
|
T2 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2977834 |
1 |
|
|
T25 |
297 |
|
T11 |
2690 |
|
T2 |
103 |
| auto[1] |
auto[1] |
auto[1] |
431406 |
1 |
|
|
T25 |
68 |
|
T11 |
310 |
|
T2 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |