Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8943985 |
1 |
|
|
T25 |
803 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
6872967 |
1 |
|
|
T25 |
1164 |
|
T11 |
6268 |
|
T2 |
388 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13051201 |
1 |
|
|
T25 |
1528 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
2765751 |
1 |
|
|
T25 |
439 |
|
T11 |
4064 |
|
T2 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8929635 |
1 |
|
|
T25 |
984 |
|
T26 |
49508 |
|
T1 |
35 |
| auto[1] |
6887317 |
1 |
|
|
T25 |
983 |
|
T1 |
19 |
|
T11 |
6773 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2058570 |
1 |
|
|
T25 |
177 |
|
T1 |
19 |
|
T11 |
1355 |
| auto[1] |
auto[0] |
auto[1] |
1384348 |
1 |
|
|
T25 |
151 |
|
T11 |
2067 |
|
T2 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2062996 |
1 |
|
|
T25 |
367 |
|
T11 |
1354 |
|
T2 |
80 |
| auto[1] |
auto[1] |
auto[1] |
1381403 |
1 |
|
|
T25 |
288 |
|
T11 |
1997 |
|
T2 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |