Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8967124 |
1 |
|
|
T25 |
964 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6849828 |
1 |
|
|
T25 |
1003 |
|
T1 |
13 |
|
T11 |
6638 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13047893 |
1 |
|
|
T25 |
1537 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
2769059 |
1 |
|
|
T25 |
430 |
|
T11 |
4683 |
|
T2 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8928139 |
1 |
|
|
T25 |
1052 |
|
T26 |
49508 |
|
T1 |
44 |
| auto[1] |
6888813 |
1 |
|
|
T25 |
915 |
|
T1 |
10 |
|
T11 |
7431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2076489 |
1 |
|
|
T25 |
188 |
|
T1 |
9 |
|
T11 |
1371 |
| auto[1] |
auto[0] |
auto[1] |
1395684 |
1 |
|
|
T25 |
167 |
|
T11 |
2255 |
|
T2 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2043265 |
1 |
|
|
T25 |
297 |
|
T1 |
1 |
|
T11 |
1377 |
| auto[1] |
auto[1] |
auto[1] |
1373375 |
1 |
|
|
T25 |
263 |
|
T11 |
2428 |
|
T2 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |