Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910349 |
1 |
|
|
T25 |
826 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6906603 |
1 |
|
|
T25 |
1141 |
|
T1 |
13 |
|
T11 |
6826 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13044852 |
1 |
|
|
T25 |
1574 |
|
T26 |
49508 |
|
T1 |
42 |
| auto[1] |
2772100 |
1 |
|
|
T25 |
393 |
|
T1 |
12 |
|
T11 |
4031 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8940482 |
1 |
|
|
T25 |
1098 |
|
T26 |
49508 |
|
T1 |
40 |
| auto[1] |
6876470 |
1 |
|
|
T25 |
869 |
|
T1 |
14 |
|
T11 |
6457 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2049193 |
1 |
|
|
T25 |
221 |
|
T1 |
2 |
|
T11 |
1243 |
| auto[1] |
auto[0] |
auto[1] |
1384191 |
1 |
|
|
T25 |
175 |
|
T1 |
11 |
|
T11 |
1868 |
| auto[1] |
auto[1] |
auto[0] |
2055177 |
1 |
|
|
T25 |
255 |
|
T11 |
1183 |
|
T2 |
147 |
| auto[1] |
auto[1] |
auto[1] |
1387909 |
1 |
|
|
T25 |
218 |
|
T1 |
1 |
|
T11 |
2163 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |