Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8935708 |
1 |
|
|
T25 |
1087 |
|
T26 |
49508 |
|
T1 |
31 |
| auto[1] |
6881244 |
1 |
|
|
T25 |
880 |
|
T1 |
23 |
|
T11 |
6272 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13054045 |
1 |
|
|
T25 |
1579 |
|
T26 |
49508 |
|
T1 |
47 |
| auto[1] |
2762907 |
1 |
|
|
T25 |
388 |
|
T1 |
7 |
|
T11 |
3674 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8943448 |
1 |
|
|
T25 |
1139 |
|
T26 |
49508 |
|
T1 |
25 |
| auto[1] |
6873504 |
1 |
|
|
T25 |
828 |
|
T1 |
29 |
|
T11 |
5756 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2057908 |
1 |
|
|
T25 |
241 |
|
T1 |
8 |
|
T11 |
1003 |
| auto[1] |
auto[0] |
auto[1] |
1380012 |
1 |
|
|
T25 |
258 |
|
T1 |
4 |
|
T11 |
1911 |
| auto[1] |
auto[1] |
auto[0] |
2052689 |
1 |
|
|
T25 |
199 |
|
T1 |
14 |
|
T11 |
1079 |
| auto[1] |
auto[1] |
auto[1] |
1382895 |
1 |
|
|
T25 |
130 |
|
T1 |
3 |
|
T11 |
1763 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |