Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8948350 |
1 |
|
|
T25 |
1143 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6868602 |
1 |
|
|
T25 |
824 |
|
T1 |
15 |
|
T11 |
7110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13047441 |
1 |
|
|
T25 |
1585 |
|
T26 |
49508 |
|
T1 |
47 |
| auto[1] |
2769511 |
1 |
|
|
T25 |
382 |
|
T1 |
7 |
|
T11 |
3952 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8934074 |
1 |
|
|
T25 |
1162 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6882878 |
1 |
|
|
T25 |
805 |
|
T1 |
13 |
|
T11 |
6301 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2071111 |
1 |
|
|
T25 |
203 |
|
T1 |
4 |
|
T11 |
1220 |
| auto[1] |
auto[0] |
auto[1] |
1388921 |
1 |
|
|
T25 |
196 |
|
T1 |
4 |
|
T11 |
1981 |
| auto[1] |
auto[1] |
auto[0] |
2042256 |
1 |
|
|
T25 |
220 |
|
T1 |
2 |
|
T11 |
1129 |
| auto[1] |
auto[1] |
auto[1] |
1380590 |
1 |
|
|
T25 |
186 |
|
T1 |
3 |
|
T11 |
1971 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |