Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8956980 |
1 |
|
|
T25 |
861 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6859972 |
1 |
|
|
T25 |
1106 |
|
T1 |
17 |
|
T11 |
7057 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13043072 |
1 |
|
|
T25 |
1532 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
2773880 |
1 |
|
|
T25 |
435 |
|
T1 |
13 |
|
T11 |
3748 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8914064 |
1 |
|
|
T25 |
1061 |
|
T26 |
49508 |
|
T1 |
26 |
| auto[1] |
6902888 |
1 |
|
|
T25 |
906 |
|
T1 |
28 |
|
T11 |
5991 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2079903 |
1 |
|
|
T25 |
180 |
|
T1 |
11 |
|
T11 |
1074 |
| auto[1] |
auto[0] |
auto[1] |
1392310 |
1 |
|
|
T25 |
165 |
|
T1 |
1 |
|
T11 |
1884 |
| auto[1] |
auto[1] |
auto[0] |
2049105 |
1 |
|
|
T25 |
291 |
|
T1 |
4 |
|
T11 |
1169 |
| auto[1] |
auto[1] |
auto[1] |
1381570 |
1 |
|
|
T25 |
270 |
|
T1 |
12 |
|
T11 |
1864 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |