Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8937532 |
1 |
|
|
T25 |
995 |
|
T26 |
49508 |
|
T1 |
26 |
| auto[1] |
6879420 |
1 |
|
|
T25 |
972 |
|
T1 |
28 |
|
T11 |
6191 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13037915 |
1 |
|
|
T25 |
1545 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
2779037 |
1 |
|
|
T25 |
422 |
|
T1 |
13 |
|
T11 |
4186 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8894220 |
1 |
|
|
T25 |
1063 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6922732 |
1 |
|
|
T25 |
904 |
|
T1 |
20 |
|
T11 |
6863 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2074306 |
1 |
|
|
T25 |
236 |
|
T11 |
1404 |
|
T2 |
170 |
| auto[1] |
auto[0] |
auto[1] |
1399295 |
1 |
|
|
T25 |
240 |
|
T11 |
2508 |
|
T2 |
45 |
| auto[1] |
auto[1] |
auto[0] |
2069389 |
1 |
|
|
T25 |
246 |
|
T1 |
7 |
|
T11 |
1273 |
| auto[1] |
auto[1] |
auto[1] |
1379742 |
1 |
|
|
T25 |
182 |
|
T1 |
13 |
|
T11 |
1678 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |