Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8877438 |
1 |
|
|
T25 |
967 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6939514 |
1 |
|
|
T25 |
1000 |
|
T1 |
21 |
|
T11 |
7320 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13047716 |
1 |
|
|
T25 |
1632 |
|
T26 |
49508 |
|
T1 |
46 |
| auto[1] |
2769236 |
1 |
|
|
T25 |
335 |
|
T1 |
8 |
|
T11 |
4655 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8951463 |
1 |
|
|
T25 |
1253 |
|
T26 |
49508 |
|
T1 |
28 |
| auto[1] |
6865489 |
1 |
|
|
T25 |
714 |
|
T1 |
26 |
|
T11 |
7420 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2040066 |
1 |
|
|
T25 |
226 |
|
T1 |
4 |
|
T11 |
1144 |
| auto[1] |
auto[0] |
auto[1] |
1377158 |
1 |
|
|
T25 |
157 |
|
T1 |
8 |
|
T11 |
1947 |
| auto[1] |
auto[1] |
auto[0] |
2056187 |
1 |
|
|
T25 |
153 |
|
T1 |
14 |
|
T11 |
1621 |
| auto[1] |
auto[1] |
auto[1] |
1392078 |
1 |
|
|
T25 |
178 |
|
T11 |
2708 |
|
T2 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |