Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8910557 |
1 |
|
|
T25 |
911 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6906395 |
1 |
|
|
T25 |
1056 |
|
T1 |
20 |
|
T11 |
7103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13038143 |
1 |
|
|
T25 |
1554 |
|
T26 |
49508 |
|
T1 |
50 |
| auto[1] |
2778809 |
1 |
|
|
T25 |
413 |
|
T1 |
4 |
|
T11 |
4103 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8923064 |
1 |
|
|
T25 |
1143 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6893888 |
1 |
|
|
T25 |
824 |
|
T1 |
17 |
|
T11 |
6559 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2047704 |
1 |
|
|
T25 |
170 |
|
T11 |
1177 |
|
T2 |
142 |
| auto[1] |
auto[0] |
auto[1] |
1387247 |
1 |
|
|
T25 |
161 |
|
T11 |
2040 |
|
T2 |
36 |
| auto[1] |
auto[1] |
auto[0] |
2067375 |
1 |
|
|
T25 |
241 |
|
T1 |
13 |
|
T11 |
1279 |
| auto[1] |
auto[1] |
auto[1] |
1391562 |
1 |
|
|
T25 |
252 |
|
T1 |
4 |
|
T11 |
2063 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |