Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930306 |
1 |
|
|
T25 |
923 |
|
T26 |
49508 |
|
T1 |
42 |
| auto[1] |
6886646 |
1 |
|
|
T25 |
1044 |
|
T1 |
12 |
|
T11 |
7042 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13047076 |
1 |
|
|
T25 |
1456 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
2769876 |
1 |
|
|
T25 |
511 |
|
T1 |
13 |
|
T11 |
4707 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8938026 |
1 |
|
|
T25 |
989 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6878926 |
1 |
|
|
T25 |
978 |
|
T1 |
20 |
|
T11 |
7480 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2055493 |
1 |
|
|
T25 |
265 |
|
T1 |
3 |
|
T11 |
1308 |
| auto[1] |
auto[0] |
auto[1] |
1388582 |
1 |
|
|
T25 |
277 |
|
T1 |
13 |
|
T11 |
2139 |
| auto[1] |
auto[1] |
auto[0] |
2053557 |
1 |
|
|
T25 |
202 |
|
T1 |
4 |
|
T11 |
1465 |
| auto[1] |
auto[1] |
auto[1] |
1381294 |
1 |
|
|
T25 |
234 |
|
T11 |
2568 |
|
T2 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |