Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8931267 |
1 |
|
|
T25 |
1056 |
|
T26 |
49508 |
|
T1 |
43 |
| auto[1] |
6885685 |
1 |
|
|
T25 |
911 |
|
T1 |
11 |
|
T11 |
7408 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13047962 |
1 |
|
|
T25 |
1542 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
2768990 |
1 |
|
|
T25 |
425 |
|
T11 |
4260 |
|
T2 |
77 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8920689 |
1 |
|
|
T25 |
1187 |
|
T26 |
49508 |
|
T1 |
49 |
| auto[1] |
6896263 |
1 |
|
|
T25 |
780 |
|
T1 |
5 |
|
T11 |
6748 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2067844 |
1 |
|
|
T25 |
195 |
|
T1 |
5 |
|
T11 |
1002 |
| auto[1] |
auto[0] |
auto[1] |
1390935 |
1 |
|
|
T25 |
242 |
|
T11 |
1791 |
|
T2 |
53 |
| auto[1] |
auto[1] |
auto[0] |
2059429 |
1 |
|
|
T25 |
160 |
|
T11 |
1486 |
|
T2 |
200 |
| auto[1] |
auto[1] |
auto[1] |
1378055 |
1 |
|
|
T25 |
183 |
|
T11 |
2469 |
|
T2 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |