Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8908487 |
1 |
|
|
T25 |
1236 |
|
T26 |
49508 |
|
T1 |
42 |
| auto[1] |
6908465 |
1 |
|
|
T25 |
731 |
|
T1 |
12 |
|
T11 |
7030 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13046136 |
1 |
|
|
T25 |
1422 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
2770816 |
1 |
|
|
T25 |
545 |
|
T11 |
4077 |
|
T2 |
100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8927062 |
1 |
|
|
T25 |
817 |
|
T26 |
49508 |
|
T1 |
49 |
| auto[1] |
6889890 |
1 |
|
|
T25 |
1150 |
|
T1 |
5 |
|
T11 |
6762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2048897 |
1 |
|
|
T25 |
411 |
|
T1 |
5 |
|
T11 |
1308 |
| auto[1] |
auto[0] |
auto[1] |
1380078 |
1 |
|
|
T25 |
343 |
|
T11 |
1954 |
|
T2 |
62 |
| auto[1] |
auto[1] |
auto[0] |
2070177 |
1 |
|
|
T25 |
194 |
|
T11 |
1377 |
|
T2 |
114 |
| auto[1] |
auto[1] |
auto[1] |
1390738 |
1 |
|
|
T25 |
202 |
|
T11 |
2123 |
|
T2 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |