Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8899009 |
1 |
|
|
T25 |
885 |
|
T26 |
49508 |
|
T1 |
22 |
| auto[1] |
6917943 |
1 |
|
|
T25 |
1082 |
|
T1 |
32 |
|
T11 |
6056 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942982 |
1 |
|
|
T25 |
1786 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
873970 |
1 |
|
|
T25 |
181 |
|
T1 |
1 |
|
T11 |
839 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8937384 |
1 |
|
|
T25 |
979 |
|
T26 |
49508 |
|
T1 |
25 |
| auto[1] |
6879568 |
1 |
|
|
T25 |
988 |
|
T1 |
29 |
|
T11 |
6876 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3007933 |
1 |
|
|
T25 |
339 |
|
T1 |
8 |
|
T11 |
3361 |
| auto[1] |
auto[0] |
auto[1] |
437049 |
1 |
|
|
T25 |
69 |
|
T1 |
1 |
|
T11 |
485 |
| auto[1] |
auto[1] |
auto[0] |
2997665 |
1 |
|
|
T25 |
468 |
|
T1 |
20 |
|
T11 |
2676 |
| auto[1] |
auto[1] |
auto[1] |
436921 |
1 |
|
|
T25 |
112 |
|
T11 |
354 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |