Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8919066 |
1 |
|
|
T25 |
1121 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6897886 |
1 |
|
|
T25 |
846 |
|
T1 |
13 |
|
T11 |
6631 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13048420 |
1 |
|
|
T25 |
1617 |
|
T26 |
49508 |
|
T1 |
47 |
| auto[1] |
2768532 |
1 |
|
|
T25 |
350 |
|
T1 |
7 |
|
T11 |
4003 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8937251 |
1 |
|
|
T25 |
1234 |
|
T26 |
49508 |
|
T1 |
34 |
| auto[1] |
6879701 |
1 |
|
|
T25 |
733 |
|
T1 |
20 |
|
T11 |
6383 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2058147 |
1 |
|
|
T25 |
177 |
|
T1 |
9 |
|
T11 |
1147 |
| auto[1] |
auto[0] |
auto[1] |
1384891 |
1 |
|
|
T25 |
166 |
|
T1 |
2 |
|
T11 |
2073 |
| auto[1] |
auto[1] |
auto[0] |
2053022 |
1 |
|
|
T25 |
206 |
|
T1 |
4 |
|
T11 |
1233 |
| auto[1] |
auto[1] |
auto[1] |
1383641 |
1 |
|
|
T25 |
184 |
|
T1 |
5 |
|
T11 |
1930 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |