Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8968835 |
1 |
|
|
T25 |
904 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6848117 |
1 |
|
|
T25 |
1063 |
|
T1 |
15 |
|
T11 |
6613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13046877 |
1 |
|
|
T25 |
1397 |
|
T26 |
49508 |
|
T1 |
50 |
| auto[1] |
2770075 |
1 |
|
|
T25 |
570 |
|
T1 |
4 |
|
T11 |
4081 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8930275 |
1 |
|
|
T25 |
835 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6886677 |
1 |
|
|
T25 |
1132 |
|
T1 |
15 |
|
T11 |
6510 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2062157 |
1 |
|
|
T25 |
269 |
|
T1 |
11 |
|
T11 |
1233 |
| auto[1] |
auto[0] |
auto[1] |
1391641 |
1 |
|
|
T25 |
237 |
|
T11 |
2055 |
|
T2 |
53 |
| auto[1] |
auto[1] |
auto[0] |
2054445 |
1 |
|
|
T25 |
293 |
|
T11 |
1196 |
|
T2 |
158 |
| auto[1] |
auto[1] |
auto[1] |
1378434 |
1 |
|
|
T25 |
333 |
|
T1 |
4 |
|
T11 |
2026 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |