Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8944664 |
1 |
|
|
T25 |
814 |
|
T26 |
49508 |
|
T1 |
37 |
| auto[1] |
6872288 |
1 |
|
|
T25 |
1153 |
|
T1 |
17 |
|
T11 |
6606 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14946922 |
1 |
|
|
T25 |
1815 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
870030 |
1 |
|
|
T25 |
152 |
|
T1 |
1 |
|
T11 |
801 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8963971 |
1 |
|
|
T25 |
1168 |
|
T26 |
49508 |
|
T1 |
32 |
| auto[1] |
6852981 |
1 |
|
|
T25 |
799 |
|
T1 |
22 |
|
T11 |
6842 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3008034 |
1 |
|
|
T25 |
293 |
|
T1 |
13 |
|
T11 |
2755 |
| auto[1] |
auto[0] |
auto[1] |
437094 |
1 |
|
|
T25 |
66 |
|
T1 |
1 |
|
T11 |
353 |
| auto[1] |
auto[1] |
auto[0] |
2974917 |
1 |
|
|
T25 |
354 |
|
T1 |
8 |
|
T11 |
3286 |
| auto[1] |
auto[1] |
auto[1] |
432936 |
1 |
|
|
T25 |
86 |
|
T11 |
448 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |