Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8929044 |
1 |
|
|
T25 |
954 |
|
T26 |
49508 |
|
T1 |
41 |
| auto[1] |
6887908 |
1 |
|
|
T25 |
1013 |
|
T1 |
13 |
|
T11 |
6822 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14942981 |
1 |
|
|
T25 |
1787 |
|
T26 |
49508 |
|
T1 |
54 |
| auto[1] |
873971 |
1 |
|
|
T25 |
180 |
|
T11 |
778 |
|
T2 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8933236 |
1 |
|
|
T25 |
1033 |
|
T26 |
49508 |
|
T1 |
33 |
| auto[1] |
6883716 |
1 |
|
|
T25 |
934 |
|
T1 |
21 |
|
T11 |
6715 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3004717 |
1 |
|
|
T25 |
402 |
|
T1 |
17 |
|
T11 |
3182 |
| auto[1] |
auto[0] |
auto[1] |
436568 |
1 |
|
|
T25 |
94 |
|
T11 |
450 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3005028 |
1 |
|
|
T25 |
352 |
|
T1 |
4 |
|
T11 |
2755 |
| auto[1] |
auto[1] |
auto[1] |
437403 |
1 |
|
|
T25 |
86 |
|
T11 |
328 |
|
T2 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |