Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8939421 |
1 |
|
|
T25 |
1124 |
|
T26 |
49508 |
|
T1 |
39 |
| auto[1] |
6877531 |
1 |
|
|
T25 |
843 |
|
T1 |
15 |
|
T11 |
6443 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14936106 |
1 |
|
|
T25 |
1860 |
|
T26 |
49508 |
|
T1 |
53 |
| auto[1] |
880846 |
1 |
|
|
T25 |
107 |
|
T1 |
1 |
|
T11 |
800 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8895203 |
1 |
|
|
T25 |
1357 |
|
T26 |
49508 |
|
T1 |
23 |
| auto[1] |
6921749 |
1 |
|
|
T25 |
610 |
|
T1 |
31 |
|
T11 |
6541 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3029733 |
1 |
|
|
T25 |
219 |
|
T1 |
22 |
|
T11 |
2872 |
| auto[1] |
auto[0] |
auto[1] |
440670 |
1 |
|
|
T25 |
49 |
|
T1 |
1 |
|
T11 |
392 |
| auto[1] |
auto[1] |
auto[0] |
3011170 |
1 |
|
|
T25 |
284 |
|
T1 |
8 |
|
T11 |
2869 |
| auto[1] |
auto[1] |
auto[1] |
440176 |
1 |
|
|
T25 |
58 |
|
T11 |
408 |
|
T2 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |