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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T763 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1027875636 Apr 04 02:47:33 PM PDT 24 Apr 04 02:47:34 PM PDT 24 52467235 ps
T764 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4182528318 Apr 04 02:47:18 PM PDT 24 Apr 04 02:47:19 PM PDT 24 162998496 ps
T765 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3077226101 Apr 04 02:47:27 PM PDT 24 Apr 04 02:47:28 PM PDT 24 15964770 ps
T41 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1464757860 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 162965808 ps
T88 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2568011113 Apr 04 02:47:13 PM PDT 24 Apr 04 02:47:14 PM PDT 24 21922360 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3323197637 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 50305178 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3123044319 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 126119656 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2331145030 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:04 PM PDT 24 164080914 ps
T769 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1462753913 Apr 04 02:47:25 PM PDT 24 Apr 04 02:47:26 PM PDT 24 63315042 ps
T770 /workspace/coverage/cover_reg_top/46.gpio_intr_test.678108850 Apr 04 02:47:26 PM PDT 24 Apr 04 02:47:26 PM PDT 24 43336208 ps
T771 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3703886370 Apr 04 02:47:20 PM PDT 24 Apr 04 02:47:22 PM PDT 24 78092684 ps
T772 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1512551620 Apr 04 02:47:37 PM PDT 24 Apr 04 02:47:37 PM PDT 24 11837227 ps
T773 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3633657350 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 51160445 ps
T774 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.94638710 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 59966346 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.381133910 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:19 PM PDT 24 41812905 ps
T776 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1085677839 Apr 04 02:47:27 PM PDT 24 Apr 04 02:47:28 PM PDT 24 36159600 ps
T116 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4082531471 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:19 PM PDT 24 311131990 ps
T777 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1128112478 Apr 04 02:47:04 PM PDT 24 Apr 04 02:47:06 PM PDT 24 48624935 ps
T778 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1149700976 Apr 04 02:47:20 PM PDT 24 Apr 04 02:47:21 PM PDT 24 102531170 ps
T779 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3307407795 Apr 04 02:47:28 PM PDT 24 Apr 04 02:47:30 PM PDT 24 14563832 ps
T780 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2488102854 Apr 04 02:47:19 PM PDT 24 Apr 04 02:47:21 PM PDT 24 201828097 ps
T781 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2682680899 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:08 PM PDT 24 144665617 ps
T782 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.692132566 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:06 PM PDT 24 452436778 ps
T89 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1884850004 Apr 04 02:47:14 PM PDT 24 Apr 04 02:47:15 PM PDT 24 35120108 ps
T90 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3029270913 Apr 04 02:47:19 PM PDT 24 Apr 04 02:47:19 PM PDT 24 38781392 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2273182893 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:07 PM PDT 24 35176563 ps
T784 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1926005582 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:18 PM PDT 24 99838317 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1733924063 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:05 PM PDT 24 132995657 ps
T91 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3579037338 Apr 04 02:47:06 PM PDT 24 Apr 04 02:47:07 PM PDT 24 13398429 ps
T786 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2145443559 Apr 04 02:47:26 PM PDT 24 Apr 04 02:47:28 PM PDT 24 28695845 ps
T787 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2350741500 Apr 04 02:47:25 PM PDT 24 Apr 04 02:47:26 PM PDT 24 55727199 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1818371178 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 35304771 ps
T789 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4150534349 Apr 04 02:47:28 PM PDT 24 Apr 04 02:47:30 PM PDT 24 50291136 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3024594837 Apr 04 02:47:27 PM PDT 24 Apr 04 02:47:29 PM PDT 24 33416851 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4233842395 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:18 PM PDT 24 94140180 ps
T115 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2891530271 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 95522066 ps
T792 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.176456062 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:04 PM PDT 24 51486090 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.188098202 Apr 04 02:47:14 PM PDT 24 Apr 04 02:47:17 PM PDT 24 391013626 ps
T794 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1619564976 Apr 04 02:47:25 PM PDT 24 Apr 04 02:47:26 PM PDT 24 36397027 ps
T42 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2511570057 Apr 04 02:47:20 PM PDT 24 Apr 04 02:47:21 PM PDT 24 422377362 ps
T795 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.984466172 Apr 04 02:47:19 PM PDT 24 Apr 04 02:47:20 PM PDT 24 14621575 ps
T796 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2310356257 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 12838607 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.832296214 Apr 04 02:47:06 PM PDT 24 Apr 04 02:47:07 PM PDT 24 140622864 ps
T798 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1351440397 Apr 04 02:47:06 PM PDT 24 Apr 04 02:47:09 PM PDT 24 309198591 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1461653016 Apr 04 02:47:08 PM PDT 24 Apr 04 02:47:09 PM PDT 24 12097603 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1443792458 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:04 PM PDT 24 78507091 ps
T800 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2059965093 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 18301929 ps
T801 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1380722047 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:17 PM PDT 24 71209592 ps
T802 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1367983317 Apr 04 02:47:15 PM PDT 24 Apr 04 02:47:17 PM PDT 24 11278075 ps
T803 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3881682053 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 40291642 ps
T804 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2010104471 Apr 04 02:47:34 PM PDT 24 Apr 04 02:47:35 PM PDT 24 23035326 ps
T805 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1140380678 Apr 04 02:47:04 PM PDT 24 Apr 04 02:47:05 PM PDT 24 22046479 ps
T806 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.895427279 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 13913307 ps
T93 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.478132464 Apr 04 02:47:03 PM PDT 24 Apr 04 02:47:04 PM PDT 24 116469044 ps
T95 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1639674268 Apr 04 02:47:19 PM PDT 24 Apr 04 02:47:20 PM PDT 24 18262079 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3451631355 Apr 04 02:47:14 PM PDT 24 Apr 04 02:47:15 PM PDT 24 57174893 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1589255676 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 31426081 ps
T809 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2678110104 Apr 04 02:47:34 PM PDT 24 Apr 04 02:47:35 PM PDT 24 44049090 ps
T810 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.834120311 Apr 04 02:47:21 PM PDT 24 Apr 04 02:47:24 PM PDT 24 474118951 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1135742216 Apr 04 02:47:18 PM PDT 24 Apr 04 02:47:19 PM PDT 24 17910560 ps
T812 /workspace/coverage/cover_reg_top/41.gpio_intr_test.717934844 Apr 04 02:47:25 PM PDT 24 Apr 04 02:47:26 PM PDT 24 22647889 ps
T813 /workspace/coverage/cover_reg_top/36.gpio_intr_test.295481952 Apr 04 02:47:30 PM PDT 24 Apr 04 02:47:32 PM PDT 24 16050631 ps
T814 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2588069419 Apr 04 02:47:18 PM PDT 24 Apr 04 02:47:19 PM PDT 24 235400713 ps
T815 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3049992647 Apr 04 02:47:15 PM PDT 24 Apr 04 02:47:16 PM PDT 24 21629963 ps
T816 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2281053280 Apr 04 02:47:27 PM PDT 24 Apr 04 02:47:30 PM PDT 24 18451953 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2496012994 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:17 PM PDT 24 28811091 ps
T818 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1329750985 Apr 04 02:47:34 PM PDT 24 Apr 04 02:47:35 PM PDT 24 16975765 ps
T819 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1468119529 Apr 04 02:47:15 PM PDT 24 Apr 04 02:47:17 PM PDT 24 141321210 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.72732977 Apr 04 02:47:19 PM PDT 24 Apr 04 02:47:19 PM PDT 24 39783222 ps
T821 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1791414330 Apr 04 02:47:31 PM PDT 24 Apr 04 02:47:32 PM PDT 24 20329097 ps
T822 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3560300761 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 14643583 ps
T823 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3765973890 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 13142201 ps
T824 /workspace/coverage/cover_reg_top/16.gpio_intr_test.727697664 Apr 04 02:47:18 PM PDT 24 Apr 04 02:47:19 PM PDT 24 39361281 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4167202216 Apr 04 02:47:02 PM PDT 24 Apr 04 02:47:05 PM PDT 24 81084784 ps
T826 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3208299292 Apr 04 02:47:27 PM PDT 24 Apr 04 02:47:29 PM PDT 24 77421740 ps
T827 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1287181346 Apr 04 02:47:26 PM PDT 24 Apr 04 02:47:27 PM PDT 24 21803059 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2252104982 Apr 04 02:47:07 PM PDT 24 Apr 04 02:47:08 PM PDT 24 109813372 ps
T829 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3881158147 Apr 04 02:47:29 PM PDT 24 Apr 04 02:47:30 PM PDT 24 38431353 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2179743823 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 25419906 ps
T831 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1665783402 Apr 04 02:47:25 PM PDT 24 Apr 04 02:47:25 PM PDT 24 59978649 ps
T832 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2898828738 Apr 04 02:47:08 PM PDT 24 Apr 04 02:47:10 PM PDT 24 98079750 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.455973358 Apr 04 02:47:08 PM PDT 24 Apr 04 02:47:09 PM PDT 24 45083540 ps
T834 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2399322914 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:19 PM PDT 24 89288590 ps
T94 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2200722516 Apr 04 02:47:05 PM PDT 24 Apr 04 02:47:06 PM PDT 24 48711249 ps
T835 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3770406062 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:18 PM PDT 24 17740072 ps
T836 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2190715748 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:17 PM PDT 24 13873759 ps
T837 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1535838143 Apr 04 02:47:35 PM PDT 24 Apr 04 02:47:36 PM PDT 24 11968057 ps
T838 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3755953065 Apr 04 02:47:20 PM PDT 24 Apr 04 02:47:23 PM PDT 24 88059772 ps
T839 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.683054928 Apr 04 02:47:17 PM PDT 24 Apr 04 02:47:19 PM PDT 24 83745429 ps
T840 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3429161099 Apr 04 02:47:16 PM PDT 24 Apr 04 02:47:18 PM PDT 24 80905144 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1187426129 Apr 04 02:47:02 PM PDT 24 Apr 04 02:47:03 PM PDT 24 41877481 ps
T842 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.892773736 Apr 04 02:47:26 PM PDT 24 Apr 04 02:47:28 PM PDT 24 233282304 ps
T843 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3411807645 Apr 04 02:47:14 PM PDT 24 Apr 04 02:47:15 PM PDT 24 15217511 ps
T844 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3486125403 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 31465628 ps
T845 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.10281548 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 952868392 ps
T846 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.522141611 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 279155820 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.362015453 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:25 PM PDT 24 81280796 ps
T848 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3552073034 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:15 PM PDT 24 374230006 ps
T849 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2612211179 Apr 04 02:03:01 PM PDT 24 Apr 04 02:03:06 PM PDT 24 128448163 ps
T850 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247564694 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:24 PM PDT 24 252659040 ps
T851 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1360908790 Apr 04 02:03:26 PM PDT 24 Apr 04 02:03:27 PM PDT 24 216819219 ps
T852 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455789870 Apr 04 02:02:59 PM PDT 24 Apr 04 02:03:04 PM PDT 24 71183677 ps
T853 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3885357236 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 56808824 ps
T854 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3937239717 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 384742192 ps
T855 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.161923824 Apr 04 02:03:01 PM PDT 24 Apr 04 02:03:06 PM PDT 24 79880664 ps
T856 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.427192572 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:23 PM PDT 24 218686910 ps
T857 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.410164913 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:13 PM PDT 24 269759424 ps
T858 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.108017336 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 64003154 ps
T859 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445357952 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:24 PM PDT 24 109444162 ps
T860 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2987336334 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 147076132 ps
T861 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128103256 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 177123000 ps
T862 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012580202 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 279924859 ps
T863 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324530829 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:15 PM PDT 24 86493213 ps
T864 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.753415202 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 80231829 ps
T865 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2533356756 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 460140920 ps
T866 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1681161550 Apr 04 02:03:16 PM PDT 24 Apr 04 02:03:17 PM PDT 24 49127174 ps
T867 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.289470812 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:23 PM PDT 24 59194236 ps
T868 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2670715681 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 102345689 ps
T869 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3814513883 Apr 04 02:03:25 PM PDT 24 Apr 04 02:03:27 PM PDT 24 115671184 ps
T870 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1500282115 Apr 04 02:03:28 PM PDT 24 Apr 04 02:03:29 PM PDT 24 159123848 ps
T871 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2344558916 Apr 04 02:03:03 PM PDT 24 Apr 04 02:03:08 PM PDT 24 1182342757 ps
T872 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.184397782 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 49824857 ps
T873 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2441829480 Apr 04 02:03:15 PM PDT 24 Apr 04 02:03:16 PM PDT 24 225963305 ps
T874 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2476590416 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 80187741 ps
T875 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2289273215 Apr 04 02:03:13 PM PDT 24 Apr 04 02:03:15 PM PDT 24 92086735 ps
T876 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1681402655 Apr 04 02:03:26 PM PDT 24 Apr 04 02:03:27 PM PDT 24 40791835 ps
T877 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364418979 Apr 04 02:03:15 PM PDT 24 Apr 04 02:03:16 PM PDT 24 264300009 ps
T878 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1933015851 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 50564504 ps
T879 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.312181982 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:24 PM PDT 24 30637522 ps
T880 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3629893615 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 87761730 ps
T881 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2653177491 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:06 PM PDT 24 56276103 ps
T882 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.223176425 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:08 PM PDT 24 80016105 ps
T883 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697580990 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:12 PM PDT 24 161138701 ps
T884 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1626475784 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 32147865 ps
T885 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3314450490 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:25 PM PDT 24 198813086 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3616103077 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:23 PM PDT 24 286334331 ps
T887 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3737840981 Apr 04 02:03:03 PM PDT 24 Apr 04 02:03:06 PM PDT 24 272164240 ps
T888 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.937781562 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:13 PM PDT 24 266967876 ps
T889 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2022946540 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 85809447 ps
T890 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3911678140 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 126603330 ps
T891 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.957628686 Apr 04 02:03:15 PM PDT 24 Apr 04 02:03:17 PM PDT 24 93669507 ps
T892 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.87307093 Apr 04 02:03:26 PM PDT 24 Apr 04 02:03:27 PM PDT 24 86448439 ps
T893 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1126445691 Apr 04 02:02:59 PM PDT 24 Apr 04 02:03:06 PM PDT 24 296779903 ps
T894 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2802818510 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:14 PM PDT 24 71597510 ps
T895 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3470929191 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 253651935 ps
T896 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3865960093 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:05 PM PDT 24 41658445 ps
T897 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3175450319 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 247089124 ps
T898 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.543436261 Apr 04 02:03:15 PM PDT 24 Apr 04 02:03:16 PM PDT 24 24298204 ps
T899 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3642748939 Apr 04 02:03:15 PM PDT 24 Apr 04 02:03:16 PM PDT 24 117966531 ps
T900 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2176488102 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 42933369 ps
T901 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925307410 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:26 PM PDT 24 151558368 ps
T902 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3252877359 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 141233490 ps
T903 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.538399260 Apr 04 02:03:01 PM PDT 24 Apr 04 02:03:06 PM PDT 24 317068048 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3340080559 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:14 PM PDT 24 139199558 ps
T905 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.460249608 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:22 PM PDT 24 33903884 ps
T906 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2997973017 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 168179359 ps
T907 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3160034584 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:24 PM PDT 24 77541124 ps
T908 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.966350168 Apr 04 02:03:13 PM PDT 24 Apr 04 02:03:16 PM PDT 24 145317446 ps
T909 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2440286544 Apr 04 02:03:26 PM PDT 24 Apr 04 02:03:27 PM PDT 24 359585049 ps
T910 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2167108201 Apr 04 02:03:35 PM PDT 24 Apr 04 02:03:36 PM PDT 24 370073275 ps
T911 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.953404323 Apr 04 02:03:03 PM PDT 24 Apr 04 02:03:06 PM PDT 24 67422373 ps
T912 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1503726056 Apr 04 02:03:02 PM PDT 24 Apr 04 02:03:08 PM PDT 24 309565781 ps
T913 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1816196312 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:12 PM PDT 24 53653981 ps
T914 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2199734037 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 58300572 ps
T915 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.550383462 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:24 PM PDT 24 48143733 ps
T916 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1657823167 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:12 PM PDT 24 49360914 ps
T917 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1933260524 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 48326034 ps
T918 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3956531505 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:23 PM PDT 24 60701241 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3863156554 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:06 PM PDT 24 270100417 ps
T920 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092555579 Apr 04 02:02:59 PM PDT 24 Apr 04 02:03:06 PM PDT 24 333404500 ps
T921 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2277784407 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:15 PM PDT 24 37690655 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.596159408 Apr 04 02:03:28 PM PDT 24 Apr 04 02:03:29 PM PDT 24 255280062 ps
T923 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3400930123 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:15 PM PDT 24 69110484 ps
T924 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2569987766 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 206313131 ps
T925 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.340892138 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:25 PM PDT 24 22028124 ps
T926 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1200189938 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:23 PM PDT 24 23060390 ps
T927 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398645926 Apr 04 02:03:01 PM PDT 24 Apr 04 02:03:05 PM PDT 24 111067146 ps
T928 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693944639 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:25 PM PDT 24 127421476 ps
T929 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3591314938 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 78799019 ps
T930 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1691459078 Apr 04 02:03:12 PM PDT 24 Apr 04 02:03:14 PM PDT 24 95904408 ps
T931 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.977319849 Apr 04 02:03:13 PM PDT 24 Apr 04 02:03:15 PM PDT 24 351383054 ps
T932 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232601322 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:24 PM PDT 24 69153589 ps
T933 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3120891676 Apr 04 02:03:22 PM PDT 24 Apr 04 02:03:23 PM PDT 24 122295685 ps
T934 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.180064634 Apr 04 02:03:23 PM PDT 24 Apr 04 02:03:24 PM PDT 24 172707650 ps
T935 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1153541576 Apr 04 02:03:24 PM PDT 24 Apr 04 02:03:26 PM PDT 24 144754645 ps
T936 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.78168652 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:13 PM PDT 24 91168633 ps
T937 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213102663 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 162459971 ps
T938 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1786212039 Apr 04 02:03:26 PM PDT 24 Apr 04 02:03:27 PM PDT 24 201489824 ps
T939 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1871249394 Apr 04 02:03:11 PM PDT 24 Apr 04 02:03:13 PM PDT 24 167365181 ps
T940 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3689336559 Apr 04 02:03:14 PM PDT 24 Apr 04 02:03:16 PM PDT 24 142165587 ps
T941 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3418913360 Apr 04 02:03:00 PM PDT 24 Apr 04 02:03:05 PM PDT 24 186756563 ps
T942 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.680277549 Apr 04 02:02:58 PM PDT 24 Apr 04 02:03:04 PM PDT 24 300321267 ps
T943 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1473402841 Apr 04 02:03:21 PM PDT 24 Apr 04 02:03:23 PM PDT 24 46851353 ps

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2101542908
Short name T2
Test name
Test status
Simulation time 238445213 ps
CPU time 2.94 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:16 PM PDT 24
Peak memory 198212 kb
Host smart-27cff29a-4d36-4ffd-9bb4-7c1095dfdd00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101542908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2101542908
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1393307852
Short name T54
Test name
Test status
Simulation time 63360128 ps
CPU time 2.45 seconds
Started Apr 04 03:39:27 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 198332 kb
Host smart-b4dede26-22d6-4e08-853f-aad326215f70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393307852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1393307852
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3620895192
Short name T18
Test name
Test status
Simulation time 29525992404 ps
CPU time 98.85 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:41:36 PM PDT 24
Peak memory 198304 kb
Host smart-4bf97321-ff24-4aac-885c-efdef6ddfe05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620895192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3620895192
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2921701367
Short name T59
Test name
Test status
Simulation time 46103242275 ps
CPU time 512.99 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:47:07 PM PDT 24
Peak memory 198420 kb
Host smart-1f1bf0a8-428e-43a3-b5e1-f9ced7bedff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2921701367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2921701367
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3874283596
Short name T35
Test name
Test status
Simulation time 134899520 ps
CPU time 0.79 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 213636 kb
Host smart-97358ecb-23cb-4a22-88ba-f7a5e7f66171
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874283596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3874283596
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3787197818
Short name T31
Test name
Test status
Simulation time 121488922 ps
CPU time 1.59 seconds
Started Apr 04 02:47:01 PM PDT 24
Finished Apr 04 02:47:03 PM PDT 24
Peak memory 198236 kb
Host smart-e77d5370-49ff-4f18-9395-d57ad825a08e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787197818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3787197818
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2617335116
Short name T197
Test name
Test status
Simulation time 23341344 ps
CPU time 0.58 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 194076 kb
Host smart-d297f6ff-b9c1-4813-aee3-12663737e620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617335116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2617335116
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.3986345453
Short name T80
Test name
Test status
Simulation time 12813764 ps
CPU time 0.65 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:16 PM PDT 24
Peak memory 195144 kb
Host smart-3a940b87-7040-47aa-851a-3b3f0706ddda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986345453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.3986345453
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2350251787
Short name T99
Test name
Test status
Simulation time 62005978 ps
CPU time 0.83 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 196652 kb
Host smart-8fec09f0-9f40-4319-b8dd-9d82ead52b85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350251787 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2350251787
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4082531471
Short name T116
Test name
Test status
Simulation time 311131990 ps
CPU time 1.1 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198256 kb
Host smart-d4f933bc-157f-4f6d-ae76-275c92c55fb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082531471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4082531471
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3076289034
Short name T40
Test name
Test status
Simulation time 216510121 ps
CPU time 1.13 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:16 PM PDT 24
Peak memory 198272 kb
Host smart-2dfb4fb4-b2de-4e89-b229-14e8397a5279
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076289034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3076289034
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2005478632
Short name T752
Test name
Test status
Simulation time 53298499 ps
CPU time 0.74 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 194964 kb
Host smart-fd71690f-8b72-4569-ab68-4e9aee79f920
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005478632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2005478632
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1351440397
Short name T798
Test name
Test status
Simulation time 309198591 ps
CPU time 3.15 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:09 PM PDT 24
Peak memory 198248 kb
Host smart-ab7b10a4-88d9-447c-8cbc-a22ac410b45c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351440397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1351440397
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2200722516
Short name T94
Test name
Test status
Simulation time 48711249 ps
CPU time 0.6 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 194676 kb
Host smart-a2bb3af2-1985-4cd8-a12d-488f7bf32dc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200722516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2200722516
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2252104982
Short name T828
Test name
Test status
Simulation time 109813372 ps
CPU time 0.85 seconds
Started Apr 04 02:47:07 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 198200 kb
Host smart-1673f9b2-fe73-412b-b3c7-f2d2d52ef0f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252104982 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2252104982
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3191318559
Short name T739
Test name
Test status
Simulation time 14360698 ps
CPU time 0.62 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 193500 kb
Host smart-b2a6cf46-cc1b-4265-9569-70f1cedda2ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191318559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3191318559
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1461653016
Short name T799
Test name
Test status
Simulation time 12097603 ps
CPU time 0.59 seconds
Started Apr 04 02:47:08 PM PDT 24
Finished Apr 04 02:47:09 PM PDT 24
Peak memory 194488 kb
Host smart-2e6d6922-7002-4f76-9748-43cede5d749b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461653016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1461653016
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.832296214
Short name T797
Test name
Test status
Simulation time 140622864 ps
CPU time 0.8 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 196412 kb
Host smart-e9b7e5b3-042b-408d-b30f-aca3a09f0803
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832296214 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.832296214
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.692132566
Short name T782
Test name
Test status
Simulation time 452436778 ps
CPU time 2.18 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 198244 kb
Host smart-f54c50b0-ebac-4920-9ee1-3d0c2d9fd89c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692132566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.692132566
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4278517378
Short name T762
Test name
Test status
Simulation time 18635168 ps
CPU time 0.7 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 195056 kb
Host smart-bae023e8-0c22-49cb-a832-a2b2d0dd4ce8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278517378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4278517378
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.4167202216
Short name T825
Test name
Test status
Simulation time 81084784 ps
CPU time 2.95 seconds
Started Apr 04 02:47:02 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 197416 kb
Host smart-14139cb8-d780-4d0d-9ad8-d34bfc119167
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167202216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.4167202216
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3510297283
Short name T87
Test name
Test status
Simulation time 123918214 ps
CPU time 0.6 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 194556 kb
Host smart-1059ed0e-0c56-4758-be37-94c6c6c19b01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510297283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3510297283
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3123044319
Short name T767
Test name
Test status
Simulation time 126119656 ps
CPU time 0.85 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 198204 kb
Host smart-c7d9ae47-9d44-4cc3-907b-46bf361ca89f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123044319 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3123044319
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3527644201
Short name T83
Test name
Test status
Simulation time 56595461 ps
CPU time 0.66 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 195816 kb
Host smart-d2b24f39-a697-4983-9e4a-5e162b9ca796
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527644201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3527644201
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2310356257
Short name T796
Test name
Test status
Simulation time 12838607 ps
CPU time 0.6 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 193888 kb
Host smart-0e9122b8-80b6-4108-9117-22fe01a4dda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310356257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2310356257
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3874930193
Short name T753
Test name
Test status
Simulation time 123261550 ps
CPU time 1.56 seconds
Started Apr 04 02:47:02 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 198088 kb
Host smart-e51df189-de35-4182-b823-26a5e79ef5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874930193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3874930193
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2898828738
Short name T832
Test name
Test status
Simulation time 98079750 ps
CPU time 1.47 seconds
Started Apr 04 02:47:08 PM PDT 24
Finished Apr 04 02:47:10 PM PDT 24
Peak memory 198176 kb
Host smart-a9eece8f-0b48-418f-8ef1-4c7594647977
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898828738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2898828738
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1557960074
Short name T738
Test name
Test status
Simulation time 107811379 ps
CPU time 0.86 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 198056 kb
Host smart-ec7b8fd5-fb36-444c-823e-e2367374d13c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557960074 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1557960074
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2190715748
Short name T836
Test name
Test status
Simulation time 13873759 ps
CPU time 0.57 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 193788 kb
Host smart-fc8ea7ef-6cd5-4420-8867-0b80916ff7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190715748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2190715748
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1468119529
Short name T819
Test name
Test status
Simulation time 141321210 ps
CPU time 0.83 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 197300 kb
Host smart-f6dcd33d-88e5-4c9e-9ce4-ed9c95b02c43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468119529 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1468119529
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.617476246
Short name T734
Test name
Test status
Simulation time 95576059 ps
CPU time 1.3 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198204 kb
Host smart-12f230b0-0298-4b02-8446-b26f62d34e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617476246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.617476246
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.683054928
Short name T839
Test name
Test status
Simulation time 83745429 ps
CPU time 0.88 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 197804 kb
Host smart-1121f892-c9ce-4e16-a8fe-75f5efc05711
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683054928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.683054928
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1305327446
Short name T756
Test name
Test status
Simulation time 74486035 ps
CPU time 1.04 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198172 kb
Host smart-fd100c1d-97e1-499f-b7ec-7f5c07cf4196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305327446 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1305327446
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1367983317
Short name T802
Test name
Test status
Simulation time 11278075 ps
CPU time 0.61 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 195036 kb
Host smart-0d3f4084-dd42-4c0b-8d7b-8231982ec010
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367983317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1367983317
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3560300761
Short name T822
Test name
Test status
Simulation time 14643583 ps
CPU time 0.57 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 193952 kb
Host smart-28f9adea-3436-4703-aab7-85ed370b7205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560300761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3560300761
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2588069419
Short name T814
Test name
Test status
Simulation time 235400713 ps
CPU time 0.82 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 196496 kb
Host smart-ee8c6695-d5fb-4b56-9b27-71aced3919e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588069419 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2588069419
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.545444774
Short name T723
Test name
Test status
Simulation time 326825100 ps
CPU time 2.73 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:23 PM PDT 24
Peak memory 198232 kb
Host smart-9e6e5480-83b4-40a9-8f97-da29e3c3ba58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545444774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.545444774
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1926005582
Short name T784
Test name
Test status
Simulation time 99838317 ps
CPU time 1.35 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 198336 kb
Host smart-ad868487-206a-494b-bec4-971d1ebf74d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926005582 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1926005582
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3770406062
Short name T835
Test name
Test status
Simulation time 17740072 ps
CPU time 0.62 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 195308 kb
Host smart-fbf81e3c-2e9f-4a4f-8b27-37b05e34796c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770406062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3770406062
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2176916772
Short name T761
Test name
Test status
Simulation time 69467998 ps
CPU time 0.63 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 194056 kb
Host smart-adc610b4-c182-492e-8f2b-a95e09d451eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176916772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2176916772
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.72732977
Short name T820
Test name
Test status
Simulation time 39783222 ps
CPU time 0.65 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 195144 kb
Host smart-03c219de-fc54-4fbf-a1f5-52a74f158b21
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72732977 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.gpio_same_csr_outstanding.72732977
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3258688746
Short name T719
Test name
Test status
Simulation time 117053495 ps
CPU time 1.7 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:16 PM PDT 24
Peak memory 198332 kb
Host smart-dd44222c-9d0a-492b-be7c-639048f3f6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258688746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3258688746
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2308293262
Short name T44
Test name
Test status
Simulation time 133762135 ps
CPU time 0.93 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 198116 kb
Host smart-4875e3a9-4f07-4031-ac4f-7a3a2ff341df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308293262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2308293262
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4181043212
Short name T748
Test name
Test status
Simulation time 36525444 ps
CPU time 0.97 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198016 kb
Host smart-b18c829c-e003-41e5-acdf-c7d44349fdbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181043212 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4181043212
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2692590051
Short name T750
Test name
Test status
Simulation time 53504474 ps
CPU time 0.59 seconds
Started Apr 04 02:47:21 PM PDT 24
Finished Apr 04 02:47:22 PM PDT 24
Peak memory 193528 kb
Host smart-82f53c7f-333a-44c7-ade1-1a70d6894fe7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692590051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2692590051
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.926721109
Short name T718
Test name
Test status
Simulation time 39975072 ps
CPU time 0.6 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 194464 kb
Host smart-d593973e-f5f1-4f14-a3d3-8d079425a8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926721109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.926721109
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2496012994
Short name T817
Test name
Test status
Simulation time 28811091 ps
CPU time 0.73 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 196284 kb
Host smart-82a88113-a22e-4eae-bd13-592e8d4a231b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496012994 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2496012994
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2399322914
Short name T834
Test name
Test status
Simulation time 89288590 ps
CPU time 2.43 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198208 kb
Host smart-1ab51047-4137-4a27-bdea-3ac8a8a8c828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399322914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2399322914
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.781704017
Short name T744
Test name
Test status
Simulation time 32097925 ps
CPU time 0.73 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198120 kb
Host smart-2edb0ccf-17fb-4ab3-a40b-54490ee4ec2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781704017 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.781704017
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.895427279
Short name T806
Test name
Test status
Simulation time 13913307 ps
CPU time 0.62 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 194972 kb
Host smart-1397a891-a2b3-49c1-ad41-3577b76be989
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895427279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.895427279
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.898123534
Short name T716
Test name
Test status
Simulation time 53156661 ps
CPU time 0.59 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 194648 kb
Host smart-d5b635e7-7572-4971-b7ff-42522542d38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898123534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.898123534
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2695900575
Short name T102
Test name
Test status
Simulation time 35503538 ps
CPU time 0.62 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 195100 kb
Host smart-453f613d-b131-4b27-8a72-764641a743af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695900575 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2695900575
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3755953065
Short name T838
Test name
Test status
Simulation time 88059772 ps
CPU time 1.95 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:23 PM PDT 24
Peak memory 198300 kb
Host smart-7636deab-eadc-4015-acdc-6fd29be3da6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755953065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3755953065
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3520715057
Short name T30
Test name
Test status
Simulation time 149600367 ps
CPU time 0.88 seconds
Started Apr 04 02:47:21 PM PDT 24
Finished Apr 04 02:47:23 PM PDT 24
Peak memory 196952 kb
Host smart-e0bb7962-7915-40c5-9a77-64edbec4a460
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520715057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3520715057
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.295610265
Short name T720
Test name
Test status
Simulation time 414648723 ps
CPU time 0.87 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 198200 kb
Host smart-9e98c849-5cd7-490e-9fdf-abe715eebaae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295610265 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.295610265
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1135742216
Short name T811
Test name
Test status
Simulation time 17910560 ps
CPU time 0.63 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 195216 kb
Host smart-10fd3ec2-922e-4429-a439-84d736d8d2f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135742216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1135742216
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1085677839
Short name T776
Test name
Test status
Simulation time 36159600 ps
CPU time 0.56 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 193932 kb
Host smart-9cb8332b-320e-4bfb-81aa-4e4e945c2d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085677839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1085677839
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2446781679
Short name T82
Test name
Test status
Simulation time 17860407 ps
CPU time 0.61 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 195408 kb
Host smart-01cf14ad-a0a3-4e69-9f00-1c10408f8cf5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446781679 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2446781679
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.834120311
Short name T810
Test name
Test status
Simulation time 474118951 ps
CPU time 2.56 seconds
Started Apr 04 02:47:21 PM PDT 24
Finished Apr 04 02:47:24 PM PDT 24
Peak memory 198136 kb
Host smart-21d1a0aa-78c7-4741-b53a-fd7dfe9698e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834120311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.834120311
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.203250526
Short name T38
Test name
Test status
Simulation time 486891593 ps
CPU time 1.36 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198324 kb
Host smart-2cc38999-649b-42c3-a54e-35d9130d484a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203250526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.203250526
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.95992680
Short name T733
Test name
Test status
Simulation time 22252576 ps
CPU time 0.73 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 198188 kb
Host smart-ed3dbfb9-0f60-4e9b-836c-5166c80c5071
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95992680 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.95992680
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1133070722
Short name T114
Test name
Test status
Simulation time 13487049 ps
CPU time 0.59 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 193552 kb
Host smart-c6dd24eb-fcd7-4b10-aef2-1b752964fd10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133070722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1133070722
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.727697664
Short name T824
Test name
Test status
Simulation time 39361281 ps
CPU time 0.57 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 194576 kb
Host smart-db2ef6aa-a1f7-4882-97af-dcbd639d1607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727697664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.727697664
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.956645349
Short name T97
Test name
Test status
Simulation time 26930358 ps
CPU time 0.63 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 194788 kb
Host smart-c61bd7ba-d5f3-4836-869d-e3ad24516bac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956645349 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.956645349
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.892773736
Short name T842
Test name
Test status
Simulation time 233282304 ps
CPU time 1.51 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 198252 kb
Host smart-280cf439-08c7-4558-a4fb-4dd8b143cbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892773736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.892773736
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3938450963
Short name T43
Test name
Test status
Simulation time 81128738 ps
CPU time 1.16 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 198324 kb
Host smart-022f8436-cac3-4554-a222-c81f5c49630d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938450963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3938450963
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4028004836
Short name T740
Test name
Test status
Simulation time 123760561 ps
CPU time 0.95 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:29 PM PDT 24
Peak memory 198192 kb
Host smart-6f602bbc-63c5-4883-a32e-a59dc168a4c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028004836 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4028004836
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.984466172
Short name T795
Test name
Test status
Simulation time 14621575 ps
CPU time 0.6 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 195484 kb
Host smart-524d9848-01c3-47e7-9ac0-529bcf852f82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984466172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.984466172
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3077226101
Short name T765
Test name
Test status
Simulation time 15964770 ps
CPU time 0.57 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 193908 kb
Host smart-9bb12ca2-786f-4a29-94b9-4ec7f9ff9cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077226101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3077226101
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3024594837
Short name T790
Test name
Test status
Simulation time 33416851 ps
CPU time 0.64 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:29 PM PDT 24
Peak memory 194884 kb
Host smart-4b0a2a93-e995-4ef2-8b56-225408c297c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024594837 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3024594837
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.240747104
Short name T726
Test name
Test status
Simulation time 52584755 ps
CPU time 1.21 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:22 PM PDT 24
Peak memory 198248 kb
Host smart-2f129c7a-d159-41cb-a20e-bd61c9fd3c63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240747104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.240747104
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1464757860
Short name T41
Test name
Test status
Simulation time 162965808 ps
CPU time 1.12 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 198292 kb
Host smart-7064737d-1d59-4dd1-a644-057f9a9ca52a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464757860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1464757860
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2488102854
Short name T780
Test name
Test status
Simulation time 201828097 ps
CPU time 1.16 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 198120 kb
Host smart-463d0440-c1b4-4f33-9a33-0ad57ba4842b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488102854 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2488102854
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3633657350
Short name T773
Test name
Test status
Simulation time 51160445 ps
CPU time 0.57 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 194864 kb
Host smart-816d2456-bd08-4404-a7b3-fb84c12c61c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633657350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3633657350
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1149700976
Short name T778
Test name
Test status
Simulation time 102531170 ps
CPU time 0.62 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 194016 kb
Host smart-c830a090-e9e0-4251-bb69-134c985933c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149700976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1149700976
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2438704201
Short name T100
Test name
Test status
Simulation time 14121448 ps
CPU time 0.62 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 194500 kb
Host smart-fe3a1885-8ed0-4327-92d4-51f81d349210
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438704201 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2438704201
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.268541084
Short name T736
Test name
Test status
Simulation time 43955850 ps
CPU time 2.24 seconds
Started Apr 04 02:47:21 PM PDT 24
Finished Apr 04 02:47:24 PM PDT 24
Peak memory 198220 kb
Host smart-65c4b3f6-0a0f-4d93-ae0f-8dddf7211775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268541084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.268541084
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.10218286
Short name T32
Test name
Test status
Simulation time 138393081 ps
CPU time 0.86 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 198068 kb
Host smart-644f8b63-fdaa-4412-ba14-d759131ceae8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10218286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.gpio_tl_intg_err.10218286
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3437555941
Short name T732
Test name
Test status
Simulation time 124958346 ps
CPU time 0.84 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 198192 kb
Host smart-8dca916c-9b4b-4a4b-9784-95278e7e61d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437555941 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3437555941
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1639674268
Short name T95
Test name
Test status
Simulation time 18262079 ps
CPU time 0.62 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 195184 kb
Host smart-bf8bf729-75cb-4979-915e-d5334991730a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639674268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1639674268
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1707053967
Short name T721
Test name
Test status
Simulation time 15385200 ps
CPU time 0.6 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 194668 kb
Host smart-099a7901-36be-4a33-9fec-e56205c8ddc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707053967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1707053967
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.347032171
Short name T96
Test name
Test status
Simulation time 95778095 ps
CPU time 0.75 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 197212 kb
Host smart-58ff1ec2-e4dd-4158-a76e-ffd795b9b184
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347032171 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.347032171
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3703886370
Short name T771
Test name
Test status
Simulation time 78092684 ps
CPU time 1.21 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:22 PM PDT 24
Peak memory 198296 kb
Host smart-3ec2d3bc-53a5-4750-93a4-f33d5bdbed40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703886370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3703886370
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3881682053
Short name T803
Test name
Test status
Simulation time 40291642 ps
CPU time 0.82 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 197192 kb
Host smart-1f5c0769-e6a0-43d1-9b24-4321efabd356
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881682053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3881682053
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.478132464
Short name T93
Test name
Test status
Simulation time 116469044 ps
CPU time 0.88 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 196276 kb
Host smart-c8119ba2-cb79-4922-9500-a2289dac6609
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478132464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.478132464
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4240860739
Short name T85
Test name
Test status
Simulation time 3702241863 ps
CPU time 3.32 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 196760 kb
Host smart-53991ea2-f143-4b91-86fe-f793548b7f0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240860739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4240860739
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.404379761
Short name T86
Test name
Test status
Simulation time 34587427 ps
CPU time 0.63 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 194956 kb
Host smart-b7a927b5-2810-4860-947c-bf991dc6986b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404379761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.404379761
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1733924063
Short name T785
Test name
Test status
Simulation time 132995657 ps
CPU time 1 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 198200 kb
Host smart-36caff61-5ab2-42e1-85fc-06b6baf3d793
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733924063 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1733924063
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.455973358
Short name T833
Test name
Test status
Simulation time 45083540 ps
CPU time 0.61 seconds
Started Apr 04 02:47:08 PM PDT 24
Finished Apr 04 02:47:09 PM PDT 24
Peak memory 194868 kb
Host smart-00369fd3-6c33-45e3-bfc8-9de8238a5cbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455973358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.455973358
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2695379751
Short name T731
Test name
Test status
Simulation time 21833206 ps
CPU time 0.57 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 193876 kb
Host smart-22cad128-3c69-4ed2-8571-4ab508f546bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695379751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2695379751
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1493356280
Short name T81
Test name
Test status
Simulation time 192196378 ps
CPU time 0.86 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 197440 kb
Host smart-49bb702c-20a6-440e-a415-4e45a48ee10b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493356280 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1493356280
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1128112478
Short name T777
Test name
Test status
Simulation time 48624935 ps
CPU time 1.27 seconds
Started Apr 04 02:47:04 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 198244 kb
Host smart-80a7ac88-93d7-48bd-8260-172df1929271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128112478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1128112478
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3588893556
Short name T758
Test name
Test status
Simulation time 1627532441 ps
CPU time 1.44 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 198248 kb
Host smart-f266ad59-e9a3-42bc-885a-06ebdde7a5a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588893556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3588893556
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4058724925
Short name T757
Test name
Test status
Simulation time 180441003 ps
CPU time 0.55 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 194568 kb
Host smart-dff82328-9b70-4c93-a1dc-be5d2570a3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058724925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4058724925
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3256356468
Short name T745
Test name
Test status
Simulation time 169425995 ps
CPU time 0.59 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 194656 kb
Host smart-dd7ef397-e286-4419-a918-b1c3627c4b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256356468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3256356468
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1462753913
Short name T769
Test name
Test status
Simulation time 63315042 ps
CPU time 0.6 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:26 PM PDT 24
Peak memory 193992 kb
Host smart-c9449fc5-a514-4ddc-a35f-76c5b9c88754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462753913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1462753913
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1791414330
Short name T821
Test name
Test status
Simulation time 20329097 ps
CPU time 0.59 seconds
Started Apr 04 02:47:31 PM PDT 24
Finished Apr 04 02:47:32 PM PDT 24
Peak memory 193860 kb
Host smart-e9514afb-4a95-45ff-a309-fe50d46967ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791414330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1791414330
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2240368528
Short name T735
Test name
Test status
Simulation time 36470822 ps
CPU time 0.6 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 193952 kb
Host smart-892b2043-071c-4c38-b325-820c615ca3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240368528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2240368528
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1329750985
Short name T818
Test name
Test status
Simulation time 16975765 ps
CPU time 0.62 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 194004 kb
Host smart-ae7550a7-d53e-4376-b9e2-84dcb495a08e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329750985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1329750985
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1619564976
Short name T794
Test name
Test status
Simulation time 36397027 ps
CPU time 0.6 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:26 PM PDT 24
Peak memory 193872 kb
Host smart-8b4cdb2c-65cf-435e-a230-42f932417e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619564976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1619564976
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1535838143
Short name T837
Test name
Test status
Simulation time 11968057 ps
CPU time 0.61 seconds
Started Apr 04 02:47:35 PM PDT 24
Finished Apr 04 02:47:36 PM PDT 24
Peak memory 193944 kb
Host smart-32c55f14-98e8-4b49-841f-1ad280b1531e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535838143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1535838143
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1376683502
Short name T741
Test name
Test status
Simulation time 43864958 ps
CPU time 0.55 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:27 PM PDT 24
Peak memory 193784 kb
Host smart-e464bee1-b9ee-40dc-b3f8-548ddbd270cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376683502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1376683502
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2350741500
Short name T787
Test name
Test status
Simulation time 55727199 ps
CPU time 0.55 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:26 PM PDT 24
Peak memory 194564 kb
Host smart-92264a4f-bba1-4674-aeb8-26f4fb7db88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350741500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2350741500
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3323197637
Short name T766
Test name
Test status
Simulation time 50305178 ps
CPU time 0.69 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 194768 kb
Host smart-34d25d22-696f-457a-8309-efc288f0b301
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323197637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3323197637
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1761948220
Short name T743
Test name
Test status
Simulation time 1004979564 ps
CPU time 3.14 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 196960 kb
Host smart-af810341-cfd8-49fe-a94b-0a6706ac0ba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761948220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1761948220
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3579037338
Short name T91
Test name
Test status
Simulation time 13398429 ps
CPU time 0.6 seconds
Started Apr 04 02:47:06 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 194564 kb
Host smart-76e128fa-5240-4f36-99c0-d8d659dbb05f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579037338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3579037338
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1589255676
Short name T808
Test name
Test status
Simulation time 31426081 ps
CPU time 0.65 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 197904 kb
Host smart-4fecf1af-d183-445a-9692-d9c44270800d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589255676 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1589255676
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.740144090
Short name T84
Test name
Test status
Simulation time 12410160 ps
CPU time 0.58 seconds
Started Apr 04 02:47:07 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 194616 kb
Host smart-cad75775-65e4-4047-8038-a63af32628ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740144090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.740144090
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1187426129
Short name T841
Test name
Test status
Simulation time 41877481 ps
CPU time 0.6 seconds
Started Apr 04 02:47:02 PM PDT 24
Finished Apr 04 02:47:03 PM PDT 24
Peak memory 193956 kb
Host smart-335767f6-adc7-41b4-b7f5-a934d1ff6e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187426129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1187426129
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1818371178
Short name T788
Test name
Test status
Simulation time 35304771 ps
CPU time 0.88 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 196568 kb
Host smart-3c163d84-f65f-44b7-b446-c4a57d2cf48e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818371178 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1818371178
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.471650147
Short name T722
Test name
Test status
Simulation time 57953401 ps
CPU time 1.57 seconds
Started Apr 04 02:47:10 PM PDT 24
Finished Apr 04 02:47:12 PM PDT 24
Peak memory 198232 kb
Host smart-4942f364-3c6d-4524-9a8b-457e0ce9f3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471650147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.471650147
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.176456062
Short name T792
Test name
Test status
Simulation time 51486090 ps
CPU time 0.83 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 197392 kb
Host smart-ae2819ae-a1c0-4366-af68-96e88e790abe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176456062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.176456062
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1512551620
Short name T772
Test name
Test status
Simulation time 11837227 ps
CPU time 0.58 seconds
Started Apr 04 02:47:37 PM PDT 24
Finished Apr 04 02:47:37 PM PDT 24
Peak memory 193924 kb
Host smart-27c5a90c-f629-4400-9358-c9e13bfaf8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512551620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1512551620
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3881158147
Short name T829
Test name
Test status
Simulation time 38431353 ps
CPU time 0.53 seconds
Started Apr 04 02:47:29 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 193924 kb
Host smart-10db4c7d-e09e-49c5-9f32-5bf2243ce517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881158147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3881158147
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1592011400
Short name T755
Test name
Test status
Simulation time 17745208 ps
CPU time 0.63 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 194628 kb
Host smart-3b20385a-7072-423a-876f-e191f2fe0657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592011400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1592011400
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1665783402
Short name T831
Test name
Test status
Simulation time 59978649 ps
CPU time 0.61 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:25 PM PDT 24
Peak memory 194572 kb
Host smart-640b0dcf-a36e-4207-a593-2f1e083a99d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665783402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1665783402
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.920567109
Short name T742
Test name
Test status
Simulation time 12491876 ps
CPU time 0.6 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:47:34 PM PDT 24
Peak memory 193904 kb
Host smart-769d1205-33da-46a2-a3dc-8ff694170a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920567109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.920567109
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.702848807
Short name T730
Test name
Test status
Simulation time 15076036 ps
CPU time 0.57 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 193936 kb
Host smart-69e41864-80de-4a92-b542-40a5881be670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702848807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.702848807
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.295481952
Short name T813
Test name
Test status
Simulation time 16050631 ps
CPU time 0.6 seconds
Started Apr 04 02:47:30 PM PDT 24
Finished Apr 04 02:47:32 PM PDT 24
Peak memory 193840 kb
Host smart-7823f965-c4d4-42fa-a5c6-79d150511c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295481952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.295481952
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1287181346
Short name T827
Test name
Test status
Simulation time 21803059 ps
CPU time 0.56 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:27 PM PDT 24
Peak memory 193816 kb
Host smart-00d766e0-ba00-477e-a554-ae13c8541970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287181346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1287181346
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1576903030
Short name T728
Test name
Test status
Simulation time 20287623 ps
CPU time 0.56 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 194588 kb
Host smart-6d579c1f-c0a0-434f-b90f-63220884e48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576903030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1576903030
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2610057062
Short name T754
Test name
Test status
Simulation time 33486284 ps
CPU time 0.6 seconds
Started Apr 04 02:47:24 PM PDT 24
Finished Apr 04 02:47:25 PM PDT 24
Peak memory 194040 kb
Host smart-8d6705b3-f7ab-40d5-b47d-a5e3dcae1145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610057062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2610057062
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2179743823
Short name T830
Test name
Test status
Simulation time 25419906 ps
CPU time 0.75 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 196936 kb
Host smart-b7b3fa0c-0603-4814-b995-429cee72de81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179743823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2179743823
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.991393284
Short name T729
Test name
Test status
Simulation time 503668623 ps
CPU time 3.15 seconds
Started Apr 04 02:47:04 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 197008 kb
Host smart-b8b5dee5-94ee-432c-9711-48e04d9f2284
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991393284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.991393284
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1443792458
Short name T92
Test name
Test status
Simulation time 78507091 ps
CPU time 0.66 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 195960 kb
Host smart-40bf9794-7eee-4d62-836b-83624a3e4e9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443792458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1443792458
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2059965093
Short name T800
Test name
Test status
Simulation time 18301929 ps
CPU time 0.72 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 197860 kb
Host smart-0b61ab16-9236-407c-aa9a-dccfef1096cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059965093 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2059965093
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2331145030
Short name T768
Test name
Test status
Simulation time 164080914 ps
CPU time 0.59 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 194816 kb
Host smart-7d762e6f-2131-4748-bcd7-29480b138ad5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331145030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2331145030
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3013480053
Short name T760
Test name
Test status
Simulation time 20818525 ps
CPU time 0.63 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 194000 kb
Host smart-800a7e5c-4d61-45a9-b1a4-22ec3417cc30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013480053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3013480053
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2981998273
Short name T79
Test name
Test status
Simulation time 16459201 ps
CPU time 0.75 seconds
Started Apr 04 02:47:03 PM PDT 24
Finished Apr 04 02:47:04 PM PDT 24
Peak memory 196224 kb
Host smart-6a1c9aab-df64-4c06-9e58-0c30ae39b57f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981998273 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2981998273
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2682680899
Short name T781
Test name
Test status
Simulation time 144665617 ps
CPU time 2.61 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:08 PM PDT 24
Peak memory 198188 kb
Host smart-034038bb-7667-4859-a45e-6d3dc1ca6768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682680899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2682680899
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2891530271
Short name T115
Test name
Test status
Simulation time 95522066 ps
CPU time 1.3 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 198292 kb
Host smart-e514b2ee-bcc0-4582-ab61-9a21c6b34c1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891530271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2891530271
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2010104471
Short name T804
Test name
Test status
Simulation time 23035326 ps
CPU time 0.6 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 193876 kb
Host smart-ac52c36a-46eb-459d-b4f3-e355b567dc37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010104471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2010104471
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.717934844
Short name T812
Test name
Test status
Simulation time 22647889 ps
CPU time 0.57 seconds
Started Apr 04 02:47:25 PM PDT 24
Finished Apr 04 02:47:26 PM PDT 24
Peak memory 193848 kb
Host smart-09ae9916-15ac-4232-99fe-f257ed579158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717934844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.717934844
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2281053280
Short name T816
Test name
Test status
Simulation time 18451953 ps
CPU time 0.62 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 194612 kb
Host smart-f0b8f90a-1ec1-447c-a2ff-e9ce8ee20ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281053280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2281053280
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2145443559
Short name T786
Test name
Test status
Simulation time 28695845 ps
CPU time 0.56 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:28 PM PDT 24
Peak memory 193984 kb
Host smart-ff3697c5-d0ae-49ec-b97f-ba2496fb40b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145443559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2145443559
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1027875636
Short name T763
Test name
Test status
Simulation time 52467235 ps
CPU time 0.6 seconds
Started Apr 04 02:47:33 PM PDT 24
Finished Apr 04 02:47:34 PM PDT 24
Peak memory 194020 kb
Host smart-6e3a5d9d-a349-4b65-89f4-7a90972f401c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027875636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1027875636
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2678110104
Short name T809
Test name
Test status
Simulation time 44049090 ps
CPU time 0.6 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 193868 kb
Host smart-9844f1c5-f030-4dbc-8f99-3b910b2ee989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678110104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2678110104
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.678108850
Short name T770
Test name
Test status
Simulation time 43336208 ps
CPU time 0.55 seconds
Started Apr 04 02:47:26 PM PDT 24
Finished Apr 04 02:47:26 PM PDT 24
Peak memory 193816 kb
Host smart-69625448-e482-4230-a321-0a9e256eb09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678108850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.678108850
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4150534349
Short name T789
Test name
Test status
Simulation time 50291136 ps
CPU time 0.57 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 194560 kb
Host smart-52df69e2-4979-4fe4-85f0-0699264e794f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150534349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4150534349
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3307407795
Short name T779
Test name
Test status
Simulation time 14563832 ps
CPU time 0.59 seconds
Started Apr 04 02:47:28 PM PDT 24
Finished Apr 04 02:47:30 PM PDT 24
Peak memory 193964 kb
Host smart-e339c9de-5491-4b46-89cf-bbd44d15c450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307407795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3307407795
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1240291099
Short name T751
Test name
Test status
Simulation time 16066456 ps
CPU time 0.62 seconds
Started Apr 04 02:47:34 PM PDT 24
Finished Apr 04 02:47:35 PM PDT 24
Peak memory 194024 kb
Host smart-36b20225-268f-4f7d-989a-ecc9388ff082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240291099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1240291099
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3572473685
Short name T717
Test name
Test status
Simulation time 203637547 ps
CPU time 0.65 seconds
Started Apr 04 02:47:04 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 196900 kb
Host smart-31b05e08-c0ad-44d0-aee6-c0616d862605
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572473685 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3572473685
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1140380678
Short name T805
Test name
Test status
Simulation time 22046479 ps
CPU time 0.71 seconds
Started Apr 04 02:47:04 PM PDT 24
Finished Apr 04 02:47:05 PM PDT 24
Peak memory 195552 kb
Host smart-33cb9715-b718-4cde-ae2a-6e05013229a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140380678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1140380678
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.779998513
Short name T725
Test name
Test status
Simulation time 35255167 ps
CPU time 0.61 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 193872 kb
Host smart-7b2cb054-8e9b-4ae7-84b7-f2be55d49c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779998513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.779998513
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.94638710
Short name T774
Test name
Test status
Simulation time 59966346 ps
CPU time 0.62 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 195900 kb
Host smart-94e9ef41-e949-4799-943a-17769858b0ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94638710 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.gpio_same_csr_outstanding.94638710
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2273182893
Short name T783
Test name
Test status
Simulation time 35176563 ps
CPU time 1.65 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:07 PM PDT 24
Peak memory 198216 kb
Host smart-9c8a945c-3a9d-458a-9870-b7ffb6884874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273182893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2273182893
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2746246241
Short name T39
Test name
Test status
Simulation time 396679667 ps
CPU time 0.9 seconds
Started Apr 04 02:47:05 PM PDT 24
Finished Apr 04 02:47:06 PM PDT 24
Peak memory 198048 kb
Host smart-6342028a-ef12-4d6b-98fb-558c0605110c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746246241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2746246241
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.381133910
Short name T775
Test name
Test status
Simulation time 41812905 ps
CPU time 1.78 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198360 kb
Host smart-2bffa970-0575-4787-87cb-0c95c980a729
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381133910 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.381133910
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2568011113
Short name T88
Test name
Test status
Simulation time 21922360 ps
CPU time 0.62 seconds
Started Apr 04 02:47:13 PM PDT 24
Finished Apr 04 02:47:14 PM PDT 24
Peak memory 195168 kb
Host smart-4b78ec7b-94a0-44e9-a427-beb0de875336
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568011113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2568011113
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3765973890
Short name T823
Test name
Test status
Simulation time 13142201 ps
CPU time 0.6 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 193832 kb
Host smart-1d08d629-0ba2-409b-80e2-83612a804b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765973890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3765973890
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.596067987
Short name T101
Test name
Test status
Simulation time 83963940 ps
CPU time 0.65 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 195788 kb
Host smart-43fab62d-e898-419b-83dd-294881e8bf45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596067987 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.596067987
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4180489459
Short name T746
Test name
Test status
Simulation time 71901545 ps
CPU time 1.19 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 198240 kb
Host smart-52c09880-409b-4782-ab08-25bc1dd5b91e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180489459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4180489459
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2511570057
Short name T42
Test name
Test status
Simulation time 422377362 ps
CPU time 1.08 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 198268 kb
Host smart-02f704ef-4310-48d6-a754-e8d6b37fd237
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511570057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2511570057
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3207287596
Short name T759
Test name
Test status
Simulation time 77996134 ps
CPU time 0.68 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 198032 kb
Host smart-85ede3cf-7cac-4d1b-8a43-34e06077bf7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207287596 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3207287596
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.720777618
Short name T737
Test name
Test status
Simulation time 12892830 ps
CPU time 0.55 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 194188 kb
Host smart-ab9f3a71-5ff5-42cf-bcaf-96a82d0cef92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720777618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.720777618
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.729260418
Short name T747
Test name
Test status
Simulation time 28975267 ps
CPU time 0.64 seconds
Started Apr 04 02:47:20 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 194672 kb
Host smart-98ff08c8-ffa3-4c06-acbb-8bbdad4e775f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729260418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.729260418
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3451631355
Short name T807
Test name
Test status
Simulation time 57174893 ps
CPU time 0.85 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:15 PM PDT 24
Peak memory 196636 kb
Host smart-932ea692-c2f8-4dbe-851b-32c6f7fac454
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451631355 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3451631355
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1413591006
Short name T727
Test name
Test status
Simulation time 92768412 ps
CPU time 1.21 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:21 PM PDT 24
Peak memory 198296 kb
Host smart-d5aa8f28-6b7b-42e3-830a-415203fae1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413591006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1413591006
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1380722047
Short name T801
Test name
Test status
Simulation time 71209592 ps
CPU time 1.14 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 198264 kb
Host smart-344e8c76-acfd-44d5-9b93-965ec3024de2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380722047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1380722047
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3049992647
Short name T815
Test name
Test status
Simulation time 21629963 ps
CPU time 0.63 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:16 PM PDT 24
Peak memory 196240 kb
Host smart-405d37c6-8fe4-4557-a715-5199791944ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049992647 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3049992647
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3029270913
Short name T90
Test name
Test status
Simulation time 38781392 ps
CPU time 0.56 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 194428 kb
Host smart-c0f63091-d43b-4c65-ade8-ea8afdd1c5c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029270913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3029270913
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4182528318
Short name T764
Test name
Test status
Simulation time 162998496 ps
CPU time 0.6 seconds
Started Apr 04 02:47:18 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 193900 kb
Host smart-b001ccb6-1d4f-4bad-96cd-8a53430a2f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182528318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4182528318
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2158818969
Short name T98
Test name
Test status
Simulation time 28962725 ps
CPU time 0.75 seconds
Started Apr 04 02:47:15 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 195256 kb
Host smart-5f3ca6d7-fb3e-4233-bad9-60094f867c49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158818969 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2158818969
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.188098202
Short name T793
Test name
Test status
Simulation time 391013626 ps
CPU time 2.12 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:17 PM PDT 24
Peak memory 198260 kb
Host smart-b9b63bfc-ce98-4870-a191-dd295e32e70f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188098202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.188098202
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3429161099
Short name T840
Test name
Test status
Simulation time 80905144 ps
CPU time 0.85 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 197468 kb
Host smart-e81de53a-1986-4731-86b8-bf5d549eff24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429161099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3429161099
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.775077407
Short name T724
Test name
Test status
Simulation time 31092292 ps
CPU time 0.92 seconds
Started Apr 04 02:47:17 PM PDT 24
Finished Apr 04 02:47:19 PM PDT 24
Peak memory 198164 kb
Host smart-071db6a3-7b6d-424b-83d8-4fcc73fe10cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775077407 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.775077407
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1884850004
Short name T89
Test name
Test status
Simulation time 35120108 ps
CPU time 0.58 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:15 PM PDT 24
Peak memory 195076 kb
Host smart-a8e5e86c-89cf-4b8c-915e-8470a6790be9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884850004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1884850004
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2374234913
Short name T749
Test name
Test status
Simulation time 14419173 ps
CPU time 0.65 seconds
Started Apr 04 02:47:19 PM PDT 24
Finished Apr 04 02:47:20 PM PDT 24
Peak memory 193984 kb
Host smart-229be979-a7fc-4978-92e9-62ef39f33b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374234913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2374234913
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3411807645
Short name T843
Test name
Test status
Simulation time 15217511 ps
CPU time 0.6 seconds
Started Apr 04 02:47:14 PM PDT 24
Finished Apr 04 02:47:15 PM PDT 24
Peak memory 194672 kb
Host smart-2fa9a335-409f-48b3-9a06-bc038e4c0c20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411807645 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3411807645
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4233842395
Short name T791
Test name
Test status
Simulation time 94140180 ps
CPU time 1.02 seconds
Started Apr 04 02:47:16 PM PDT 24
Finished Apr 04 02:47:18 PM PDT 24
Peak memory 198120 kb
Host smart-22b0a64c-5377-4dec-af6f-99f906357347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233842395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4233842395
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3208299292
Short name T826
Test name
Test status
Simulation time 77421740 ps
CPU time 1.09 seconds
Started Apr 04 02:47:27 PM PDT 24
Finished Apr 04 02:47:29 PM PDT 24
Peak memory 198216 kb
Host smart-f60b9df8-aa10-4e71-90ac-06656d9fb40f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208299292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3208299292
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3061090334
Short name T229
Test name
Test status
Simulation time 20994267 ps
CPU time 0.57 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 194016 kb
Host smart-8078d7f3-490f-4b77-81d9-00143e30238b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061090334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3061090334
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.993237146
Short name T384
Test name
Test status
Simulation time 18546423 ps
CPU time 0.69 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 194376 kb
Host smart-bcecec6e-67b8-4daa-bbe8-7bf8047bd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993237146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.993237146
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3823274688
Short name T430
Test name
Test status
Simulation time 2808701959 ps
CPU time 25.54 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 197252 kb
Host smart-39d17e3a-1d6a-473b-bf11-ca675b930f91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823274688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3823274688
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1041619186
Short name T111
Test name
Test status
Simulation time 39418764 ps
CPU time 0.77 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196100 kb
Host smart-fa5d79bb-04fc-4dad-9c52-109212168839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041619186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1041619186
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2208396107
Short name T448
Test name
Test status
Simulation time 93124105 ps
CPU time 1.36 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 197228 kb
Host smart-6c1f4e22-aaa8-416c-bea9-6927c131c04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208396107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2208396107
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3025079333
Short name T618
Test name
Test status
Simulation time 187947206 ps
CPU time 2.59 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196636 kb
Host smart-496862cf-1129-45e4-82d5-3b2a12b4880f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025079333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3025079333
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1818356504
Short name T529
Test name
Test status
Simulation time 310097830 ps
CPU time 1.6 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196016 kb
Host smart-d6b95f17-e64a-4904-8ac7-2cac6c26e4f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818356504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1818356504
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2964188273
Short name T595
Test name
Test status
Simulation time 58578906 ps
CPU time 1.11 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 196236 kb
Host smart-50e0219a-a200-4490-a63e-4228332d5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964188273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2964188273
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.421814571
Short name T450
Test name
Test status
Simulation time 268393033 ps
CPU time 1.41 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 197204 kb
Host smart-a5738485-7e46-468b-b269-c84a82ee0816
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421814571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.421814571
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1546997854
Short name T233
Test name
Test status
Simulation time 108885536 ps
CPU time 2.55 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:58 PM PDT 24
Peak memory 198184 kb
Host smart-28356ff1-c731-4429-93bc-3f0dd6e48cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546997854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1546997854
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1205434812
Short name T337
Test name
Test status
Simulation time 189131166 ps
CPU time 1.1 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 196540 kb
Host smart-1bf1f188-87ee-4a9b-873b-379d31d3bbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205434812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1205434812
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.257530344
Short name T608
Test name
Test status
Simulation time 140155657 ps
CPU time 1.3 seconds
Started Apr 04 03:37:51 PM PDT 24
Finished Apr 04 03:37:52 PM PDT 24
Peak memory 197004 kb
Host smart-f0f3c6bb-2c72-456e-8753-19061c855620
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257530344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.257530344
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2291862343
Short name T713
Test name
Test status
Simulation time 35015648313 ps
CPU time 51.59 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:38:45 PM PDT 24
Peak memory 198244 kb
Host smart-deba1a98-6ef2-4599-964e-0a6318a947f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291862343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2291862343
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.474456046
Short name T207
Test name
Test status
Simulation time 15548837 ps
CPU time 0.58 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 194300 kb
Host smart-e6b549cf-cdec-4fe0-b5a9-7387dfb2028c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474456046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.474456046
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.386672601
Short name T310
Test name
Test status
Simulation time 31852066 ps
CPU time 0.77 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196160 kb
Host smart-4776cbb4-ac5a-465d-85be-00efa7c70e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386672601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.386672601
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3249835935
Short name T223
Test name
Test status
Simulation time 3204665083 ps
CPU time 28.7 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:38:22 PM PDT 24
Peak memory 198264 kb
Host smart-a031da65-a15d-4bf7-a451-d9728639173a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249835935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3249835935
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1611618190
Short name T424
Test name
Test status
Simulation time 945245024 ps
CPU time 0.92 seconds
Started Apr 04 03:37:59 PM PDT 24
Finished Apr 04 03:38:00 PM PDT 24
Peak memory 196712 kb
Host smart-ef4b8f6a-3758-415d-8e60-07ad7bd6fc5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611618190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1611618190
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1413743784
Short name T48
Test name
Test status
Simulation time 177656168 ps
CPU time 1.29 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 196912 kb
Host smart-1d93f450-4cb6-4e6c-9692-6b6228e5b3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413743784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1413743784
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.726682093
Short name T161
Test name
Test status
Simulation time 69864684 ps
CPU time 1.57 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196964 kb
Host smart-3df3c467-b79e-42ce-b63d-05969083b3a4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726682093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.726682093
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1694850205
Short name T596
Test name
Test status
Simulation time 82364695 ps
CPU time 0.95 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 195564 kb
Host smart-f1802490-e6fb-425f-9872-35e51977af9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694850205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1694850205
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2160428781
Short name T415
Test name
Test status
Simulation time 41441672 ps
CPU time 1 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196852 kb
Host smart-007404d0-7979-4905-8522-3de74536f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160428781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2160428781
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3279382620
Short name T425
Test name
Test status
Simulation time 32838229 ps
CPU time 0.83 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 197580 kb
Host smart-6559eb9c-3692-4e71-af5a-ab2ba81335f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279382620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3279382620
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2446653862
Short name T329
Test name
Test status
Simulation time 148955220 ps
CPU time 2.06 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 198192 kb
Host smart-2a7ff3f4-ce02-4089-a324-4ee19843cc22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446653862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2446653862
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4004359852
Short name T33
Test name
Test status
Simulation time 58840348 ps
CPU time 0.87 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 213792 kb
Host smart-8f5dd9e4-838d-4048-afa4-4af62f1f7b93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004359852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4004359852
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2668841478
Short name T185
Test name
Test status
Simulation time 71676081 ps
CPU time 1.27 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:54 PM PDT 24
Peak memory 197008 kb
Host smart-8fd0d294-8957-4abc-b8b1-d4d84d4f590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668841478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2668841478
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.968526668
Short name T316
Test name
Test status
Simulation time 43581026 ps
CPU time 0.96 seconds
Started Apr 04 03:37:53 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 195736 kb
Host smart-1ab4b4d3-8b93-43e3-92ab-759fb038a68d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968526668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.968526668
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1146574931
Short name T661
Test name
Test status
Simulation time 10297247143 ps
CPU time 38.64 seconds
Started Apr 04 03:37:50 PM PDT 24
Finished Apr 04 03:38:29 PM PDT 24
Peak memory 198348 kb
Host smart-034bad05-71b0-44a7-b884-b4db9e521500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146574931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1146574931
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2279140019
Short name T460
Test name
Test status
Simulation time 56581597 ps
CPU time 0.57 seconds
Started Apr 04 03:38:16 PM PDT 24
Finished Apr 04 03:38:16 PM PDT 24
Peak memory 194280 kb
Host smart-dd3ac697-23a4-41f6-9e25-7f31167cf607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279140019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2279140019
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1377020147
Short name T388
Test name
Test status
Simulation time 25693182 ps
CPU time 0.7 seconds
Started Apr 04 03:38:16 PM PDT 24
Finished Apr 04 03:38:17 PM PDT 24
Peak memory 194392 kb
Host smart-84963773-6070-4c24-9906-aa1135d78775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377020147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1377020147
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1415000478
Short name T136
Test name
Test status
Simulation time 794981456 ps
CPU time 14.86 seconds
Started Apr 04 03:38:21 PM PDT 24
Finished Apr 04 03:38:36 PM PDT 24
Peak memory 198156 kb
Host smart-afc3f275-30d7-41d2-ba14-afdd9207c5e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415000478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1415000478
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.811659577
Short name T356
Test name
Test status
Simulation time 263082004 ps
CPU time 0.78 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 196740 kb
Host smart-c3ad03e6-de9d-4741-ac8d-646d3a186b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811659577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.811659577
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3345684763
Short name T107
Test name
Test status
Simulation time 206322550 ps
CPU time 1.46 seconds
Started Apr 04 03:38:22 PM PDT 24
Finished Apr 04 03:38:24 PM PDT 24
Peak memory 196036 kb
Host smart-a2f33fcf-6c49-4ab6-9b37-be9b4d51dd24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345684763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3345684763
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3752927366
Short name T701
Test name
Test status
Simulation time 78294255 ps
CPU time 3.21 seconds
Started Apr 04 03:38:23 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 198244 kb
Host smart-7434d569-c8b5-495a-91c1-2828d6190b68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752927366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3752927366
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2345339699
Short name T631
Test name
Test status
Simulation time 102479514 ps
CPU time 1.83 seconds
Started Apr 04 03:38:21 PM PDT 24
Finished Apr 04 03:38:22 PM PDT 24
Peak memory 196352 kb
Host smart-155401cd-e397-4288-bea9-1c77f189ba71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345339699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2345339699
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.576805921
Short name T489
Test name
Test status
Simulation time 97980631 ps
CPU time 1.12 seconds
Started Apr 04 03:38:28 PM PDT 24
Finished Apr 04 03:38:30 PM PDT 24
Peak memory 196664 kb
Host smart-de923abe-7196-40db-a140-fb5872616790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576805921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.576805921
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3160016236
Short name T571
Test name
Test status
Simulation time 198237996 ps
CPU time 1.02 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 196980 kb
Host smart-dba25707-0a59-41f1-83a7-954c53499e0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160016236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3160016236
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3654365738
Short name T152
Test name
Test status
Simulation time 232891162 ps
CPU time 2.19 seconds
Started Apr 04 03:38:15 PM PDT 24
Finished Apr 04 03:38:17 PM PDT 24
Peak memory 198112 kb
Host smart-ae1b3aff-0b4f-4ddc-8b25-98bc63ad32a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654365738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3654365738
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3563324507
Short name T235
Test name
Test status
Simulation time 69313423 ps
CPU time 0.74 seconds
Started Apr 04 03:38:24 PM PDT 24
Finished Apr 04 03:38:25 PM PDT 24
Peak memory 196068 kb
Host smart-cdb7fbf1-f02d-4d93-b13c-5f031e19d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563324507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3563324507
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1559286520
Short name T241
Test name
Test status
Simulation time 79728727 ps
CPU time 0.8 seconds
Started Apr 04 03:38:18 PM PDT 24
Finished Apr 04 03:38:19 PM PDT 24
Peak memory 195336 kb
Host smart-5a927951-8763-464b-a2ab-c4d9c24a62e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559286520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1559286520
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.656649071
Short name T63
Test name
Test status
Simulation time 15013622371 ps
CPU time 144.85 seconds
Started Apr 04 03:38:20 PM PDT 24
Finished Apr 04 03:40:45 PM PDT 24
Peak memory 198376 kb
Host smart-f1dada26-a090-43d0-8f28-70ad15ada688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656649071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.656649071
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1409085830
Short name T658
Test name
Test status
Simulation time 307311594910 ps
CPU time 1526.02 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 04:03:52 PM PDT 24
Peak memory 198340 kb
Host smart-e8378bb3-8858-49ad-8c5b-d67bf0e0762a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1409085830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1409085830
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1416650866
Short name T498
Test name
Test status
Simulation time 26313129 ps
CPU time 0.6 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 194160 kb
Host smart-0b2470a0-0fa8-45ef-b14d-231b78d6009f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416650866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1416650866
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3086288383
Short name T692
Test name
Test status
Simulation time 16874886 ps
CPU time 0.67 seconds
Started Apr 04 03:38:23 PM PDT 24
Finished Apr 04 03:38:24 PM PDT 24
Peak memory 194372 kb
Host smart-96098082-9d4a-4b17-9d13-43f321883376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086288383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3086288383
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2232529829
Short name T603
Test name
Test status
Simulation time 5294031745 ps
CPU time 25.74 seconds
Started Apr 04 03:38:22 PM PDT 24
Finished Apr 04 03:38:48 PM PDT 24
Peak memory 197204 kb
Host smart-b6c69620-7e7f-4dcd-836f-e182390d77ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232529829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2232529829
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2419395430
Short name T427
Test name
Test status
Simulation time 64769644 ps
CPU time 0.81 seconds
Started Apr 04 03:38:29 PM PDT 24
Finished Apr 04 03:38:30 PM PDT 24
Peak memory 196184 kb
Host smart-875f2eb1-7dbc-4af4-8639-3c0c4858fb04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419395430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2419395430
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2721337011
Short name T557
Test name
Test status
Simulation time 60829500 ps
CPU time 1.15 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:27 PM PDT 24
Peak memory 195988 kb
Host smart-9697062e-18fe-4aca-b50d-b626653c655f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721337011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2721337011
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.17346644
Short name T193
Test name
Test status
Simulation time 153380956 ps
CPU time 3.09 seconds
Started Apr 04 03:38:23 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 198252 kb
Host smart-6f1e0fee-733c-43b1-8275-9d4b15bd38a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17346644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.gpio_intr_with_filter_rand_intr_event.17346644
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2144342251
Short name T660
Test name
Test status
Simulation time 607101437 ps
CPU time 2.88 seconds
Started Apr 04 03:38:22 PM PDT 24
Finished Apr 04 03:38:25 PM PDT 24
Peak memory 197416 kb
Host smart-22d522ba-5dac-4902-b09f-272c0865ce3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144342251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2144342251
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3711907324
Short name T222
Test name
Test status
Simulation time 94670157 ps
CPU time 1.15 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:19 PM PDT 24
Peak memory 196964 kb
Host smart-3c362f6f-78b0-4398-bfc6-541f11262250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711907324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3711907324
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.401856407
Short name T392
Test name
Test status
Simulation time 179935914 ps
CPU time 1.11 seconds
Started Apr 04 03:38:24 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 196772 kb
Host smart-8bee7120-ea03-4c8e-b3b9-dabe3acdcd60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401856407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.401856407
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1601637973
Short name T186
Test name
Test status
Simulation time 216570872 ps
CPU time 3.69 seconds
Started Apr 04 03:38:26 PM PDT 24
Finished Apr 04 03:38:30 PM PDT 24
Peak memory 198196 kb
Host smart-4c498817-6359-43a5-aa1f-5786e1169dcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601637973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1601637973
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.108034913
Short name T276
Test name
Test status
Simulation time 82466147 ps
CPU time 1.39 seconds
Started Apr 04 03:38:26 PM PDT 24
Finished Apr 04 03:38:28 PM PDT 24
Peak memory 195920 kb
Host smart-1781b9c3-858c-4130-ba77-bf252077af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108034913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.108034913
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2755562742
Short name T347
Test name
Test status
Simulation time 50024645 ps
CPU time 0.93 seconds
Started Apr 04 03:38:21 PM PDT 24
Finished Apr 04 03:38:22 PM PDT 24
Peak memory 196576 kb
Host smart-62846c9c-6e27-4ba3-9ebb-5d451f3ef516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755562742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2755562742
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1017074043
Short name T234
Test name
Test status
Simulation time 39271386597 ps
CPU time 85.84 seconds
Started Apr 04 03:38:19 PM PDT 24
Finished Apr 04 03:39:45 PM PDT 24
Peak memory 198312 kb
Host smart-568fac09-9f70-44cc-b455-cbae22e6dc13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017074043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1017074043
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1984830168
Short name T77
Test name
Test status
Simulation time 729100657595 ps
CPU time 1657.31 seconds
Started Apr 04 03:38:28 PM PDT 24
Finished Apr 04 04:06:06 PM PDT 24
Peak memory 198424 kb
Host smart-83f0e0fb-b428-4c45-ae2e-0850da8494f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1984830168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1984830168
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2631697764
Short name T358
Test name
Test status
Simulation time 26979160 ps
CPU time 0.54 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:32 PM PDT 24
Peak memory 194296 kb
Host smart-3d0546ca-4c4a-427d-94ff-d17f2094c072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631697764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2631697764
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4085334683
Short name T127
Test name
Test status
Simulation time 16677971 ps
CPU time 0.59 seconds
Started Apr 04 03:38:19 PM PDT 24
Finished Apr 04 03:38:20 PM PDT 24
Peak memory 194716 kb
Host smart-d0d40035-e3bf-4aab-9f9a-c56fdf81aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085334683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4085334683
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3279903602
Short name T667
Test name
Test status
Simulation time 910716580 ps
CPU time 10.1 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:42 PM PDT 24
Peak memory 197152 kb
Host smart-585f789c-d586-47e7-af46-71fce942eeba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279903602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3279903602
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2060898417
Short name T160
Test name
Test status
Simulation time 58004356 ps
CPU time 1.06 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 198072 kb
Host smart-72734cce-c5b5-48df-b85b-07f07f9d889a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060898417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2060898417
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.969761277
Short name T257
Test name
Test status
Simulation time 268538753 ps
CPU time 0.99 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:38:35 PM PDT 24
Peak memory 196976 kb
Host smart-5f1964d4-69a4-4a24-a6ba-b7b4e96107df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969761277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.969761277
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2689538098
Short name T118
Test name
Test status
Simulation time 126419368 ps
CPU time 2.6 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:36 PM PDT 24
Peak memory 198236 kb
Host smart-e659ba5d-149b-4f03-8559-3507e7e7ce29
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689538098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2689538098
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1340840794
Short name T693
Test name
Test status
Simulation time 1608894091 ps
CPU time 3.5 seconds
Started Apr 04 03:38:30 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 198200 kb
Host smart-7b408f17-ad62-4a6c-a59b-23d621a78155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340840794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1340840794
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2528512965
Short name T251
Test name
Test status
Simulation time 84715657 ps
CPU time 1.03 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:19 PM PDT 24
Peak memory 196968 kb
Host smart-c596e54f-c0de-4745-a8c0-aa102d7b6f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528512965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2528512965
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3056729004
Short name T578
Test name
Test status
Simulation time 64821891 ps
CPU time 0.86 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 196856 kb
Host smart-5ddde227-3031-4a3a-96f6-8b06601a08b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056729004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3056729004
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3574236677
Short name T272
Test name
Test status
Simulation time 103459020 ps
CPU time 1.38 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:33 PM PDT 24
Peak memory 198196 kb
Host smart-c5ce2f48-60dd-42a9-a4fa-379c6887cbd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574236677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3574236677
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2817015870
Short name T512
Test name
Test status
Simulation time 243240923 ps
CPU time 1.15 seconds
Started Apr 04 03:38:24 PM PDT 24
Finished Apr 04 03:38:25 PM PDT 24
Peak memory 195896 kb
Host smart-8733da32-acaf-4374-830e-9a7e68b7377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817015870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2817015870
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.979581868
Short name T339
Test name
Test status
Simulation time 292011417 ps
CPU time 1.3 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:27 PM PDT 24
Peak memory 197120 kb
Host smart-ec75267f-164b-491f-a49a-b1a658e3d545
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979581868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.979581868
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2958116177
Short name T481
Test name
Test status
Simulation time 4562075451 ps
CPU time 118.92 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:40:33 PM PDT 24
Peak memory 198240 kb
Host smart-117ce87c-72d3-4c3b-a9c6-8cc4db78e6f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958116177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2958116177
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3146997956
Short name T130
Test name
Test status
Simulation time 76624051 ps
CPU time 0.77 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:33 PM PDT 24
Peak memory 195524 kb
Host smart-d8f13f77-129d-4466-b9f3-e32722e0dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146997956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3146997956
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1893937095
Short name T140
Test name
Test status
Simulation time 1249861702 ps
CPU time 16.35 seconds
Started Apr 04 03:38:31 PM PDT 24
Finished Apr 04 03:38:48 PM PDT 24
Peak memory 198224 kb
Host smart-6ecdd1b2-5ae9-4a31-92b4-5e6e77a3efcb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893937095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1893937095
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.729470661
Short name T477
Test name
Test status
Simulation time 96907292 ps
CPU time 0.95 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:33 PM PDT 24
Peak memory 197524 kb
Host smart-0490b930-c749-48c2-88ac-6396edb927cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729470661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.729470661
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4088160378
Short name T615
Test name
Test status
Simulation time 40462431 ps
CPU time 0.8 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:35 PM PDT 24
Peak memory 195644 kb
Host smart-b2e02fbc-a6e2-4bdc-be39-71353741d92d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088160378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4088160378
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2650533587
Short name T523
Test name
Test status
Simulation time 120010590 ps
CPU time 2.36 seconds
Started Apr 04 03:38:36 PM PDT 24
Finished Apr 04 03:38:39 PM PDT 24
Peak memory 196720 kb
Host smart-73b805ed-08b1-4e68-bd1e-f420df3ebd36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650533587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2650533587
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.228313404
Short name T518
Test name
Test status
Simulation time 285649116 ps
CPU time 1.57 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:35 PM PDT 24
Peak memory 196956 kb
Host smart-b38fa3a8-4b1e-459c-9d45-f43d27de1bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228313404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
228313404
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3380814884
Short name T383
Test name
Test status
Simulation time 272492738 ps
CPU time 1.24 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:38:35 PM PDT 24
Peak memory 196108 kb
Host smart-d9c2e220-9c48-4b8a-b63a-e918fb11ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380814884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3380814884
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2609054847
Short name T323
Test name
Test status
Simulation time 24548915 ps
CPU time 0.86 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 196256 kb
Host smart-c23806ac-cacf-453b-8971-cf2445eaa9ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609054847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2609054847
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.407768980
Short name T301
Test name
Test status
Simulation time 285638369 ps
CPU time 4.62 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:38 PM PDT 24
Peak memory 197216 kb
Host smart-b5f6b1bf-48b8-496c-a28f-f57c3a8d7a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407768980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.407768980
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2964463637
Short name T601
Test name
Test status
Simulation time 51484444 ps
CPU time 1.3 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 196440 kb
Host smart-85305dc4-7b10-4729-b4e0-6072d21ca6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964463637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2964463637
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.909110990
Short name T287
Test name
Test status
Simulation time 377190539 ps
CPU time 1 seconds
Started Apr 04 03:38:31 PM PDT 24
Finished Apr 04 03:38:33 PM PDT 24
Peak memory 195904 kb
Host smart-b139a247-917c-41d9-af9f-d8e92564e12f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909110990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.909110990
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.321898601
Short name T325
Test name
Test status
Simulation time 6331454391 ps
CPU time 93.2 seconds
Started Apr 04 03:38:36 PM PDT 24
Finished Apr 04 03:40:10 PM PDT 24
Peak memory 198308 kb
Host smart-5a95d811-2a00-48cb-8d09-c0cdd8f4e698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321898601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.321898601
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.744225105
Short name T37
Test name
Test status
Simulation time 47851964 ps
CPU time 0.58 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 194008 kb
Host smart-21eec526-9cb1-404c-b559-de9041bb664c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744225105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.744225105
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1657722666
Short name T559
Test name
Test status
Simulation time 271161512 ps
CPU time 0.91 seconds
Started Apr 04 03:38:35 PM PDT 24
Finished Apr 04 03:38:36 PM PDT 24
Peak memory 196492 kb
Host smart-2de525ce-6fe9-4ea2-af8e-c0a978612486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657722666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1657722666
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2328420723
Short name T475
Test name
Test status
Simulation time 737973208 ps
CPU time 26.01 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 198148 kb
Host smart-0945c67c-54ba-4cb9-8520-c5a973055dcd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328420723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2328420723
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.695072732
Short name T680
Test name
Test status
Simulation time 268549655 ps
CPU time 0.99 seconds
Started Apr 04 03:38:49 PM PDT 24
Finished Apr 04 03:38:50 PM PDT 24
Peak memory 198092 kb
Host smart-ed2c9a7b-684a-47aa-94ce-26ad0d7b909f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695072732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.695072732
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3673091443
Short name T657
Test name
Test status
Simulation time 48772813 ps
CPU time 0.9 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:33 PM PDT 24
Peak memory 196940 kb
Host smart-2a38498f-ac33-43fe-a12f-c82309f9d37b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673091443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3673091443
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1236499101
Short name T363
Test name
Test status
Simulation time 311073775 ps
CPU time 2.45 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:38:36 PM PDT 24
Peak memory 198272 kb
Host smart-bbf4936a-690b-4473-9add-ab1f9f87e49c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236499101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1236499101
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3247228251
Short name T400
Test name
Test status
Simulation time 127341710 ps
CPU time 2.37 seconds
Started Apr 04 03:38:32 PM PDT 24
Finished Apr 04 03:38:35 PM PDT 24
Peak memory 197100 kb
Host smart-051c2a0d-e294-4aea-857c-a4580c63c7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247228251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3247228251
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1465363851
Short name T694
Test name
Test status
Simulation time 126766881 ps
CPU time 0.86 seconds
Started Apr 04 03:38:33 PM PDT 24
Finished Apr 04 03:38:34 PM PDT 24
Peak memory 196796 kb
Host smart-cc0a30e0-0166-4e7b-8211-3adf7ca68d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465363851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1465363851
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.91073481
Short name T352
Test name
Test status
Simulation time 119854511 ps
CPU time 1.15 seconds
Started Apr 04 03:38:34 PM PDT 24
Finished Apr 04 03:38:36 PM PDT 24
Peak memory 196284 kb
Host smart-490d1343-f02e-4abe-8947-20982528ff54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91073481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup_
pulldown.91073481
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.940730705
Short name T137
Test name
Test status
Simulation time 304964450 ps
CPU time 1.52 seconds
Started Apr 04 03:38:31 PM PDT 24
Finished Apr 04 03:38:32 PM PDT 24
Peak memory 198140 kb
Host smart-bc6b584d-5875-4874-ab7e-00184789011e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940730705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.940730705
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3381243230
Short name T290
Test name
Test status
Simulation time 140041701 ps
CPU time 1.13 seconds
Started Apr 04 03:38:31 PM PDT 24
Finished Apr 04 03:38:32 PM PDT 24
Peak memory 195920 kb
Host smart-04b38516-3a5e-4a5e-8e01-a2c8b18ebd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381243230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3381243230
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3921322407
Short name T295
Test name
Test status
Simulation time 1430988651 ps
CPU time 1.29 seconds
Started Apr 04 03:38:30 PM PDT 24
Finished Apr 04 03:38:31 PM PDT 24
Peak memory 197004 kb
Host smart-4a449c2c-4ac4-4b79-85c6-39cc24a0f546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921322407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3921322407
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2309846949
Short name T156
Test name
Test status
Simulation time 4444870847 ps
CPU time 64.91 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:39:55 PM PDT 24
Peak memory 198336 kb
Host smart-5e9425dd-32ea-4e0d-a1d7-db4d820ef855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309846949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2309846949
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2538300120
Short name T563
Test name
Test status
Simulation time 30766308 ps
CPU time 0.65 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 194332 kb
Host smart-8ed030a5-92b2-486f-99fa-d1811ccfd476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538300120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2538300120
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1370651873
Short name T204
Test name
Test status
Simulation time 111762670 ps
CPU time 0.72 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195508 kb
Host smart-b8bac5ec-2d82-42c4-9926-b50e131e26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370651873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1370651873
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.603600620
Short name T176
Test name
Test status
Simulation time 909189223 ps
CPU time 12.19 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:39:03 PM PDT 24
Peak memory 196868 kb
Host smart-7843872c-bfde-431c-8e89-30879c0adf08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603600620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.603600620
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1921851166
Short name T558
Test name
Test status
Simulation time 196801923 ps
CPU time 1.2 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 196584 kb
Host smart-648c173e-8178-41de-a586-23f4fd3df597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921851166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1921851166
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.332485864
Short name T208
Test name
Test status
Simulation time 150461414 ps
CPU time 0.85 seconds
Started Apr 04 03:38:55 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 196400 kb
Host smart-22eb2c79-0328-4d96-ac97-a1fcdab7c261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332485864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.332485864
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.847262381
Short name T231
Test name
Test status
Simulation time 203917185 ps
CPU time 2.24 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 198300 kb
Host smart-2ffde64d-5f9b-44b3-b71d-8a5fb776c8d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847262381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.847262381
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1014527261
Short name T72
Test name
Test status
Simulation time 69142574 ps
CPU time 1.99 seconds
Started Apr 04 03:38:48 PM PDT 24
Finished Apr 04 03:38:50 PM PDT 24
Peak memory 198232 kb
Host smart-f59ebd48-9a87-461f-b728-610137f40349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014527261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1014527261
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.939430168
Short name T640
Test name
Test status
Simulation time 24830964 ps
CPU time 0.69 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 196360 kb
Host smart-1c80a41d-9ca7-4665-a3d0-f73136bd5055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939430168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.939430168
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3140662089
Short name T188
Test name
Test status
Simulation time 59875279 ps
CPU time 1.15 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 197552 kb
Host smart-6f75c514-c7e2-4b89-9e95-bd9ef3ccb22d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140662089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3140662089
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2434773680
Short name T5
Test name
Test status
Simulation time 131571108 ps
CPU time 1.87 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 198136 kb
Host smart-08bb6f17-c3c9-4681-a4f1-e92c0a1e0074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434773680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2434773680
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2785221239
Short name T473
Test name
Test status
Simulation time 240663053 ps
CPU time 1.09 seconds
Started Apr 04 03:38:54 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 195760 kb
Host smart-48abb6f3-cdb7-44b9-9ca5-972508acced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785221239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2785221239
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.287860661
Short name T288
Test name
Test status
Simulation time 865642182 ps
CPU time 1.44 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 196976 kb
Host smart-107ca33d-8e88-4e84-b1ba-b773f0cd7c49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287860661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.287860661
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.137154919
Short name T401
Test name
Test status
Simulation time 7228228360 ps
CPU time 53.07 seconds
Started Apr 04 03:38:48 PM PDT 24
Finished Apr 04 03:39:41 PM PDT 24
Peak memory 198356 kb
Host smart-341252b5-9f08-41d5-a021-d46baa10064f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137154919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.137154919
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1422598994
Short name T639
Test name
Test status
Simulation time 24257414 ps
CPU time 0.56 seconds
Started Apr 04 03:38:54 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 194012 kb
Host smart-6f8d77d2-cd72-4ed6-81a1-99218152dd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422598994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1422598994
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3801837313
Short name T198
Test name
Test status
Simulation time 87342628 ps
CPU time 0.91 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195936 kb
Host smart-99086b8e-fdd7-4d8d-a6b7-51c2735177c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801837313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3801837313
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3333804006
Short name T575
Test name
Test status
Simulation time 1242294411 ps
CPU time 15.73 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:39:06 PM PDT 24
Peak memory 195740 kb
Host smart-4b858517-cd80-409b-a57d-1c278143df39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333804006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3333804006
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.314347064
Short name T407
Test name
Test status
Simulation time 51079892 ps
CPU time 0.81 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 196180 kb
Host smart-f88fa30b-4ecc-4f54-9235-4f28445fc41f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314347064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.314347064
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1784823707
Short name T436
Test name
Test status
Simulation time 108994263 ps
CPU time 0.97 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 195800 kb
Host smart-da44df7e-82b6-49a5-8d89-b4000c9d6278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784823707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1784823707
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2054340779
Short name T524
Test name
Test status
Simulation time 166408867 ps
CPU time 3.56 seconds
Started Apr 04 03:38:49 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 198116 kb
Host smart-ae27e846-17ed-41af-a8f0-d309623f5cf1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054340779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2054340779
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3923281273
Short name T461
Test name
Test status
Simulation time 72249264 ps
CPU time 1.73 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 196752 kb
Host smart-fc976683-22df-489c-b935-642d515d907c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923281273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3923281273
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.838269100
Short name T219
Test name
Test status
Simulation time 36469450 ps
CPU time 0.91 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 196724 kb
Host smart-e7eb11e8-81b9-415f-979d-e1986a00d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838269100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.838269100
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1917419305
Short name T470
Test name
Test status
Simulation time 35004237 ps
CPU time 0.96 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 196880 kb
Host smart-52ff4608-57db-47f9-9448-30a7a06f4d44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917419305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1917419305
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.721741450
Short name T367
Test name
Test status
Simulation time 84841746 ps
CPU time 1.72 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 198116 kb
Host smart-d4c26aaf-7a2f-4ef9-afc7-badc0028a9e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721741450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.721741450
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.264754254
Short name T342
Test name
Test status
Simulation time 117565564 ps
CPU time 0.68 seconds
Started Apr 04 03:38:49 PM PDT 24
Finished Apr 04 03:38:50 PM PDT 24
Peak memory 194324 kb
Host smart-fc5484c8-1888-40a8-bb6d-7d7ea084028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264754254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.264754254
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4144439977
Short name T178
Test name
Test status
Simulation time 63934356 ps
CPU time 1.06 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 195696 kb
Host smart-ad8e5d6e-7ff8-43a7-8bdf-d93a08b4c13b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144439977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4144439977
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2432131141
Short name T602
Test name
Test status
Simulation time 17181835217 ps
CPU time 125.94 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:40:57 PM PDT 24
Peak memory 198296 kb
Host smart-bf1a17a9-f298-4b5b-90aa-8214df20eda2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432131141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2432131141
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.950115090
Short name T61
Test name
Test status
Simulation time 47712565672 ps
CPU time 1091.99 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:57:04 PM PDT 24
Peak memory 198388 kb
Host smart-43e553f8-26ad-49c4-a955-7b840e66450e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=950115090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.950115090
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.630898777
Short name T248
Test name
Test status
Simulation time 42198045 ps
CPU time 0.59 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 194812 kb
Host smart-a86ff7a1-f25b-429b-9247-9c01950f10c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630898777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.630898777
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1198400597
Short name T110
Test name
Test status
Simulation time 94678386 ps
CPU time 0.8 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195440 kb
Host smart-ca0a8daf-fcde-4156-b48a-f1b38bb12599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198400597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1198400597
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.59801254
Short name T334
Test name
Test status
Simulation time 359234372 ps
CPU time 5 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:58 PM PDT 24
Peak memory 196848 kb
Host smart-e0dd163e-ca44-47b2-9d54-d910b0c8eb95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59801254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stress
.59801254
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.719381352
Short name T525
Test name
Test status
Simulation time 162662956 ps
CPU time 0.67 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 194596 kb
Host smart-6f97029c-9285-42b4-9235-5d357ef384e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719381352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.719381352
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1759516594
Short name T67
Test name
Test status
Simulation time 661750801 ps
CPU time 1.28 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 196028 kb
Host smart-2bce0469-1397-47c7-8c88-40f1ac8393c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759516594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1759516594
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.265771344
Short name T381
Test name
Test status
Simulation time 55945836 ps
CPU time 1.21 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 198236 kb
Host smart-b45854b0-d8ed-4655-af7e-ef380c40e08e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265771344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.265771344
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.863994110
Short name T398
Test name
Test status
Simulation time 48961607 ps
CPU time 1.64 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 197036 kb
Host smart-3967e1ac-71d8-479b-ae67-e898928759bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863994110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
863994110
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2053075501
Short name T509
Test name
Test status
Simulation time 63200395 ps
CPU time 1.29 seconds
Started Apr 04 03:38:55 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 197224 kb
Host smart-2bd83997-3a4d-4d84-b89b-c0637ee1b05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053075501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2053075501
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3941693678
Short name T691
Test name
Test status
Simulation time 29333469 ps
CPU time 0.69 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 194552 kb
Host smart-519f467b-3dbf-410a-8e06-0d6626a9fad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941693678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3941693678
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2042628262
Short name T495
Test name
Test status
Simulation time 5916817637 ps
CPU time 4.95 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 198160 kb
Host smart-2ffc23c9-6012-422a-803f-1d3243016f30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042628262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2042628262
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1243252804
Short name T695
Test name
Test status
Simulation time 475059184 ps
CPU time 1.26 seconds
Started Apr 04 03:38:49 PM PDT 24
Finished Apr 04 03:38:50 PM PDT 24
Peak memory 196836 kb
Host smart-7ff5d7b9-e422-40a7-9db1-1ede40a0232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243252804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1243252804
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2922507457
Short name T135
Test name
Test status
Simulation time 212817951 ps
CPU time 1.2 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 196048 kb
Host smart-5f395452-2184-4d9c-a965-93875a124871
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922507457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2922507457
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1483766958
Short name T583
Test name
Test status
Simulation time 32205212940 ps
CPU time 217.2 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:42:28 PM PDT 24
Peak memory 198252 kb
Host smart-c0255c4b-591e-4821-9a3c-860e08e786ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483766958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1483766958
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2077801772
Short name T60
Test name
Test status
Simulation time 205825742063 ps
CPU time 1997.93 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 04:12:10 PM PDT 24
Peak memory 198408 kb
Host smart-3d22ef63-ed27-4057-82af-50b7cd61fe8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2077801772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2077801772
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2446024586
Short name T16
Test name
Test status
Simulation time 15754634 ps
CPU time 0.58 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 194776 kb
Host smart-17cc7122-94bb-4fdf-857f-52342656d402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446024586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2446024586
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3619456649
Short name T652
Test name
Test status
Simulation time 153207908 ps
CPU time 0.88 seconds
Started Apr 04 03:38:50 PM PDT 24
Finished Apr 04 03:38:51 PM PDT 24
Peak memory 195624 kb
Host smart-6043069e-9f75-41fa-9e06-158afe185ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619456649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3619456649
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2643392443
Short name T282
Test name
Test status
Simulation time 1079931068 ps
CPU time 14.11 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 197144 kb
Host smart-cdbb18a3-4dad-49b1-b181-4e1077087566
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643392443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2643392443
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2015384977
Short name T22
Test name
Test status
Simulation time 83550642 ps
CPU time 1.06 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 198092 kb
Host smart-697a3adc-688e-4145-8280-e70196c0167c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015384977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2015384977
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2138445551
Short name T711
Test name
Test status
Simulation time 63683535 ps
CPU time 0.78 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 195496 kb
Host smart-3c0048aa-aaf4-4d8e-9d94-ac3f569e73e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138445551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2138445551
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.552153462
Short name T297
Test name
Test status
Simulation time 127614344 ps
CPU time 2.63 seconds
Started Apr 04 03:38:54 PM PDT 24
Finished Apr 04 03:38:56 PM PDT 24
Peak memory 198284 kb
Host smart-3efd8b34-0edf-4157-b241-d9356a1450f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552153462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.552153462
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.858568194
Short name T69
Test name
Test status
Simulation time 127959450 ps
CPU time 3.61 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 198108 kb
Host smart-2b50a49e-f838-4607-86ea-e030f568055b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858568194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
858568194
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1871346028
Short name T246
Test name
Test status
Simulation time 63261190 ps
CPU time 0.66 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195288 kb
Host smart-0605f586-d0f0-45e0-8f42-bf4faa233f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871346028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1871346028
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.545498483
Short name T567
Test name
Test status
Simulation time 125679800 ps
CPU time 1.4 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 197228 kb
Host smart-fb3e693f-877c-4025-b13a-846adf845aa2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545498483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.545498483
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3479715206
Short name T239
Test name
Test status
Simulation time 252835269 ps
CPU time 4.41 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:56 PM PDT 24
Peak memory 198176 kb
Host smart-1937d2a5-ae8b-40b6-a3ad-581bde461a9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479715206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3479715206
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3294104430
Short name T138
Test name
Test status
Simulation time 216721427 ps
CPU time 1.06 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:38:52 PM PDT 24
Peak memory 195992 kb
Host smart-b84cc0f9-a170-4862-999a-19895fddbe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294104430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3294104430
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.170679925
Short name T374
Test name
Test status
Simulation time 62603298 ps
CPU time 1.06 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 195636 kb
Host smart-54002b39-5b80-4b39-a630-36d8f9ae7ad1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170679925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.170679925
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1920869144
Short name T194
Test name
Test status
Simulation time 56343756607 ps
CPU time 75.61 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:40:08 PM PDT 24
Peak memory 198348 kb
Host smart-8f93a519-c50f-48fd-9aaa-7607a7bd9a50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920869144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1920869144
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3917552670
Short name T56
Test name
Test status
Simulation time 49784138057 ps
CPU time 885.16 seconds
Started Apr 04 03:38:51 PM PDT 24
Finished Apr 04 03:53:36 PM PDT 24
Peak memory 198408 kb
Host smart-c4feab73-d8d1-46a4-87a5-f250bdbcd057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3917552670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3917552670
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3511477295
Short name T573
Test name
Test status
Simulation time 13053349 ps
CPU time 0.57 seconds
Started Apr 04 03:38:55 PM PDT 24
Finished Apr 04 03:38:56 PM PDT 24
Peak memory 194044 kb
Host smart-662777f4-393d-4684-a236-0f5684029ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511477295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3511477295
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2737354058
Short name T373
Test name
Test status
Simulation time 114893474 ps
CPU time 0.73 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195392 kb
Host smart-d8733493-9ba5-4ac4-a161-505123e98988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737354058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2737354058
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3857436662
Short name T104
Test name
Test status
Simulation time 1023844636 ps
CPU time 3.79 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:55 PM PDT 24
Peak memory 196168 kb
Host smart-580be0dd-b8e8-4094-9d28-6c9108fa8ba3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857436662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3857436662
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1761820924
Short name T331
Test name
Test status
Simulation time 146072699 ps
CPU time 0.73 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 194940 kb
Host smart-208316b7-d5e3-49fb-8913-e0c36285dac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761820924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1761820924
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4038060586
Short name T544
Test name
Test status
Simulation time 58748585 ps
CPU time 0.76 seconds
Started Apr 04 03:39:01 PM PDT 24
Finished Apr 04 03:39:02 PM PDT 24
Peak memory 194568 kb
Host smart-8004fe70-000e-45ac-8701-35ee8d391ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038060586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4038060586
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3332120534
Short name T569
Test name
Test status
Simulation time 21968682 ps
CPU time 0.96 seconds
Started Apr 04 03:39:01 PM PDT 24
Finished Apr 04 03:39:02 PM PDT 24
Peak memory 196376 kb
Host smart-d9b85508-f496-4343-ac22-60c56cecd9eb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332120534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3332120534
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1284115689
Short name T708
Test name
Test status
Simulation time 238778696 ps
CPU time 2.48 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 198008 kb
Host smart-51813bb7-45cb-4140-a608-c1260c09fd6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284115689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1284115689
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1866175411
Short name T378
Test name
Test status
Simulation time 120450237 ps
CPU time 1.12 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 196740 kb
Host smart-2c9b477c-a7e7-4f4f-96f5-eb94385d3759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866175411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1866175411
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3760738397
Short name T151
Test name
Test status
Simulation time 287037583 ps
CPU time 1.51 seconds
Started Apr 04 03:39:01 PM PDT 24
Finished Apr 04 03:39:03 PM PDT 24
Peak memory 197180 kb
Host smart-1916808a-becd-4394-82f5-a1e336e82153
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760738397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3760738397
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1673992557
Short name T675
Test name
Test status
Simulation time 93153926 ps
CPU time 4.42 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:39:02 PM PDT 24
Peak memory 198168 kb
Host smart-4f4df7fa-d1f4-4b48-bcdf-03fe3ed53d9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673992557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1673992557
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3200533384
Short name T313
Test name
Test status
Simulation time 209836801 ps
CPU time 1.11 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:53 PM PDT 24
Peak memory 195816 kb
Host smart-f69a7962-2fba-4a27-bfe0-ff37ef99c642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200533384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3200533384
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3088184203
Short name T343
Test name
Test status
Simulation time 1475549606 ps
CPU time 1.39 seconds
Started Apr 04 03:38:55 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 196920 kb
Host smart-71ca0cf0-21c4-4f12-ae91-db8d20138690
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088184203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3088184203
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4172761816
Short name T468
Test name
Test status
Simulation time 7764309352 ps
CPU time 205.15 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:42:23 PM PDT 24
Peak memory 198384 kb
Host smart-d040f7ca-8a81-4327-9ed8-1c707b30f657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172761816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4172761816
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2645935547
Short name T537
Test name
Test status
Simulation time 91485653412 ps
CPU time 2005.07 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 04:12:21 PM PDT 24
Peak memory 198304 kb
Host smart-cea42b2f-f3e5-419b-a59d-902a086b623e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2645935547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2645935547
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3466485132
Short name T433
Test name
Test status
Simulation time 35813941 ps
CPU time 0.55 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:05 PM PDT 24
Peak memory 194072 kb
Host smart-ee954066-a022-46f0-a9cb-295aa2ceef7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466485132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3466485132
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4258162565
Short name T634
Test name
Test status
Simulation time 105417484 ps
CPU time 0.75 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 195388 kb
Host smart-b3583e29-873a-4589-b40c-86caf561030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258162565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4258162565
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1312230888
Short name T599
Test name
Test status
Simulation time 1106222844 ps
CPU time 17.11 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 196500 kb
Host smart-55c0545f-ff54-4c2d-aae0-9ca847e79a18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312230888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1312230888
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4083129663
Short name T584
Test name
Test status
Simulation time 108742747 ps
CPU time 0.81 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 196840 kb
Host smart-fb1194af-778c-4703-9be8-7eeaa43f2559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083129663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4083129663
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.169198208
Short name T405
Test name
Test status
Simulation time 412479601 ps
CPU time 1.47 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:55 PM PDT 24
Peak memory 196068 kb
Host smart-43ee91c7-ea04-4f43-8e25-da74c91435bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169198208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.169198208
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2491046694
Short name T566
Test name
Test status
Simulation time 332001032 ps
CPU time 3.48 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:58 PM PDT 24
Peak memory 198360 kb
Host smart-3ebd0566-d258-4790-9176-8e07c4e7c23e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491046694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2491046694
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3287609968
Short name T380
Test name
Test status
Simulation time 580222859 ps
CPU time 3.24 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:58 PM PDT 24
Peak memory 198268 kb
Host smart-12d4b004-348f-4e53-9f14-9042dc760cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287609968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3287609968
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1504956844
Short name T432
Test name
Test status
Simulation time 72700067 ps
CPU time 0.91 seconds
Started Apr 04 03:37:56 PM PDT 24
Finished Apr 04 03:37:57 PM PDT 24
Peak memory 196860 kb
Host smart-bd2f6a20-1c8c-4b7d-a3a2-30a023e66ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504956844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1504956844
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2815686239
Short name T673
Test name
Test status
Simulation time 197077614 ps
CPU time 1.22 seconds
Started Apr 04 03:37:55 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 196000 kb
Host smart-5ecfbdcd-5c31-4c77-b445-42476f2ed607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815686239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2815686239
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3158684955
Short name T485
Test name
Test status
Simulation time 457484981 ps
CPU time 2.33 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:03 PM PDT 24
Peak memory 198180 kb
Host smart-3a7659dc-0140-4749-ade8-3b8f0e96f58b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158684955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3158684955
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.419032133
Short name T45
Test name
Test status
Simulation time 31940116 ps
CPU time 0.8 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 213708 kb
Host smart-ae64491d-62e1-46d1-855b-ee13bfb0dd5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419032133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.419032133
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1466805334
Short name T252
Test name
Test status
Simulation time 70796971 ps
CPU time 1.06 seconds
Started Apr 04 03:37:52 PM PDT 24
Finished Apr 04 03:37:53 PM PDT 24
Peak memory 195920 kb
Host smart-fb5c9bb3-1a27-41c1-b890-82b142c00ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466805334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1466805334
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2537850663
Short name T576
Test name
Test status
Simulation time 72084250 ps
CPU time 1.21 seconds
Started Apr 04 03:37:54 PM PDT 24
Finished Apr 04 03:37:56 PM PDT 24
Peak memory 195696 kb
Host smart-9b45e8ac-d584-492c-804c-cdae63ecaa0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537850663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2537850663
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.381978526
Short name T205
Test name
Test status
Simulation time 16972389211 ps
CPU time 171.57 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:40:57 PM PDT 24
Peak memory 198320 kb
Host smart-6b7c54a5-4d7e-438c-a5e0-b4e67b91659d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381978526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.381978526
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.345947341
Short name T232
Test name
Test status
Simulation time 24470530 ps
CPU time 0.6 seconds
Started Apr 04 03:38:59 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 194080 kb
Host smart-3ae75b8d-2f67-47ba-a659-d5ca8ac318d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345947341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.345947341
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.482612127
Short name T169
Test name
Test status
Simulation time 69958784 ps
CPU time 0.96 seconds
Started Apr 04 03:38:57 PM PDT 24
Finished Apr 04 03:38:58 PM PDT 24
Peak memory 196408 kb
Host smart-6d77fb81-fb4b-48d4-b9b9-ef5b5706d66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482612127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.482612127
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4020577457
Short name T613
Test name
Test status
Simulation time 3604960988 ps
CPU time 21.54 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 197684 kb
Host smart-36a8b1db-1fc3-4200-a7e8-3adce2e33c42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020577457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4020577457
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1518404119
Short name T503
Test name
Test status
Simulation time 508596364 ps
CPU time 1 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 198076 kb
Host smart-866d747a-0a4c-4293-a401-beda3b923ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518404119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1518404119
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3131259898
Short name T428
Test name
Test status
Simulation time 45644737 ps
CPU time 1.22 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 196096 kb
Host smart-2a3efde8-992d-47d6-9859-6ce673a11dc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131259898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3131259898
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.805261019
Short name T533
Test name
Test status
Simulation time 117771979 ps
CPU time 2.69 seconds
Started Apr 04 03:38:59 PM PDT 24
Finished Apr 04 03:39:02 PM PDT 24
Peak memory 198344 kb
Host smart-2122f710-4a61-43a4-8aa4-3141006b2a7a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805261019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.805261019
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1937304077
Short name T519
Test name
Test status
Simulation time 517834425 ps
CPU time 2.63 seconds
Started Apr 04 03:38:57 PM PDT 24
Finished Apr 04 03:39:00 PM PDT 24
Peak memory 197084 kb
Host smart-4e3b1d7d-5e85-45c4-b8dd-ad36eb4b2a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937304077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1937304077
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1407626347
Short name T124
Test name
Test status
Simulation time 27988778 ps
CPU time 1 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 196036 kb
Host smart-d3d351d3-d401-459b-a045-f43ca09b685d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407626347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1407626347
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3486718763
Short name T697
Test name
Test status
Simulation time 119556593 ps
CPU time 1.31 seconds
Started Apr 04 03:38:57 PM PDT 24
Finished Apr 04 03:38:58 PM PDT 24
Peak memory 196752 kb
Host smart-5040280d-3b29-4e12-8e03-250591fbece2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486718763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3486718763
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2785380785
Short name T299
Test name
Test status
Simulation time 89328712 ps
CPU time 4.04 seconds
Started Apr 04 03:38:52 PM PDT 24
Finished Apr 04 03:38:56 PM PDT 24
Peak memory 198212 kb
Host smart-f46a27db-5e70-4514-b43e-837347358c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785380785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2785380785
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3145102356
Short name T527
Test name
Test status
Simulation time 32496593 ps
CPU time 1.1 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 196616 kb
Host smart-88bf66a4-f0c0-46e9-9754-8decf0cf39e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145102356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3145102356
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.366603514
Short name T386
Test name
Test status
Simulation time 61197924 ps
CPU time 0.99 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 196000 kb
Host smart-260eaf0e-c3e0-4b72-8b09-5be3768400c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366603514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.366603514
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1031705302
Short name T319
Test name
Test status
Simulation time 8729828858 ps
CPU time 58.02 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:39:56 PM PDT 24
Peak memory 198340 kb
Host smart-60c8d2c4-c942-49e1-aa3f-aa3640cfc3c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031705302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1031705302
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1402681394
Short name T64
Test name
Test status
Simulation time 18402010 ps
CPU time 0.61 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 194036 kb
Host smart-349e497b-b58b-43b0-82d5-9756a9bad7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402681394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1402681394
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1340135385
Short name T109
Test name
Test status
Simulation time 36732457 ps
CPU time 0.71 seconds
Started Apr 04 03:38:57 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 195548 kb
Host smart-d4df7c24-978b-4ccb-a0c9-2e408e75fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340135385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1340135385
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1296058586
Short name T539
Test name
Test status
Simulation time 2635596126 ps
CPU time 23 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:32 PM PDT 24
Peak memory 198228 kb
Host smart-29955572-0a27-4396-8e5f-b8cd71a7d007
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296058586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1296058586
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.531184855
Short name T230
Test name
Test status
Simulation time 163616475 ps
CPU time 0.8 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 194976 kb
Host smart-a8476eea-54ef-496a-9eda-11556e0f0aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531184855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.531184855
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2346763544
Short name T214
Test name
Test status
Simulation time 114898482 ps
CPU time 0.85 seconds
Started Apr 04 03:39:05 PM PDT 24
Finished Apr 04 03:39:06 PM PDT 24
Peak memory 196836 kb
Host smart-cd2aa204-cbea-4207-973c-281d1787910d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346763544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2346763544
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1069384196
Short name T332
Test name
Test status
Simulation time 140119493 ps
CPU time 2.68 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:12 PM PDT 24
Peak memory 198288 kb
Host smart-1606942a-9a10-4d78-8bd0-8fc68ed48a1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069384196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1069384196
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.306424837
Short name T202
Test name
Test status
Simulation time 334174497 ps
CPU time 1.82 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 196000 kb
Host smart-6966a34a-571a-4678-ae25-efefb68266db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306424837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
306424837
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2892341499
Short name T190
Test name
Test status
Simulation time 363888050 ps
CPU time 0.89 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:38:59 PM PDT 24
Peak memory 196224 kb
Host smart-cf64fbf1-90bf-492f-8070-710258a40daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892341499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2892341499
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2498734961
Short name T157
Test name
Test status
Simulation time 330894949 ps
CPU time 0.88 seconds
Started Apr 04 03:38:56 PM PDT 24
Finished Apr 04 03:38:57 PM PDT 24
Peak memory 196244 kb
Host smart-2118cb5b-7dd7-4012-910c-983a5904a364
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498734961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2498734961
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.571369424
Short name T649
Test name
Test status
Simulation time 58501838 ps
CPU time 2.67 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 198180 kb
Host smart-0576fac2-5998-4f16-8109-4f0fb9c1bd8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571369424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.571369424
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1056252495
Short name T546
Test name
Test status
Simulation time 40381416 ps
CPU time 1.25 seconds
Started Apr 04 03:38:58 PM PDT 24
Finished Apr 04 03:39:00 PM PDT 24
Peak memory 196632 kb
Host smart-6245d9cf-d091-409d-b298-11a97b392143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056252495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1056252495
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1987321650
Short name T612
Test name
Test status
Simulation time 122060331 ps
CPU time 0.95 seconds
Started Apr 04 03:38:53 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 196420 kb
Host smart-b68152d3-2286-4284-99ae-e71cc3e85870
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987321650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1987321650
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1105017269
Short name T330
Test name
Test status
Simulation time 53307660661 ps
CPU time 179.59 seconds
Started Apr 04 03:39:05 PM PDT 24
Finished Apr 04 03:42:04 PM PDT 24
Peak memory 198332 kb
Host smart-6a2c1593-877f-4f0e-85da-7c7a5bef8027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105017269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1105017269
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3930624668
Short name T36
Test name
Test status
Simulation time 29837495 ps
CPU time 0.54 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 194088 kb
Host smart-e02e6d5b-7bc6-4762-a7bb-e01a218ee104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930624668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3930624668
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1017601152
Short name T108
Test name
Test status
Simulation time 163602253 ps
CPU time 0.66 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 194396 kb
Host smart-326b9cde-dad1-4bc4-85f4-5bac1b4f96cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017601152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1017601152
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3094019389
Short name T371
Test name
Test status
Simulation time 287256032 ps
CPU time 14.72 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:25 PM PDT 24
Peak memory 198228 kb
Host smart-456f2f27-68c2-4806-8349-31cbd767aa69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094019389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3094019389
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2566978129
Short name T574
Test name
Test status
Simulation time 294467935 ps
CPU time 1.04 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 198276 kb
Host smart-5ab0a2f7-a6db-4c76-8c3d-9dcf0529de3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566978129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2566978129
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.371416951
Short name T668
Test name
Test status
Simulation time 71191472 ps
CPU time 1.22 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 197036 kb
Host smart-eb64c820-ba9c-4896-a977-7c4f204fd2a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371416951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.371416951
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3761200130
Short name T526
Test name
Test status
Simulation time 340055553 ps
CPU time 3.6 seconds
Started Apr 04 03:39:12 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 198208 kb
Host smart-5ccbb8d0-b8a5-4864-8770-2c946285976e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761200130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3761200130
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3511101477
Short name T253
Test name
Test status
Simulation time 212935674 ps
CPU time 2.25 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:12 PM PDT 24
Peak memory 196320 kb
Host smart-07373af5-7b5c-4683-b08f-5a96108d68e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511101477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3511101477
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2064678512
Short name T431
Test name
Test status
Simulation time 263366403 ps
CPU time 0.71 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 196252 kb
Host smart-bcf37aff-894f-413d-9ac1-c3e2375b44a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064678512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2064678512
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3605755215
Short name T662
Test name
Test status
Simulation time 50626459 ps
CPU time 1.18 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196044 kb
Host smart-7e806ad3-a58c-4ac5-a7ff-ecf96a93c5ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605755215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3605755215
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1105614801
Short name T177
Test name
Test status
Simulation time 377428603 ps
CPU time 5.72 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:15 PM PDT 24
Peak memory 198244 kb
Host smart-d0ab80e0-f2de-4910-9e51-abc5336cf063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105614801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1105614801
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3625568554
Short name T561
Test name
Test status
Simulation time 108054177 ps
CPU time 0.94 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 195720 kb
Host smart-9627f105-2b10-494a-8d08-8d391ba2af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625568554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3625568554
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1541293681
Short name T620
Test name
Test status
Simulation time 30918214 ps
CPU time 0.89 seconds
Started Apr 04 03:39:12 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 196596 kb
Host smart-6d86f900-780a-4104-8860-23965945d5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541293681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1541293681
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3180254728
Short name T167
Test name
Test status
Simulation time 28631853990 ps
CPU time 133.16 seconds
Started Apr 04 03:39:04 PM PDT 24
Finished Apr 04 03:41:18 PM PDT 24
Peak memory 198324 kb
Host smart-86c795f8-1f54-465f-aa56-47a679b94aeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180254728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3180254728
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.737913868
Short name T702
Test name
Test status
Simulation time 23827065 ps
CPU time 0.54 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 194028 kb
Host smart-534782a9-0103-4156-92f2-2b8ee6c76d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737913868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.737913868
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1983072209
Short name T494
Test name
Test status
Simulation time 74084717 ps
CPU time 0.67 seconds
Started Apr 04 03:39:12 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 194188 kb
Host smart-62cfc4ce-f05d-44bb-81b6-e4b542877eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983072209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1983072209
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2274682538
Short name T284
Test name
Test status
Simulation time 410885252 ps
CPU time 17.5 seconds
Started Apr 04 03:39:05 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 195736 kb
Host smart-eacad739-99c0-4170-85ed-62b47537e184
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274682538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2274682538
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.317720559
Short name T669
Test name
Test status
Simulation time 188693898 ps
CPU time 0.9 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196236 kb
Host smart-903d486a-e557-42aa-8ffc-0ad2060cba29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317720559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.317720559
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1235441744
Short name T365
Test name
Test status
Simulation time 17501754 ps
CPU time 0.69 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 194548 kb
Host smart-425f4d5d-be12-4d5c-b647-b902aa4e43fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235441744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1235441744
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1168469948
Short name T357
Test name
Test status
Simulation time 352081462 ps
CPU time 3.75 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 198212 kb
Host smart-5ac8a2eb-d4de-4a08-8567-21650a195837
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168469948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1168469948
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4073965278
Short name T280
Test name
Test status
Simulation time 58067955 ps
CPU time 0.87 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 196212 kb
Host smart-bc2cdb68-818a-4ceb-a0ee-9713d1fd861b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073965278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4073965278
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3970317888
Short name T52
Test name
Test status
Simulation time 29475049 ps
CPU time 0.74 seconds
Started Apr 04 03:39:08 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 196308 kb
Host smart-defee10c-29e2-471a-a58b-c3a7c7eba8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970317888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3970317888
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.468970170
Short name T327
Test name
Test status
Simulation time 1264753649 ps
CPU time 1.42 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 198380 kb
Host smart-ad674ab1-414b-4018-b94a-caf75b12b4cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468970170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.468970170
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1747163724
Short name T76
Test name
Test status
Simulation time 43759603 ps
CPU time 1.19 seconds
Started Apr 04 03:39:05 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 198220 kb
Host smart-6ee43f17-fe32-4d6f-8633-0483d4c98e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747163724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1747163724
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.937504470
Short name T269
Test name
Test status
Simulation time 68563446 ps
CPU time 0.75 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 195288 kb
Host smart-d43a0785-5af8-45dd-916c-e5027a8265f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937504470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.937504470
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1843571253
Short name T273
Test name
Test status
Simulation time 231685555 ps
CPU time 0.97 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196476 kb
Host smart-f080e79b-f097-428a-90d2-dd1c34aa000b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843571253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1843571253
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2502806319
Short name T6
Test name
Test status
Simulation time 12655142276 ps
CPU time 158.13 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:41:47 PM PDT 24
Peak memory 198352 kb
Host smart-16371dd2-3369-4d20-b50d-e7bac08b8c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502806319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2502806319
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.345093110
Short name T712
Test name
Test status
Simulation time 13390490 ps
CPU time 0.58 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 194100 kb
Host smart-f1a3bd73-a13f-4d8c-8292-060ca36b9c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345093110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.345093110
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2742882108
Short name T624
Test name
Test status
Simulation time 36120085 ps
CPU time 0.84 seconds
Started Apr 04 03:39:04 PM PDT 24
Finished Apr 04 03:39:05 PM PDT 24
Peak memory 195400 kb
Host smart-81c6019b-29f4-4fdd-bbcc-8f4ce804bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742882108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2742882108
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1053787547
Short name T397
Test name
Test status
Simulation time 1425399946 ps
CPU time 20.36 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:30 PM PDT 24
Peak memory 198196 kb
Host smart-ca885b0c-ab48-4758-928d-8dbfe3079b36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053787547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1053787547
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4280304289
Short name T13
Test name
Test status
Simulation time 154047310 ps
CPU time 1.02 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:12 PM PDT 24
Peak memory 196592 kb
Host smart-3123312b-868b-4a82-889b-8b87c40180b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280304289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4280304289
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1955550042
Short name T463
Test name
Test status
Simulation time 142430502 ps
CPU time 1.33 seconds
Started Apr 04 03:39:05 PM PDT 24
Finished Apr 04 03:39:06 PM PDT 24
Peak memory 197424 kb
Host smart-639cc086-9de9-40d2-9c03-dda0c7cdd95d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955550042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1955550042
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.4262891164
Short name T353
Test name
Test status
Simulation time 96332207 ps
CPU time 3.72 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:13 PM PDT 24
Peak memory 198340 kb
Host smart-4e9b695d-4eea-48d8-b65e-211ffadd020f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262891164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.4262891164
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2344012266
Short name T123
Test name
Test status
Simulation time 168695673 ps
CPU time 1.9 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:12 PM PDT 24
Peak memory 196904 kb
Host smart-1490a9eb-7158-49ca-bc4c-92db98f10006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344012266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2344012266
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.115120635
Short name T226
Test name
Test status
Simulation time 80052143 ps
CPU time 0.69 seconds
Started Apr 04 03:39:04 PM PDT 24
Finished Apr 04 03:39:04 PM PDT 24
Peak memory 194564 kb
Host smart-e535b62f-3e12-4d08-9462-0e9924376b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115120635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.115120635
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1316040414
Short name T435
Test name
Test status
Simulation time 114079585 ps
CPU time 1.06 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 196204 kb
Host smart-1ba2078e-ef73-4f20-bd14-c8383c974e3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316040414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1316040414
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.984937363
Short name T74
Test name
Test status
Simulation time 121492433 ps
CPU time 1.29 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 198128 kb
Host smart-9dbded60-1f29-4576-96eb-4f28c59617f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984937363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.984937363
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.67191880
Short name T409
Test name
Test status
Simulation time 49558161 ps
CPU time 0.95 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 196664 kb
Host smart-2614c390-c3d4-4d43-9db3-ca1baa84c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67191880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.67191880
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1363592158
Short name T215
Test name
Test status
Simulation time 129326864 ps
CPU time 1.17 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 196672 kb
Host smart-d704fdaa-2cb2-4bc8-8b41-dcffae203075
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363592158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1363592158
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3848634821
Short name T11
Test name
Test status
Simulation time 7741274930 ps
CPU time 27.42 seconds
Started Apr 04 03:39:08 PM PDT 24
Finished Apr 04 03:39:35 PM PDT 24
Peak memory 198344 kb
Host smart-52ff0441-4055-4bf6-a87f-984920542456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848634821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3848634821
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2207633735
Short name T55
Test name
Test status
Simulation time 99805434886 ps
CPU time 2339.9 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 04:18:08 PM PDT 24
Peak memory 198472 kb
Host smart-38fcd4fb-a615-4808-94dd-f6a3ac79cabe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2207633735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2207633735
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.749780165
Short name T228
Test name
Test status
Simulation time 11570870 ps
CPU time 0.57 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 194020 kb
Host smart-a0c5ea44-b804-47ea-81e9-7c66a2556d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749780165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.749780165
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3285348846
Short name T469
Test name
Test status
Simulation time 196896737 ps
CPU time 0.76 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:07 PM PDT 24
Peak memory 195564 kb
Host smart-55a98c76-00b2-44df-8e45-d17994ea230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285348846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3285348846
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.583286709
Short name T501
Test name
Test status
Simulation time 546442693 ps
CPU time 26.74 seconds
Started Apr 04 03:39:18 PM PDT 24
Finished Apr 04 03:39:44 PM PDT 24
Peak memory 198212 kb
Host smart-da59057f-bcdc-4759-bf02-e35cf58f1058
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583286709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.583286709
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.466025368
Short name T163
Test name
Test status
Simulation time 68377102 ps
CPU time 1.01 seconds
Started Apr 04 03:39:15 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 198040 kb
Host smart-04d2627f-4a3c-4250-b72f-3d1cc94ee7d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466025368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.466025368
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1212251464
Short name T238
Test name
Test status
Simulation time 31020818 ps
CPU time 0.8 seconds
Started Apr 04 03:39:04 PM PDT 24
Finished Apr 04 03:39:05 PM PDT 24
Peak memory 195760 kb
Host smart-0233e848-b3ed-4797-b5f7-1427c411b486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212251464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1212251464
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1581829492
Short name T413
Test name
Test status
Simulation time 208012355 ps
CPU time 2.18 seconds
Started Apr 04 03:39:16 PM PDT 24
Finished Apr 04 03:39:18 PM PDT 24
Peak memory 198252 kb
Host smart-3463332f-f83a-4250-b378-a89cb24e35a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581829492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1581829492
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3766280438
Short name T377
Test name
Test status
Simulation time 190950949 ps
CPU time 3.51 seconds
Started Apr 04 03:39:06 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 195980 kb
Host smart-c2a86298-2e84-4c15-9f69-8c2f73085152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766280438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3766280438
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2062669159
Short name T616
Test name
Test status
Simulation time 92181054 ps
CPU time 1.01 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196724 kb
Host smart-686829aa-ac16-4113-a3ec-b73e3629e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062669159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2062669159
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.5343852
Short name T150
Test name
Test status
Simulation time 32516417 ps
CPU time 0.81 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 195656 kb
Host smart-b163a503-f4aa-4610-9f47-d54926b44596
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5343852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_p
ulldown.5343852
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_smoke.3840903562
Short name T486
Test name
Test status
Simulation time 27444565 ps
CPU time 0.78 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 195472 kb
Host smart-64fb225c-1275-412b-93c1-25833935f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840903562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3840903562
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3748554759
Short name T707
Test name
Test status
Simulation time 63097471 ps
CPU time 1.06 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 195680 kb
Host smart-a22c6de1-a6ea-4b71-8ccb-c56db7857794
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748554759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3748554759
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2090681509
Short name T262
Test name
Test status
Simulation time 10109768721 ps
CPU time 75.72 seconds
Started Apr 04 03:39:16 PM PDT 24
Finished Apr 04 03:40:32 PM PDT 24
Peak memory 198340 kb
Host smart-a26a6e2f-7cbe-4bdb-8c86-6f852091f356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090681509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2090681509
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3219943530
Short name T292
Test name
Test status
Simulation time 37016034 ps
CPU time 0.59 seconds
Started Apr 04 03:39:08 PM PDT 24
Finished Apr 04 03:39:09 PM PDT 24
Peak memory 194220 kb
Host smart-6242b533-2df9-431c-95a2-a7415736df5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219943530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3219943530
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.311518501
Short name T224
Test name
Test status
Simulation time 89746921 ps
CPU time 0.91 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 195888 kb
Host smart-f0fc68f4-e68b-42c5-870e-7324ee341fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311518501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.311518501
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1125290123
Short name T548
Test name
Test status
Simulation time 1390375417 ps
CPU time 16.6 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:27 PM PDT 24
Peak memory 197044 kb
Host smart-3568a77c-e830-4b30-a232-290bef3330bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125290123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1125290123
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.270680452
Short name T440
Test name
Test status
Simulation time 138772106 ps
CPU time 0.91 seconds
Started Apr 04 03:39:07 PM PDT 24
Finished Apr 04 03:39:08 PM PDT 24
Peak memory 196932 kb
Host smart-71e418c6-86bc-4b35-b3d3-8fb6e20ff79b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270680452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.270680452
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.4004175365
Short name T66
Test name
Test status
Simulation time 201892291 ps
CPU time 1.09 seconds
Started Apr 04 03:39:12 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 196900 kb
Host smart-c7955bfe-5a14-4a6f-a0c2-65273c584ae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004175365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4004175365
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2641433936
Short name T155
Test name
Test status
Simulation time 381423749 ps
CPU time 2.67 seconds
Started Apr 04 03:39:14 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 198344 kb
Host smart-378b1d3d-47b8-4391-90d0-a3701bef5a31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641433936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2641433936
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1835596427
Short name T182
Test name
Test status
Simulation time 108317023 ps
CPU time 1.87 seconds
Started Apr 04 03:39:08 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196300 kb
Host smart-be038eff-f79c-4fdc-8bde-dd7f91583d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835596427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1835596427
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1189678185
Short name T132
Test name
Test status
Simulation time 77707827 ps
CPU time 0.95 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 196024 kb
Host smart-c9c52aea-e7c8-48bc-843c-26d2e7d16400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189678185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1189678185
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2398065575
Short name T289
Test name
Test status
Simulation time 17532661 ps
CPU time 0.63 seconds
Started Apr 04 03:39:15 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 195224 kb
Host smart-24e313d5-6026-4c20-8e29-ddd2d031e8aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398065575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2398065575
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3939283982
Short name T483
Test name
Test status
Simulation time 482633002 ps
CPU time 4.66 seconds
Started Apr 04 03:39:14 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 198248 kb
Host smart-b75b9dd2-8a91-489d-a924-5eb96a623924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939283982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3939283982
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2082931868
Short name T622
Test name
Test status
Simulation time 95365922 ps
CPU time 0.99 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 195740 kb
Host smart-d7e92868-48be-4790-af18-784c1fb4944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082931868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2082931868
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4291338748
Short name T439
Test name
Test status
Simulation time 36996643 ps
CPU time 1.16 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:11 PM PDT 24
Peak memory 196036 kb
Host smart-163880ed-fbfc-4a9e-8d6a-6b669df9b59f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291338748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4291338748
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1710922484
Short name T120
Test name
Test status
Simulation time 61614900299 ps
CPU time 193.87 seconds
Started Apr 04 03:39:15 PM PDT 24
Finished Apr 04 03:42:29 PM PDT 24
Peak memory 198360 kb
Host smart-82a179cb-1cd2-4db9-842e-bcd35df0e361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710922484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1710922484
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2948272635
Short name T242
Test name
Test status
Simulation time 118250489 ps
CPU time 0.58 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 195140 kb
Host smart-ea6cb791-bc19-4a02-8488-9f4770d52550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948272635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2948272635
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3351698932
Short name T218
Test name
Test status
Simulation time 189941643 ps
CPU time 0.58 seconds
Started Apr 04 03:39:15 PM PDT 24
Finished Apr 04 03:39:16 PM PDT 24
Peak memory 194100 kb
Host smart-eee65d2a-1c7f-425c-91a6-ecb4dfd10cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351698932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3351698932
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2315026796
Short name T119
Test name
Test status
Simulation time 1248699963 ps
CPU time 23.26 seconds
Started Apr 04 03:39:12 PM PDT 24
Finished Apr 04 03:39:36 PM PDT 24
Peak memory 197108 kb
Host smart-1a6dc3f6-d11b-4fb7-8c65-1bb8ce0fbf43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315026796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2315026796
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3655288380
Short name T212
Test name
Test status
Simulation time 264619676 ps
CPU time 1.06 seconds
Started Apr 04 03:39:26 PM PDT 24
Finished Apr 04 03:39:27 PM PDT 24
Peak memory 197896 kb
Host smart-63da2de0-f946-4d75-bc37-705f004b1e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655288380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3655288380
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1190289914
Short name T50
Test name
Test status
Simulation time 49828119 ps
CPU time 0.9 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 196848 kb
Host smart-35de8512-0090-4e76-808f-a14e08db0e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190289914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1190289914
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.545685796
Short name T344
Test name
Test status
Simulation time 101151030 ps
CPU time 1.99 seconds
Started Apr 04 03:39:14 PM PDT 24
Finished Apr 04 03:39:16 PM PDT 24
Peak memory 198260 kb
Host smart-ca0626b2-36d7-4edd-bc53-4e86d8a0f2f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545685796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.545685796
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4041782499
Short name T149
Test name
Test status
Simulation time 83777331 ps
CPU time 0.89 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 196340 kb
Host smart-78bcaa2d-0649-4ed8-868d-23d369c18e3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041782499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4041782499
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1298103597
Short name T203
Test name
Test status
Simulation time 53261671 ps
CPU time 0.77 seconds
Started Apr 04 03:39:09 PM PDT 24
Finished Apr 04 03:39:10 PM PDT 24
Peak memory 195532 kb
Host smart-fc0c2751-885e-4fd6-86a9-25c93675cbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298103597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1298103597
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1630822366
Short name T614
Test name
Test status
Simulation time 31470102 ps
CPU time 1.24 seconds
Started Apr 04 03:39:15 PM PDT 24
Finished Apr 04 03:39:17 PM PDT 24
Peak memory 198248 kb
Host smart-db449c70-379f-4888-bd0a-c0165e346a98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630822366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1630822366
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2170132590
Short name T324
Test name
Test status
Simulation time 2380582989 ps
CPU time 4.9 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 198212 kb
Host smart-fcc02475-17fa-4ee6-9db6-50bfa31c0731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170132590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2170132590
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3084926418
Short name T478
Test name
Test status
Simulation time 65634927 ps
CPU time 1.29 seconds
Started Apr 04 03:39:10 PM PDT 24
Finished Apr 04 03:39:12 PM PDT 24
Peak memory 198136 kb
Host smart-6c47b3aa-5831-4669-8333-1d6a318a9bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084926418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3084926418
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3160016576
Short name T534
Test name
Test status
Simulation time 34040053 ps
CPU time 1.15 seconds
Started Apr 04 03:39:11 PM PDT 24
Finished Apr 04 03:39:14 PM PDT 24
Peak memory 195680 kb
Host smart-bdd655a0-1f8a-4c82-ba63-ee24118677fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160016576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3160016576
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4184385318
Short name T306
Test name
Test status
Simulation time 43035868130 ps
CPU time 156.24 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:41:59 PM PDT 24
Peak memory 198276 kb
Host smart-7b2bafcc-8248-4b07-b19e-484667d06df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184385318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4184385318
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.122562309
Short name T507
Test name
Test status
Simulation time 118493474529 ps
CPU time 805.39 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:52:48 PM PDT 24
Peak memory 198396 kb
Host smart-fe9b9bdd-d89a-416f-a785-f9210d96c0fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=122562309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.122562309
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.4054432064
Short name T497
Test name
Test status
Simulation time 22125446 ps
CPU time 0.56 seconds
Started Apr 04 03:39:24 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 194028 kb
Host smart-eef9998c-603d-4450-bc45-a6f7d02436ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054432064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.4054432064
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2632019501
Short name T183
Test name
Test status
Simulation time 101707797 ps
CPU time 0.91 seconds
Started Apr 04 03:39:25 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 195988 kb
Host smart-938b3ff8-b936-44d9-ba9f-5895fbe5fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632019501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2632019501
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2137803018
Short name T625
Test name
Test status
Simulation time 605049223 ps
CPU time 20.32 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:42 PM PDT 24
Peak memory 197204 kb
Host smart-37de1027-45cd-4391-a14a-0a4ea00c49c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137803018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2137803018
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4124912984
Short name T516
Test name
Test status
Simulation time 52778138 ps
CPU time 0.78 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:20 PM PDT 24
Peak memory 196004 kb
Host smart-bc9be504-ce0d-46df-a466-33597ee62a16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124912984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4124912984
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1767294773
Short name T454
Test name
Test status
Simulation time 50859560 ps
CPU time 1.14 seconds
Started Apr 04 03:39:27 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 196132 kb
Host smart-28182fff-c76f-497d-b0b0-f4bd9226dec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767294773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1767294773
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3047362743
Short name T689
Test name
Test status
Simulation time 1101890178 ps
CPU time 3.71 seconds
Started Apr 04 03:39:20 PM PDT 24
Finished Apr 04 03:39:24 PM PDT 24
Peak memory 198292 kb
Host smart-31e76d89-f63d-4e60-81ab-038f86d8d53e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047362743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3047362743
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1948347533
Short name T70
Test name
Test status
Simulation time 145012150 ps
CPU time 1.06 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:20 PM PDT 24
Peak memory 195600 kb
Host smart-e3b19ab8-ee35-4fcb-9155-45a27908cd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948347533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1948347533
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1730948595
Short name T681
Test name
Test status
Simulation time 229727319 ps
CPU time 1.17 seconds
Started Apr 04 03:39:18 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 198260 kb
Host smart-977d968d-1250-4657-aff1-82b08b40907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730948595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1730948595
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2027073445
Short name T520
Test name
Test status
Simulation time 161969243 ps
CPU time 0.99 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 195988 kb
Host smart-6ce16d53-cde0-42e0-bf0e-3d0c8c6cac88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027073445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2027073445
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1558770329
Short name T148
Test name
Test status
Simulation time 181544583 ps
CPU time 3.42 seconds
Started Apr 04 03:39:29 PM PDT 24
Finished Apr 04 03:39:33 PM PDT 24
Peak memory 198136 kb
Host smart-03293fab-7748-4fbd-a782-00538674636f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558770329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1558770329
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4146917447
Short name T174
Test name
Test status
Simulation time 193950651 ps
CPU time 0.97 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:20 PM PDT 24
Peak memory 196492 kb
Host smart-802bfbbc-6227-4e84-b0b5-cfa2cb3c7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146917447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4146917447
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1423183430
Short name T535
Test name
Test status
Simulation time 41201789 ps
CPU time 0.9 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 195788 kb
Host smart-c250a077-b0c5-4397-904f-77eec5a41c37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423183430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1423183430
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3118608076
Short name T515
Test name
Test status
Simulation time 1582127098 ps
CPU time 52.05 seconds
Started Apr 04 03:39:20 PM PDT 24
Finished Apr 04 03:40:12 PM PDT 24
Peak memory 198264 kb
Host smart-139b1659-e42c-48be-8e8b-9dc7f0ebf0a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118608076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3118608076
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2116573639
Short name T29
Test name
Test status
Simulation time 146251699768 ps
CPU time 1500.39 seconds
Started Apr 04 03:39:26 PM PDT 24
Finished Apr 04 04:04:27 PM PDT 24
Peak memory 198292 kb
Host smart-a2213fa3-f84e-4179-884d-6a5b7ba9c64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2116573639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2116573639
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.802315085
Short name T326
Test name
Test status
Simulation time 18987323 ps
CPU time 0.54 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 193188 kb
Host smart-0b4ff103-e3ba-4f39-92e0-a68c56da53de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802315085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.802315085
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4116336097
Short name T547
Test name
Test status
Simulation time 15791419 ps
CPU time 0.61 seconds
Started Apr 04 03:39:27 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 194024 kb
Host smart-b7d24804-49df-4bf6-8bab-41553c08385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116336097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4116336097
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3946485164
Short name T336
Test name
Test status
Simulation time 2766046410 ps
CPU time 25.02 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:47 PM PDT 24
Peak memory 197084 kb
Host smart-4168d109-0c6e-4d44-9219-c8f26a2da792
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946485164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3946485164
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3438260502
Short name T24
Test name
Test status
Simulation time 245112393 ps
CPU time 0.83 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 196072 kb
Host smart-b60f976d-8c81-43f1-91f8-da9e75262708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438260502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3438260502
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2655643183
Short name T274
Test name
Test status
Simulation time 35771909 ps
CPU time 1.13 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:21 PM PDT 24
Peak memory 196280 kb
Host smart-0fc90e73-34ef-48e6-a257-b98c7f8a1af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655643183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2655643183
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3293228802
Short name T502
Test name
Test status
Simulation time 73633513 ps
CPU time 0.88 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 196392 kb
Host smart-42b3e6de-f72c-4270-91b9-c7bee4163d32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293228802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3293228802
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.939888070
Short name T164
Test name
Test status
Simulation time 486996096 ps
CPU time 3.46 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:29 PM PDT 24
Peak memory 197384 kb
Host smart-b18443db-df07-41c6-b826-29d03b646f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939888070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
939888070
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.54583696
Short name T665
Test name
Test status
Simulation time 262720472 ps
CPU time 1.24 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:22 PM PDT 24
Peak memory 197192 kb
Host smart-076c6a26-e7e5-4dd8-a253-f300db7be803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54583696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.54583696
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3908201661
Short name T643
Test name
Test status
Simulation time 136985347 ps
CPU time 0.92 seconds
Started Apr 04 03:39:24 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 196216 kb
Host smart-b3f0366a-e7d8-4280-abb1-b23dbf584406
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908201661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3908201661
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1041727931
Short name T259
Test name
Test status
Simulation time 39873519 ps
CPU time 2.02 seconds
Started Apr 04 03:39:25 PM PDT 24
Finished Apr 04 03:39:27 PM PDT 24
Peak memory 198120 kb
Host smart-0aa9997f-27ab-47c4-b762-50a30ecbd0c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041727931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1041727931
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1331631193
Short name T422
Test name
Test status
Simulation time 290359971 ps
CPU time 1.07 seconds
Started Apr 04 03:39:17 PM PDT 24
Finished Apr 04 03:39:18 PM PDT 24
Peak memory 196404 kb
Host smart-e3e7c3b4-600f-4229-89ca-9445a3d3b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331631193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1331631193
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2438453834
Short name T423
Test name
Test status
Simulation time 63004128 ps
CPU time 0.98 seconds
Started Apr 04 03:39:24 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 195912 kb
Host smart-89c78e15-983f-4f43-a819-d8cc511d864f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438453834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2438453834
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3225643688
Short name T8
Test name
Test status
Simulation time 7510639109 ps
CPU time 80.35 seconds
Started Apr 04 03:39:25 PM PDT 24
Finished Apr 04 03:40:46 PM PDT 24
Peak memory 198300 kb
Host smart-97927848-b7e9-4498-8ce6-49ec05bc2cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225643688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3225643688
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1080805191
Short name T58
Test name
Test status
Simulation time 211970359800 ps
CPU time 629.87 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:49:52 PM PDT 24
Peak memory 206584 kb
Host smart-e1f16941-bad6-4da3-9e38-0d27f0b3b826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1080805191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1080805191
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4281350553
Short name T623
Test name
Test status
Simulation time 17379549 ps
CPU time 0.59 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 194068 kb
Host smart-0dcfd70e-b530-46a8-9f68-452cc0dcf138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281350553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4281350553
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.516399552
Short name T364
Test name
Test status
Simulation time 16441754 ps
CPU time 0.66 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:02 PM PDT 24
Peak memory 194196 kb
Host smart-3d834036-4376-4849-8717-8946a26b8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516399552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.516399552
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2661828910
Short name T703
Test name
Test status
Simulation time 1672157456 ps
CPU time 13.64 seconds
Started Apr 04 03:38:02 PM PDT 24
Finished Apr 04 03:38:16 PM PDT 24
Peak memory 198220 kb
Host smart-65be0ea4-d5d2-4b0d-abd8-a1072f53e068
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661828910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2661828910
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2087227668
Short name T459
Test name
Test status
Simulation time 157750870 ps
CPU time 0.96 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 197156 kb
Host smart-cd8b7bd9-3639-41d9-9853-95e4c1e6a76b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087227668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2087227668
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2196060629
Short name T128
Test name
Test status
Simulation time 168722032 ps
CPU time 1.08 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 196848 kb
Host smart-330a4e84-7ff4-4241-a455-a18c6b775c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196060629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2196060629
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3380251172
Short name T467
Test name
Test status
Simulation time 80881084 ps
CPU time 1.78 seconds
Started Apr 04 03:38:02 PM PDT 24
Finished Apr 04 03:38:04 PM PDT 24
Peak memory 196972 kb
Host smart-c2d4db3d-d6c8-4a96-9392-5a7eef7a5df9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380251172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3380251172
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.958721638
Short name T540
Test name
Test status
Simulation time 152493483 ps
CPU time 3.42 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 196064 kb
Host smart-6ee11fbe-b09a-4e98-8693-a0d530cbb16c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958721638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.958721638
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1814069350
Short name T683
Test name
Test status
Simulation time 52816039 ps
CPU time 1.02 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:02 PM PDT 24
Peak memory 195544 kb
Host smart-5b6a2617-fb97-4f50-875b-1a718f3c4de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814069350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1814069350
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4122506654
Short name T318
Test name
Test status
Simulation time 55835314 ps
CPU time 1.19 seconds
Started Apr 04 03:38:03 PM PDT 24
Finished Apr 04 03:38:05 PM PDT 24
Peak memory 196708 kb
Host smart-7ec30f25-12ce-4650-ae1f-ffff6e63310b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122506654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4122506654
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.878581370
Short name T7
Test name
Test status
Simulation time 2223973111 ps
CPU time 6.26 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 198276 kb
Host smart-a05e3c3d-a66d-4998-aa5f-1ff8a47b0a6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878581370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.878581370
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3387634420
Short name T34
Test name
Test status
Simulation time 418267086 ps
CPU time 0.94 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 214920 kb
Host smart-f7bc0ff7-5eb0-44f1-b229-6b2a4c01151e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387634420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3387634420
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3466596501
Short name T549
Test name
Test status
Simulation time 128112448 ps
CPU time 1.03 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 197452 kb
Host smart-425ee79d-7938-4b6d-b5af-5acc8046b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466596501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3466596501
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3656720618
Short name T394
Test name
Test status
Simulation time 317457555 ps
CPU time 1.33 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 198204 kb
Host smart-4673e1dd-2fdc-4cb2-b470-60468bbf47d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656720618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3656720618
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.432466850
Short name T541
Test name
Test status
Simulation time 6013118792 ps
CPU time 22.58 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:31 PM PDT 24
Peak memory 198316 kb
Host smart-b4131333-2b7f-4a56-afc9-3bb0bcbfddc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432466850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.432466850
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2300807410
Short name T487
Test name
Test status
Simulation time 19862018 ps
CPU time 0.57 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:22 PM PDT 24
Peak memory 194272 kb
Host smart-ef6d93ae-96a1-4fcb-b891-b3b4e89ce21e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300807410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2300807410
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.680934347
Short name T597
Test name
Test status
Simulation time 139758443 ps
CPU time 0.87 seconds
Started Apr 04 03:39:27 PM PDT 24
Finished Apr 04 03:39:28 PM PDT 24
Peak memory 196676 kb
Host smart-f002539e-fbb0-447a-9062-402678db09e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680934347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.680934347
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3933344320
Short name T291
Test name
Test status
Simulation time 1261338526 ps
CPU time 9.1 seconds
Started Apr 04 03:39:18 PM PDT 24
Finished Apr 04 03:39:28 PM PDT 24
Peak memory 196868 kb
Host smart-3e580851-30a5-45dc-b40a-2300c6c9201d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933344320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3933344320
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.607619830
Short name T581
Test name
Test status
Simulation time 147266303 ps
CPU time 1.04 seconds
Started Apr 04 03:39:22 PM PDT 24
Finished Apr 04 03:39:25 PM PDT 24
Peak memory 196800 kb
Host smart-53227049-09ce-4485-9005-ff4ee61404ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607619830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.607619830
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.612500400
Short name T604
Test name
Test status
Simulation time 125716871 ps
CPU time 0.83 seconds
Started Apr 04 03:39:27 PM PDT 24
Finished Apr 04 03:39:28 PM PDT 24
Peak memory 195812 kb
Host smart-18c67a6a-b5bb-4631-bcc6-fe649ac89626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612500400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.612500400
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1894903473
Short name T441
Test name
Test status
Simulation time 131792044 ps
CPU time 3.68 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:27 PM PDT 24
Peak memory 196716 kb
Host smart-600d5552-ac54-4a63-b09e-5b55ae933f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894903473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1894903473
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1712178051
Short name T536
Test name
Test status
Simulation time 44960045 ps
CPU time 1.28 seconds
Started Apr 04 03:39:26 PM PDT 24
Finished Apr 04 03:39:28 PM PDT 24
Peak memory 195932 kb
Host smart-2bd3a9d8-9e45-4a19-aa34-3385569c9ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712178051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1712178051
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2271707398
Short name T500
Test name
Test status
Simulation time 121397643 ps
CPU time 1.12 seconds
Started Apr 04 03:39:18 PM PDT 24
Finished Apr 04 03:39:19 PM PDT 24
Peak memory 196960 kb
Host smart-1e2d8a1e-2bc0-41fb-a3ed-e7353f5fae45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271707398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2271707398
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2363070743
Short name T165
Test name
Test status
Simulation time 124903896 ps
CPU time 6.57 seconds
Started Apr 04 03:39:25 PM PDT 24
Finished Apr 04 03:39:32 PM PDT 24
Peak memory 198060 kb
Host smart-aeb5989c-c150-4ca8-ba8d-7f9c7a9bad94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363070743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2363070743
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3515905812
Short name T12
Test name
Test status
Simulation time 173584116 ps
CPU time 0.71 seconds
Started Apr 04 03:39:20 PM PDT 24
Finished Apr 04 03:39:21 PM PDT 24
Peak memory 194480 kb
Host smart-5782fe46-af61-4e96-800b-676b5b183848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515905812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3515905812
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.914018686
Short name T179
Test name
Test status
Simulation time 67808279 ps
CPU time 1.36 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:39:23 PM PDT 24
Peak memory 198224 kb
Host smart-80b0f419-0322-4e9e-83ac-3073a97f6049
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914018686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.914018686
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3238928155
Short name T134
Test name
Test status
Simulation time 12046552533 ps
CPU time 168.13 seconds
Started Apr 04 03:39:26 PM PDT 24
Finished Apr 04 03:42:14 PM PDT 24
Peak memory 198164 kb
Host smart-993e2837-8ec2-4ceb-ab48-9def93a6ac5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238928155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3238928155
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3157049659
Short name T659
Test name
Test status
Simulation time 22778985643 ps
CPU time 428.14 seconds
Started Apr 04 03:39:21 PM PDT 24
Finished Apr 04 03:46:29 PM PDT 24
Peak memory 198444 kb
Host smart-d3eac8cf-9636-47da-b302-e7a77d57fc8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3157049659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3157049659
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3959786570
Short name T375
Test name
Test status
Simulation time 39586230 ps
CPU time 0.56 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:39 PM PDT 24
Peak memory 194088 kb
Host smart-f5069995-308d-4ee2-a915-5fd5723ec598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959786570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3959786570
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2961712226
Short name T552
Test name
Test status
Simulation time 89608298 ps
CPU time 0.72 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:26 PM PDT 24
Peak memory 195256 kb
Host smart-13c84503-8ec9-4f28-93f6-725dac106b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961712226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2961712226
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.990597184
Short name T184
Test name
Test status
Simulation time 3059447333 ps
CPU time 25.36 seconds
Started Apr 04 03:39:37 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 197680 kb
Host smart-6b6ecb82-9d7c-4dcf-9651-63a37cca5c3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990597184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.990597184
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2863752900
Short name T588
Test name
Test status
Simulation time 69343846 ps
CPU time 0.74 seconds
Started Apr 04 03:39:39 PM PDT 24
Finished Apr 04 03:39:41 PM PDT 24
Peak memory 194980 kb
Host smart-e814d62d-e382-4d97-aad6-6b507f425e3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863752900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2863752900
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3502098513
Short name T677
Test name
Test status
Simulation time 82768108 ps
CPU time 1.16 seconds
Started Apr 04 03:39:20 PM PDT 24
Finished Apr 04 03:39:21 PM PDT 24
Peak memory 196384 kb
Host smart-51ab54e0-246c-4f2c-b992-f410f14fcd76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502098513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3502098513
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.818153562
Short name T564
Test name
Test status
Simulation time 86158856 ps
CPU time 3.38 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:42 PM PDT 24
Peak memory 198416 kb
Host smart-36ac929a-a5c6-491f-b81b-b369de00a782
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818153562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.818153562
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2565036924
Short name T416
Test name
Test status
Simulation time 111772471 ps
CPU time 2.68 seconds
Started Apr 04 03:39:40 PM PDT 24
Finished Apr 04 03:39:43 PM PDT 24
Peak memory 196720 kb
Host smart-5da4d939-5425-4458-8df5-f8bbb90fbf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565036924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2565036924
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2735428937
Short name T227
Test name
Test status
Simulation time 47310178 ps
CPU time 1.11 seconds
Started Apr 04 03:39:23 PM PDT 24
Finished Apr 04 03:39:25 PM PDT 24
Peak memory 196240 kb
Host smart-dd8f41aa-e005-4bf5-aaa5-c6beec4b29e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735428937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2735428937
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3602004542
Short name T376
Test name
Test status
Simulation time 117139356 ps
CPU time 1.19 seconds
Started Apr 04 03:39:20 PM PDT 24
Finished Apr 04 03:39:21 PM PDT 24
Peak memory 197052 kb
Host smart-80b62feb-07c7-44ee-a134-06fe18c854ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602004542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3602004542
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2941353302
Short name T268
Test name
Test status
Simulation time 81957788 ps
CPU time 1.22 seconds
Started Apr 04 03:39:39 PM PDT 24
Finished Apr 04 03:39:41 PM PDT 24
Peak memory 198228 kb
Host smart-ad7bb17c-ddb5-4137-bae8-f3a6bbd6f424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941353302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2941353302
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.213478368
Short name T455
Test name
Test status
Simulation time 112214293 ps
CPU time 0.94 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:20 PM PDT 24
Peak memory 195968 kb
Host smart-f532097f-6931-4073-94a4-e7edbce3484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213478368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.213478368
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3940438606
Short name T644
Test name
Test status
Simulation time 375508028 ps
CPU time 1.21 seconds
Started Apr 04 03:39:19 PM PDT 24
Finished Apr 04 03:39:20 PM PDT 24
Peak memory 195980 kb
Host smart-e3e0de27-caff-47f9-9550-521774d3ffca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940438606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3940438606
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2038404844
Short name T346
Test name
Test status
Simulation time 23054675296 ps
CPU time 153.59 seconds
Started Apr 04 03:39:37 PM PDT 24
Finished Apr 04 03:42:10 PM PDT 24
Peak memory 198224 kb
Host smart-bddceeca-95f4-467d-8e07-80eb194a904e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038404844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2038404844
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3199159717
Short name T626
Test name
Test status
Simulation time 14606793 ps
CPU time 0.57 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 194088 kb
Host smart-481d7b2e-d191-4e6d-b38f-0d5c6dae6cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199159717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3199159717
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3130575696
Short name T321
Test name
Test status
Simulation time 116917985 ps
CPU time 0.75 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:39 PM PDT 24
Peak memory 195380 kb
Host smart-fb8ee46b-d15b-4dbf-8a26-01d2581eea79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130575696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3130575696
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4291264490
Short name T293
Test name
Test status
Simulation time 122753143 ps
CPU time 6.31 seconds
Started Apr 04 03:39:37 PM PDT 24
Finished Apr 04 03:39:43 PM PDT 24
Peak memory 195740 kb
Host smart-754fe3a3-b33e-4ec0-8cec-896b371ca784
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291264490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4291264490
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1948410245
Short name T19
Test name
Test status
Simulation time 300497746 ps
CPU time 1.04 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 198108 kb
Host smart-807542b7-1edc-4ad3-a0f3-14621d6dc51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948410245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1948410245
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2271618450
Short name T192
Test name
Test status
Simulation time 150982899 ps
CPU time 1.14 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:39 PM PDT 24
Peak memory 196988 kb
Host smart-e6dec8b7-2bff-41f9-a1a2-a590fe19c672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271618450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2271618450
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3149283253
Short name T75
Test name
Test status
Simulation time 53070350 ps
CPU time 1.18 seconds
Started Apr 04 03:39:37 PM PDT 24
Finished Apr 04 03:39:38 PM PDT 24
Peak memory 197268 kb
Host smart-9b7ce38f-89ab-4341-8fbf-eb662a731a11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149283253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3149283253
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4284125027
Short name T320
Test name
Test status
Simulation time 528018552 ps
CPU time 2.52 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:41 PM PDT 24
Peak memory 197300 kb
Host smart-3e4e44c4-c231-46e7-b595-5e2ca60a34a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284125027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4284125027
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3348640111
Short name T636
Test name
Test status
Simulation time 75673073 ps
CPU time 1.23 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:40 PM PDT 24
Peak memory 198260 kb
Host smart-70cd2e64-3354-44c9-9920-602ace7e8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348640111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3348640111
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2795509741
Short name T443
Test name
Test status
Simulation time 31071339 ps
CPU time 1.13 seconds
Started Apr 04 03:39:38 PM PDT 24
Finished Apr 04 03:39:40 PM PDT 24
Peak memory 196028 kb
Host smart-012a29dd-5c4c-4167-87b1-acd1ad9ab743
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795509741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2795509741
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.291298963
Short name T210
Test name
Test status
Simulation time 935486419 ps
CPU time 3.76 seconds
Started Apr 04 03:39:39 PM PDT 24
Finished Apr 04 03:39:43 PM PDT 24
Peak memory 198224 kb
Host smart-9dedbe8e-5fe5-420d-9060-fe44b5a22a30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291298963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.291298963
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1738379217
Short name T591
Test name
Test status
Simulation time 40781385 ps
CPU time 1.2 seconds
Started Apr 04 03:39:39 PM PDT 24
Finished Apr 04 03:39:41 PM PDT 24
Peak memory 196800 kb
Host smart-022d390d-4318-4b23-ba4f-439e470ad05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738379217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1738379217
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2954951400
Short name T653
Test name
Test status
Simulation time 65018277 ps
CPU time 1.17 seconds
Started Apr 04 03:39:37 PM PDT 24
Finished Apr 04 03:39:38 PM PDT 24
Peak memory 196976 kb
Host smart-6a9b7038-60c6-4671-bf1a-61d13060bc56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954951400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2954951400
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2681494248
Short name T304
Test name
Test status
Simulation time 29286342121 ps
CPU time 87.58 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 03:41:23 PM PDT 24
Peak memory 198296 kb
Host smart-fa44ba85-42a7-45b1-97e6-f7c650820023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681494248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2681494248
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.794940009
Short name T255
Test name
Test status
Simulation time 29907451 ps
CPU time 0.62 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 194988 kb
Host smart-56b9ca24-1dae-4896-8f21-7013429f0c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794940009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.794940009
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3618995298
Short name T245
Test name
Test status
Simulation time 23248440 ps
CPU time 0.69 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 03:39:56 PM PDT 24
Peak memory 194316 kb
Host smart-5fa47b71-4667-49ec-aa38-7ffb21f0cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618995298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3618995298
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2743298294
Short name T158
Test name
Test status
Simulation time 1723300153 ps
CPU time 24.77 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:22 PM PDT 24
Peak memory 197152 kb
Host smart-533da627-e82d-44e0-a0fc-76dc5b684c5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743298294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2743298294
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2257125599
Short name T20
Test name
Test status
Simulation time 395129625 ps
CPU time 1.09 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 196632 kb
Host smart-f14e353b-1ac1-41ee-ae99-bacb40cb643d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257125599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2257125599
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1599849947
Short name T14
Test name
Test status
Simulation time 175421238 ps
CPU time 1.39 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196764 kb
Host smart-eccbc8e6-9468-46b5-b1e9-28230405d204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599849947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1599849947
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2763933619
Short name T505
Test name
Test status
Simulation time 276655465 ps
CPU time 2.93 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 198156 kb
Host smart-838c5ab1-4434-4c54-ab7c-6a2e71eb0af0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763933619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2763933619
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3293083474
Short name T511
Test name
Test status
Simulation time 144875654 ps
CPU time 3.04 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 197248 kb
Host smart-2f4d96ac-63da-4175-ba4e-9e92d5fd7e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293083474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3293083474
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.184684075
Short name T704
Test name
Test status
Simulation time 22280566 ps
CPU time 0.71 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195408 kb
Host smart-acc5b3ea-1193-499a-9598-9192a39c1f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184684075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.184684075
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2758050244
Short name T606
Test name
Test status
Simulation time 31333048 ps
CPU time 0.74 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 03:39:56 PM PDT 24
Peak memory 195640 kb
Host smart-e948eeec-d2ef-4c7d-84a5-52525da87d3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758050244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2758050244
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2131438625
Short name T490
Test name
Test status
Simulation time 1836605082 ps
CPU time 5.03 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 198192 kb
Host smart-27b4c28f-bf28-4284-802d-3aba353a8a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131438625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2131438625
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.200488805
Short name T49
Test name
Test status
Simulation time 77636410 ps
CPU time 1.21 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195648 kb
Host smart-be9c2af5-88c6-4dde-b728-193d1cb7edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200488805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.200488805
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.719740213
Short name T598
Test name
Test status
Simulation time 356820378 ps
CPU time 1.58 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 197140 kb
Host smart-67399336-3a7d-4450-b1bc-f51a1710cf64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719740213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.719740213
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2205007971
Short name T195
Test name
Test status
Simulation time 17026803 ps
CPU time 0.58 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:39:59 PM PDT 24
Peak memory 194100 kb
Host smart-588d53ce-b0dc-499a-990f-b89e33a7f50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205007971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2205007971
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3700329480
Short name T666
Test name
Test status
Simulation time 17777426 ps
CPU time 0.59 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 194784 kb
Host smart-db3109b2-e16e-4e86-b5ce-2961490b7681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700329480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3700329480
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1742551574
Short name T404
Test name
Test status
Simulation time 423026817 ps
CPU time 7.12 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 198144 kb
Host smart-f3004aae-8984-41f4-9b6c-0976e9535d97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742551574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1742551574
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1912525552
Short name T173
Test name
Test status
Simulation time 56967264 ps
CPU time 1.1 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 198236 kb
Host smart-c99edd5d-7c90-4336-ae76-7f04496b9bb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912525552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1912525552
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1761173064
Short name T129
Test name
Test status
Simulation time 39095526 ps
CPU time 1.15 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 196428 kb
Host smart-fb48a1f6-9f39-401d-b899-b2cb3d98e132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761173064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1761173064
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1156337719
Short name T594
Test name
Test status
Simulation time 78072071 ps
CPU time 3.24 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 198296 kb
Host smart-ac6ec025-a487-4d95-877f-346f29f6fde7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156337719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1156337719
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.500283205
Short name T25
Test name
Test status
Simulation time 387295079 ps
CPU time 2.51 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 197196 kb
Host smart-d2fbb26a-4976-4847-b5b1-23eed10b5d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500283205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
500283205
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2577916789
Short name T105
Test name
Test status
Simulation time 68421141 ps
CPU time 0.91 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 196008 kb
Host smart-b2833a25-c06c-4628-a06a-82153c819081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577916789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2577916789
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.266868842
Short name T47
Test name
Test status
Simulation time 153631272 ps
CPU time 1.2 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196828 kb
Host smart-bb500b0f-69e5-40e8-bbfe-02166064f6f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266868842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.266868842
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.303014637
Short name T112
Test name
Test status
Simulation time 211894173 ps
CPU time 5.04 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 198156 kb
Host smart-d6704f09-b0e2-4db5-b368-5abf0c1db858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303014637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.303014637
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.230295654
Short name T635
Test name
Test status
Simulation time 64013231 ps
CPU time 1.23 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 197280 kb
Host smart-84ce2293-5649-47a3-9500-4ddb5cf29f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230295654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.230295654
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4074779540
Short name T244
Test name
Test status
Simulation time 81658339 ps
CPU time 1.2 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:39:59 PM PDT 24
Peak memory 198152 kb
Host smart-6918a427-3b57-4e84-9af5-11eb92b4bc3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074779540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4074779540
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3480579289
Short name T528
Test name
Test status
Simulation time 4316269426 ps
CPU time 123.56 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:42:02 PM PDT 24
Peak memory 198320 kb
Host smart-3a369d70-2628-4b01-8761-9420841b4d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480579289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3480579289
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3005382442
Short name T341
Test name
Test status
Simulation time 14956760 ps
CPU time 0.57 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 194012 kb
Host smart-caab63cb-d53d-463e-9ab3-f707969f5c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005382442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3005382442
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.407102328
Short name T617
Test name
Test status
Simulation time 35338962 ps
CPU time 0.84 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196164 kb
Host smart-762de7fc-faa8-4379-b64f-70cf078508f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407102328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.407102328
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3433584248
Short name T488
Test name
Test status
Simulation time 2845699629 ps
CPU time 17.14 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 197228 kb
Host smart-326a5253-15a6-441e-b9fc-29e80fdd698c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433584248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3433584248
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3674074635
Short name T664
Test name
Test status
Simulation time 49175828 ps
CPU time 0.76 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 194844 kb
Host smart-8b76e877-f02e-46ab-bb8c-06210b1ce3f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674074635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3674074635
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2602165050
Short name T698
Test name
Test status
Simulation time 79531261 ps
CPU time 1.28 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 197412 kb
Host smart-4d204e2e-fee3-4652-a17a-4d6747eda26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602165050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2602165050
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3213156666
Short name T247
Test name
Test status
Simulation time 852393814 ps
CPU time 2.99 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 198348 kb
Host smart-93ce59dc-04f2-440b-aafe-143847bc1370
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213156666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3213156666
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1514250867
Short name T531
Test name
Test status
Simulation time 115847110 ps
CPU time 3.68 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 198204 kb
Host smart-cd1ad980-1281-48e7-a9bd-869787544d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514250867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1514250867
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2022516070
Short name T302
Test name
Test status
Simulation time 30646309 ps
CPU time 1.17 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 197308 kb
Host smart-8ca6e2ad-d99d-4866-bf55-88c5c6ba66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022516070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2022516070
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3670427665
Short name T62
Test name
Test status
Simulation time 52989357 ps
CPU time 0.82 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195796 kb
Host smart-b9c08cb4-3b75-44c4-9893-6acf8497cd06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670427665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3670427665
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3286038671
Short name T10
Test name
Test status
Simulation time 2173843717 ps
CPU time 6.02 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:06 PM PDT 24
Peak memory 198220 kb
Host smart-6ee42db7-047f-4721-9c6e-d779f3bc8f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286038671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3286038671
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1917733581
Short name T630
Test name
Test status
Simulation time 173469517 ps
CPU time 1.08 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 195904 kb
Host smart-e5064cfc-6fba-4488-88a1-247e6c2f0f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917733581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1917733581
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.731600338
Short name T390
Test name
Test status
Simulation time 66439933 ps
CPU time 1.34 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 196928 kb
Host smart-152d1749-66fa-41f6-90eb-dc032ecc5eb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731600338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.731600338
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2994070234
Short name T589
Test name
Test status
Simulation time 24888037133 ps
CPU time 96.84 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:41:34 PM PDT 24
Peak memory 198380 kb
Host smart-076a3e91-7977-4b83-a867-01ed684a8124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994070234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2994070234
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2229203259
Short name T699
Test name
Test status
Simulation time 71355869249 ps
CPU time 1852.95 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 04:10:52 PM PDT 24
Peak memory 198420 kb
Host smart-9e3556cf-598a-41c2-98d2-64914ac09e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2229203259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2229203259
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2708789901
Short name T446
Test name
Test status
Simulation time 37018828 ps
CPU time 0.58 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 194308 kb
Host smart-b8a628b5-63c1-4760-ade7-9e901cf85da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708789901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2708789901
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3248567080
Short name T426
Test name
Test status
Simulation time 46602445 ps
CPU time 0.95 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 196724 kb
Host smart-06bb4569-7e57-40e8-92f7-7918276256bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248567080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3248567080
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2138492475
Short name T556
Test name
Test status
Simulation time 164001895 ps
CPU time 5.61 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 195756 kb
Host smart-bc7e49af-6b31-476a-a04a-0fdb1629c58b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138492475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2138492475
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3425924999
Short name T389
Test name
Test status
Simulation time 383952207 ps
CPU time 1.11 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 03:39:57 PM PDT 24
Peak memory 198096 kb
Host smart-4bbf729b-f79f-432a-87c6-b5f920c8199d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425924999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3425924999
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2966871968
Short name T199
Test name
Test status
Simulation time 193936668 ps
CPU time 1.02 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 03:39:56 PM PDT 24
Peak memory 196924 kb
Host smart-4ab160a9-2282-4169-b058-a2ad5acc99b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966871968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2966871968
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3407358471
Short name T600
Test name
Test status
Simulation time 115841806 ps
CPU time 2.37 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196696 kb
Host smart-e74d1eef-cda6-4e74-95d9-3d80cd7a351d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407358471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3407358471
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2451983241
Short name T23
Test name
Test status
Simulation time 186405949 ps
CPU time 3.04 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195964 kb
Host smart-ece80b8c-3f8a-4ff4-9f81-d8f4c3532cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451983241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2451983241
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1539230524
Short name T370
Test name
Test status
Simulation time 123810620 ps
CPU time 1.3 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 198204 kb
Host smart-abdb4938-2331-48f0-b900-e0662db6b6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539230524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1539230524
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3149387390
Short name T476
Test name
Test status
Simulation time 117807141 ps
CPU time 1.18 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 197584 kb
Host smart-080808e8-c15a-4d9a-a688-45a1df1482ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149387390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3149387390
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.796592569
Short name T278
Test name
Test status
Simulation time 716835555 ps
CPU time 1.27 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:59 PM PDT 24
Peak memory 198016 kb
Host smart-3383005a-39f4-465e-8072-e30823532e7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796592569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.796592569
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3906638
Short name T522
Test name
Test status
Simulation time 49294022 ps
CPU time 1.3 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:39:59 PM PDT 24
Peak memory 198212 kb
Host smart-7153b2c5-4e7d-4809-a359-ba33758d03ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3906638
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.4263324286
Short name T15
Test name
Test status
Simulation time 172490371 ps
CPU time 1.23 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 198096 kb
Host smart-247476a6-98fa-4d53-b7f4-57e79ebbd990
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263324286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.4263324286
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.936423729
Short name T285
Test name
Test status
Simulation time 11277201792 ps
CPU time 39.4 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:41 PM PDT 24
Peak memory 198348 kb
Host smart-b756715c-fc12-44d3-b16a-c09d96d2b09e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936423729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.936423729
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1511930967
Short name T103
Test name
Test status
Simulation time 68276253149 ps
CPU time 1853.59 seconds
Started Apr 04 03:39:55 PM PDT 24
Finished Apr 04 04:10:49 PM PDT 24
Peak memory 198296 kb
Host smart-ae31c27e-eba4-4e5d-8586-14693e9e825b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1511930967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1511930967
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1299271408
Short name T360
Test name
Test status
Simulation time 15268627 ps
CPU time 0.58 seconds
Started Apr 04 03:39:56 PM PDT 24
Finished Apr 04 03:39:58 PM PDT 24
Peak memory 194096 kb
Host smart-b13e998c-285f-4979-8b40-b6c063d21440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299271408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1299271408
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4170183885
Short name T582
Test name
Test status
Simulation time 363201783 ps
CPU time 0.92 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196816 kb
Host smart-ce34e640-659f-44d9-8e8a-8eb9ce1f02e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170183885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4170183885
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.513046215
Short name T508
Test name
Test status
Simulation time 1118946915 ps
CPU time 4.31 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 195720 kb
Host smart-872f1852-a731-4065-8ad4-d994d5421c15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513046215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.513046215
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1943153992
Short name T456
Test name
Test status
Simulation time 232559582 ps
CPU time 0.89 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 197396 kb
Host smart-6db63bf1-4a5e-4e2d-8cf9-80c95b073880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943153992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1943153992
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.21666812
Short name T491
Test name
Test status
Simulation time 203070975 ps
CPU time 0.97 seconds
Started Apr 04 03:40:00 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196340 kb
Host smart-245a6932-920c-44d9-80bc-70c74672374f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.21666812
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1410066481
Short name T555
Test name
Test status
Simulation time 93665773 ps
CPU time 3.42 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 196744 kb
Host smart-2fa3b0a7-b159-451f-a028-fabaefac3bb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410066481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1410066481
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3634660566
Short name T258
Test name
Test status
Simulation time 239452577 ps
CPU time 1.7 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 196068 kb
Host smart-c3b7934b-d96e-401c-a62b-0bbbee7e85a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634660566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3634660566
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3606935366
Short name T307
Test name
Test status
Simulation time 275561832 ps
CPU time 1.4 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 196720 kb
Host smart-030bf8cd-f85f-4ebb-8f40-5bdbd0090d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606935366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3606935366
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2563039054
Short name T142
Test name
Test status
Simulation time 63971526 ps
CPU time 0.96 seconds
Started Apr 04 03:40:00 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196236 kb
Host smart-a477621d-b374-4b19-afe7-a672c035d2eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563039054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2563039054
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3177284487
Short name T250
Test name
Test status
Simulation time 459852041 ps
CPU time 3.82 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:07 PM PDT 24
Peak memory 198224 kb
Host smart-a0dd973d-de31-4684-984b-35c14cec1435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177284487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3177284487
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1631359817
Short name T349
Test name
Test status
Simulation time 42572279 ps
CPU time 1.24 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 196484 kb
Host smart-49977b93-e8ee-4222-94cf-6f485f965278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631359817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1631359817
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1047547374
Short name T562
Test name
Test status
Simulation time 192374968 ps
CPU time 1.14 seconds
Started Apr 04 03:39:57 PM PDT 24
Finished Apr 04 03:40:00 PM PDT 24
Peak memory 195848 kb
Host smart-6e5158f2-fd17-4923-a0b1-9eb7598b7334
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047547374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1047547374
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.4073883705
Short name T309
Test name
Test status
Simulation time 4846160287 ps
CPU time 72.8 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:41:11 PM PDT 24
Peak memory 198452 kb
Host smart-2715804c-de30-4e69-8492-5c169d83ee79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073883705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.4073883705
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1463631968
Short name T629
Test name
Test status
Simulation time 172491840562 ps
CPU time 1030.92 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:57:13 PM PDT 24
Peak memory 198368 kb
Host smart-869def3b-1bf3-4831-ae9e-8f3c053eaf5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1463631968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1463631968
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1169472765
Short name T362
Test name
Test status
Simulation time 38702904 ps
CPU time 0.56 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 194072 kb
Host smart-073b8ccc-7f87-4fe6-a0f5-c364fb8042c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169472765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1169472765
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3032084600
Short name T311
Test name
Test status
Simulation time 123485754 ps
CPU time 0.76 seconds
Started Apr 04 03:40:00 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195480 kb
Host smart-5a0f96de-e638-4c87-8130-2f30d7815d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032084600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3032084600
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2273755860
Short name T451
Test name
Test status
Simulation time 831721537 ps
CPU time 17.27 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 195724 kb
Host smart-2f5353ca-d0e0-41e8-91be-7b870ceeeeef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273755860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2273755860
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3069537032
Short name T146
Test name
Test status
Simulation time 78057971 ps
CPU time 0.77 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 196716 kb
Host smart-b4dd80a3-6a9a-4dd3-b8ab-200c5a879f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069537032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3069537032
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3979008516
Short name T355
Test name
Test status
Simulation time 159832103 ps
CPU time 0.99 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 196264 kb
Host smart-40c66bd6-3f72-4542-8fb7-acee2c05d0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979008516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3979008516
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.987341417
Short name T671
Test name
Test status
Simulation time 191919775 ps
CPU time 2.05 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 198364 kb
Host smart-7fee6030-d2f3-46fe-a4a6-30e55e89919c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987341417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.987341417
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1876154222
Short name T170
Test name
Test status
Simulation time 47230895 ps
CPU time 1.22 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 196948 kb
Host smart-daaf0e65-0d53-4168-a884-2b751d61a346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876154222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1876154222
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3449080726
Short name T593
Test name
Test status
Simulation time 58419069 ps
CPU time 1.13 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 196284 kb
Host smart-a52e8c9b-3d92-4ba9-854b-e682a233f9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449080726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3449080726
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2275123289
Short name T260
Test name
Test status
Simulation time 48506146 ps
CPU time 1.2 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 196240 kb
Host smart-14df2848-da7e-4165-84ad-8627599ead76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275123289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2275123289
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.337145573
Short name T687
Test name
Test status
Simulation time 114411658 ps
CPU time 5.59 seconds
Started Apr 04 03:39:59 PM PDT 24
Finished Apr 04 03:40:06 PM PDT 24
Peak memory 198220 kb
Host smart-e55bdba1-bc5e-433f-8a9a-0999a7880c3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337145573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.337145573
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.4065119695
Short name T619
Test name
Test status
Simulation time 127360363 ps
CPU time 1.16 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 196076 kb
Host smart-b831757a-ae12-4d9d-b87f-e0df68c0027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065119695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.4065119695
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1699336646
Short name T646
Test name
Test status
Simulation time 98212899 ps
CPU time 1.45 seconds
Started Apr 04 03:40:04 PM PDT 24
Finished Apr 04 03:40:06 PM PDT 24
Peak memory 198208 kb
Host smart-33b19943-0562-4d3d-ad63-08e6806a68ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699336646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1699336646
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2942000617
Short name T410
Test name
Test status
Simulation time 8967737069 ps
CPU time 124.1 seconds
Started Apr 04 03:39:58 PM PDT 24
Finished Apr 04 03:42:03 PM PDT 24
Peak memory 198304 kb
Host smart-e7a97fc2-8126-4167-8980-ba5608f9f3a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942000617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2942000617
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2782960363
Short name T471
Test name
Test status
Simulation time 43351925 ps
CPU time 0.59 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 194796 kb
Host smart-5e481c3d-708f-4f91-97a9-f6380a277385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782960363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2782960363
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1504568093
Short name T263
Test name
Test status
Simulation time 27826805 ps
CPU time 0.81 seconds
Started Apr 04 03:40:00 PM PDT 24
Finished Apr 04 03:40:01 PM PDT 24
Peak memory 195392 kb
Host smart-b5c6d5c7-d449-4bbd-ba60-3a308e10418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504568093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1504568093
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.115439841
Short name T26
Test name
Test status
Simulation time 478261740 ps
CPU time 23.11 seconds
Started Apr 04 03:40:09 PM PDT 24
Finished Apr 04 03:40:32 PM PDT 24
Peak memory 197056 kb
Host smart-50ee89a4-c857-4aeb-acb2-0d953cb26bef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115439841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.115439841
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3413998466
Short name T217
Test name
Test status
Simulation time 127483780 ps
CPU time 0.72 seconds
Started Apr 04 03:40:03 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 194768 kb
Host smart-8dd4c19d-dfe1-4f75-89bc-234ab8ac552c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413998466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3413998466
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1118473546
Short name T387
Test name
Test status
Simulation time 540156957 ps
CPU time 1.56 seconds
Started Apr 04 03:40:00 PM PDT 24
Finished Apr 04 03:40:02 PM PDT 24
Peak memory 197284 kb
Host smart-74871dd8-16bb-434f-a609-983d9b24e1ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118473546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1118473546
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1284606240
Short name T442
Test name
Test status
Simulation time 172086885 ps
CPU time 2.06 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 198292 kb
Host smart-59a73237-12e5-412b-b981-a0b831cf5111
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284606240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1284606240
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1176419518
Short name T412
Test name
Test status
Simulation time 120081025 ps
CPU time 1.54 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 196372 kb
Host smart-571b51a2-3799-4f59-8a06-33cb0aebadbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176419518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1176419518
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3668699242
Short name T514
Test name
Test status
Simulation time 187584408 ps
CPU time 0.94 seconds
Started Apr 04 03:40:04 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 196216 kb
Host smart-9e05df7c-843b-4804-8fc0-0fe8477bc8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668699242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3668699242
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3003769251
Short name T651
Test name
Test status
Simulation time 86422921 ps
CPU time 1.37 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 196076 kb
Host smart-73b45822-b982-4ec7-a57c-b791dabddb15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003769251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3003769251
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2208413155
Short name T411
Test name
Test status
Simulation time 397524737 ps
CPU time 4.53 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:06 PM PDT 24
Peak memory 198284 kb
Host smart-ea29e103-d41d-4fea-85fe-9ef67bc8ae0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208413155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2208413155
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3954939969
Short name T256
Test name
Test status
Simulation time 110685315 ps
CPU time 1.15 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 195888 kb
Host smart-f585f90c-d8e7-4e8f-b8ad-4de2575afcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954939969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3954939969
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.881513670
Short name T139
Test name
Test status
Simulation time 71217588 ps
CPU time 1.06 seconds
Started Apr 04 03:40:04 PM PDT 24
Finished Apr 04 03:40:05 PM PDT 24
Peak memory 196672 kb
Host smart-79e2beac-340f-4fd2-bb0c-9b493ec21f5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881513670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.881513670
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1520561286
Short name T406
Test name
Test status
Simulation time 5226084985 ps
CPU time 135.76 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:42:17 PM PDT 24
Peak memory 198256 kb
Host smart-d30a2d26-78dc-47dd-a785-554c7fc1259f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520561286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1520561286
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1029470854
Short name T28
Test name
Test status
Simulation time 77929504583 ps
CPU time 1798.29 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 04:10:00 PM PDT 24
Peak memory 198404 kb
Host smart-476bb816-b428-45b4-beeb-0f22c890e5c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1029470854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1029470854
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1120640552
Short name T648
Test name
Test status
Simulation time 14677045 ps
CPU time 0.56 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 194072 kb
Host smart-dd0439a3-c422-443c-af27-1a06f8a401e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120640552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1120640552
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1066237531
Short name T249
Test name
Test status
Simulation time 31008623 ps
CPU time 0.95 seconds
Started Apr 04 03:38:02 PM PDT 24
Finished Apr 04 03:38:03 PM PDT 24
Peak memory 196780 kb
Host smart-120f1103-0fd0-4a00-83ab-318cee646e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066237531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1066237531
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3504246684
Short name T144
Test name
Test status
Simulation time 1429813840 ps
CPU time 18.82 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:24 PM PDT 24
Peak memory 196928 kb
Host smart-b9643a55-5b80-491c-949a-42ad2ae14b48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504246684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3504246684
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2814017619
Short name T1
Test name
Test status
Simulation time 34395283 ps
CPU time 0.77 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:02 PM PDT 24
Peak memory 195044 kb
Host smart-de4b5723-f1fe-4566-aa11-5909f06a4527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814017619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2814017619
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2462906094
Short name T191
Test name
Test status
Simulation time 235769786 ps
CPU time 1.12 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 195888 kb
Host smart-ffc9f6ed-5263-4c52-b1eb-7fc97d6cccbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462906094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2462906094
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3490471637
Short name T53
Test name
Test status
Simulation time 289930471 ps
CPU time 2.8 seconds
Started Apr 04 03:38:02 PM PDT 24
Finished Apr 04 03:38:05 PM PDT 24
Peak memory 198276 kb
Host smart-c525fc0e-4f69-4c8f-b59d-f65c68ce8d6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490471637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3490471637
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1926579948
Short name T402
Test name
Test status
Simulation time 48831971 ps
CPU time 0.86 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 194692 kb
Host smart-19c825b6-347f-4b5b-9fc8-113a6ea24dbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926579948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1926579948
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.146169458
Short name T464
Test name
Test status
Simulation time 24248944 ps
CPU time 0.94 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 196804 kb
Host smart-34ff814d-9f43-4554-bcb2-6f6e24eb8c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146169458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.146169458
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.980861873
Short name T670
Test name
Test status
Simulation time 77131741 ps
CPU time 0.8 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196444 kb
Host smart-23556bcf-5605-4c7f-b23f-c681c2d12539
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980861873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.980861873
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.336223537
Short name T236
Test name
Test status
Simulation time 220924870 ps
CPU time 1.31 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 198212 kb
Host smart-9c5900f4-a190-4f6f-9d33-4d76ff28eaa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336223537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.336223537
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2450001146
Short name T46
Test name
Test status
Simulation time 101162028 ps
CPU time 0.77 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 213660 kb
Host smart-a1fc4d70-8dd0-4c4e-9a75-7785506205dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450001146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2450001146
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2662851203
Short name T126
Test name
Test status
Simulation time 69694467 ps
CPU time 1.27 seconds
Started Apr 04 03:38:03 PM PDT 24
Finished Apr 04 03:38:04 PM PDT 24
Peak memory 195744 kb
Host smart-60e020df-597c-4499-a489-e0ed3174b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662851203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2662851203
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2925846187
Short name T506
Test name
Test status
Simulation time 378181760 ps
CPU time 1.03 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 195892 kb
Host smart-652ba3a5-82bf-4899-a86e-438b8a94ddf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925846187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2925846187
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1486610021
Short name T266
Test name
Test status
Simulation time 1466607901 ps
CPU time 44.43 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:54 PM PDT 24
Peak memory 198300 kb
Host smart-e7b77a95-fb3c-4f0a-bef2-6d803d4c2625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486610021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1486610021
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2189817342
Short name T543
Test name
Test status
Simulation time 19421658 ps
CPU time 0.57 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 194012 kb
Host smart-0dc66040-ba6f-40f3-9b0b-5c6ed89322d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189817342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2189817342
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3264453362
Short name T171
Test name
Test status
Simulation time 76029197 ps
CPU time 0.86 seconds
Started Apr 04 03:40:13 PM PDT 24
Finished Apr 04 03:40:14 PM PDT 24
Peak memory 196580 kb
Host smart-60b9a203-db90-44c2-8950-fe2d79c90022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264453362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3264453362
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3887934126
Short name T482
Test name
Test status
Simulation time 365677272 ps
CPU time 6.84 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:22 PM PDT 24
Peak memory 198200 kb
Host smart-21320ec2-971a-449b-b171-bd983c205ad8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887934126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3887934126
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4074357857
Short name T688
Test name
Test status
Simulation time 47185261 ps
CPU time 0.84 seconds
Started Apr 04 03:40:12 PM PDT 24
Finished Apr 04 03:40:12 PM PDT 24
Peak memory 196136 kb
Host smart-8aed63ee-1db9-43a9-8e96-3ecaa2e67133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074357857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4074357857
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1525635779
Short name T499
Test name
Test status
Simulation time 178608600 ps
CPU time 1.26 seconds
Started Apr 04 03:40:13 PM PDT 24
Finished Apr 04 03:40:14 PM PDT 24
Peak memory 196056 kb
Host smart-705e80b6-ab63-479b-9656-a315da625a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525635779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1525635779
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2816202106
Short name T705
Test name
Test status
Simulation time 161195718 ps
CPU time 3.33 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 198280 kb
Host smart-78349df7-1aeb-48ca-89e6-3200a2220ae7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816202106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2816202106
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3449748090
Short name T611
Test name
Test status
Simulation time 52486903 ps
CPU time 1.04 seconds
Started Apr 04 03:40:11 PM PDT 24
Finished Apr 04 03:40:12 PM PDT 24
Peak memory 195688 kb
Host smart-4f6c8824-5c73-43de-a9e0-d7ac58d1e209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449748090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3449748090
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.106860180
Short name T714
Test name
Test status
Simulation time 66486316 ps
CPU time 0.9 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 196892 kb
Host smart-9a3afd59-cec1-401a-ad65-bb911d73735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106860180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.106860180
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.432573883
Short name T335
Test name
Test status
Simulation time 180166804 ps
CPU time 1.11 seconds
Started Apr 04 03:40:11 PM PDT 24
Finished Apr 04 03:40:12 PM PDT 24
Peak memory 196216 kb
Host smart-5dc5a55e-2f65-476b-a336-a240c0c07295
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432573883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.432573883
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2924110828
Short name T637
Test name
Test status
Simulation time 153866134 ps
CPU time 1.64 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 198284 kb
Host smart-1181ddc9-88de-4024-8b20-14d43498fbb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924110828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2924110828
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2742264496
Short name T71
Test name
Test status
Simulation time 60597222 ps
CPU time 1.26 seconds
Started Apr 04 03:40:01 PM PDT 24
Finished Apr 04 03:40:03 PM PDT 24
Peak memory 195788 kb
Host smart-12021934-341b-4a49-b51f-2a744aa71bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742264496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2742264496
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1887064580
Short name T679
Test name
Test status
Simulation time 376503249 ps
CPU time 1.38 seconds
Started Apr 04 03:40:02 PM PDT 24
Finished Apr 04 03:40:04 PM PDT 24
Peak memory 198244 kb
Host smart-e69fa6c0-9575-4d0b-a09b-c08168e64310
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887064580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1887064580
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1869787773
Short name T609
Test name
Test status
Simulation time 2129701938 ps
CPU time 28 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:44 PM PDT 24
Peak memory 197940 kb
Host smart-6c3eddcd-c317-41ff-99c4-936952aebc3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869787773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1869787773
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3704506157
Short name T621
Test name
Test status
Simulation time 84208386575 ps
CPU time 2305.37 seconds
Started Apr 04 03:40:20 PM PDT 24
Finished Apr 04 04:18:45 PM PDT 24
Peak memory 198272 kb
Host smart-630f450c-8a34-4814-90ae-4b1f45840738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3704506157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3704506157
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4008231084
Short name T458
Test name
Test status
Simulation time 38818920 ps
CPU time 0.59 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 194936 kb
Host smart-8afde648-d056-404d-8b6b-2d0ce926b3af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008231084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4008231084
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1958418913
Short name T590
Test name
Test status
Simulation time 47769258 ps
CPU time 0.64 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 194252 kb
Host smart-15114e68-979a-487d-ba11-3d4d11580f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958418913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1958418913
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3475382116
Short name T65
Test name
Test status
Simulation time 1022008055 ps
CPU time 7.84 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 197280 kb
Host smart-9f144e14-92c2-40f3-aa04-87a56eb9f65d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475382116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3475382116
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3948407866
Short name T237
Test name
Test status
Simulation time 27559405 ps
CPU time 0.7 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 194676 kb
Host smart-d8eb4e14-2471-4894-ba37-44abd5596047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948407866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3948407866
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2296995834
Short name T294
Test name
Test status
Simulation time 259016567 ps
CPU time 1.26 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 198316 kb
Host smart-f33514e1-d8bb-4249-9735-4221fff245ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296995834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2296995834
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2185802662
Short name T513
Test name
Test status
Simulation time 144561093 ps
CPU time 3.2 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 198324 kb
Host smart-55603098-1986-4bdf-afb0-60f657182122
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185802662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2185802662
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.234141829
Short name T275
Test name
Test status
Simulation time 152916388 ps
CPU time 3.36 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 197444 kb
Host smart-09837aa1-dc8a-4763-9cc4-f8f03f952467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234141829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
234141829
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3685953302
Short name T674
Test name
Test status
Simulation time 157044589 ps
CPU time 0.9 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 196084 kb
Host smart-ece1d55d-81b2-4bff-991e-21c6caa6154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685953302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3685953302
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.414880452
Short name T206
Test name
Test status
Simulation time 37112480 ps
CPU time 0.89 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 196936 kb
Host smart-0a2f250d-0ac1-42fa-879b-76cd82728003
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414880452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.414880452
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.128137509
Short name T261
Test name
Test status
Simulation time 2266129836 ps
CPU time 5.06 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:24 PM PDT 24
Peak memory 197916 kb
Host smart-043ac8c7-4695-4f92-9fcd-3cf81e9f44f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128137509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.128137509
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1973811479
Short name T447
Test name
Test status
Simulation time 37519904 ps
CPU time 0.96 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 195744 kb
Host smart-c917ac33-84a2-4ae2-8926-c16ff461163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973811479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1973811479
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3790873951
Short name T700
Test name
Test status
Simulation time 309992399 ps
CPU time 1.39 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 195580 kb
Host smart-1b4ed754-0235-4d30-84b3-bb43a94cc2e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790873951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3790873951
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.717639985
Short name T317
Test name
Test status
Simulation time 35434908730 ps
CPU time 50.29 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:41:05 PM PDT 24
Peak memory 198304 kb
Host smart-7153f078-3cf9-49d3-bfbf-443289619240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717639985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.717639985
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3398361131
Short name T189
Test name
Test status
Simulation time 11471914 ps
CPU time 0.54 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 192888 kb
Host smart-c81b5680-1b89-48bb-9e6c-fbc463284a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398361131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3398361131
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.301884449
Short name T143
Test name
Test status
Simulation time 172072652 ps
CPU time 0.85 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 196576 kb
Host smart-fb320a39-938f-4cd2-9383-e206cbca389a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301884449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.301884449
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3715792443
Short name T133
Test name
Test status
Simulation time 1313499168 ps
CPU time 16.53 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:33 PM PDT 24
Peak memory 198104 kb
Host smart-589d3814-d615-4bcb-a8b1-0bbf8c2cb3d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715792443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3715792443
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3979920074
Short name T399
Test name
Test status
Simulation time 202937173 ps
CPU time 0.97 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 198148 kb
Host smart-5e8afbbb-d6a3-4d4f-9a68-ad4e03ce2018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979920074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3979920074
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1569016006
Short name T438
Test name
Test status
Simulation time 315928665 ps
CPU time 0.92 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 197012 kb
Host smart-36388f6a-a629-40ce-9aa0-5057e3801767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569016006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1569016006
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.872585796
Short name T429
Test name
Test status
Simulation time 31884032 ps
CPU time 1.48 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 198376 kb
Host smart-e59a5573-b711-4e32-aa53-01290fb619ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872585796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.872585796
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1655991846
Short name T419
Test name
Test status
Simulation time 173154063 ps
CPU time 3.17 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 196056 kb
Host smart-c42df8af-0256-4ecd-a4ea-1e05efab8ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655991846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1655991846
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1525123706
Short name T243
Test name
Test status
Simulation time 35262526 ps
CPU time 1 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 196968 kb
Host smart-031f8fcb-7871-4c29-9032-8da28bfa2c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525123706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1525123706
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.343364790
Short name T220
Test name
Test status
Simulation time 30681128 ps
CPU time 0.6 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 194476 kb
Host smart-059b3a95-c2f5-49e2-8f6e-370f3a7dec3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343364790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.343364790
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1028016966
Short name T627
Test name
Test status
Simulation time 127507141 ps
CPU time 5.37 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 198132 kb
Host smart-ba2db263-296b-496a-86fd-abc8cee10d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028016966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1028016966
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1280113969
Short name T638
Test name
Test status
Simulation time 134750957 ps
CPU time 1.47 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 198204 kb
Host smart-73baccb2-9b71-4984-81ac-ac94bac86b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280113969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1280113969
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3998496012
Short name T338
Test name
Test status
Simulation time 41223026 ps
CPU time 1.15 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 196448 kb
Host smart-1a4302e3-4e67-44ad-8220-040506269254
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998496012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3998496012
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1160001592
Short name T676
Test name
Test status
Simulation time 3148451087 ps
CPU time 34.57 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:49 PM PDT 24
Peak memory 198268 kb
Host smart-dc40713b-fb93-42b4-a878-4bb9bbd81161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160001592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1160001592
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2865106561
Short name T57
Test name
Test status
Simulation time 349406009907 ps
CPU time 1189.44 seconds
Started Apr 04 03:40:12 PM PDT 24
Finished Apr 04 04:00:02 PM PDT 24
Peak memory 198436 kb
Host smart-66e4acb1-9135-4d23-97e8-4e6da6afd1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2865106561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2865106561
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1828873014
Short name T655
Test name
Test status
Simulation time 33104043 ps
CPU time 0.57 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 194108 kb
Host smart-e5fc3475-ee3e-4759-bc8c-472beb5aba09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828873014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1828873014
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4155066324
Short name T452
Test name
Test status
Simulation time 114159265 ps
CPU time 0.66 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 194292 kb
Host smart-b96c102e-23c3-4fc3-9b13-2fae7bd3596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155066324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4155066324
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3512211538
Short name T685
Test name
Test status
Simulation time 542953497 ps
CPU time 5.36 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 197256 kb
Host smart-12b84f66-a778-4deb-a1b3-da786de3ef35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512211538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3512211538
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2678529343
Short name T542
Test name
Test status
Simulation time 65935863 ps
CPU time 0.89 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 197936 kb
Host smart-25c8894d-93fd-4ca5-812f-c754fe360a95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678529343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2678529343
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1811778614
Short name T585
Test name
Test status
Simulation time 220463890 ps
CPU time 1.1 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 196280 kb
Host smart-2d17e989-c210-426f-bdcc-6030a160208e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811778614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1811778614
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2636894180
Short name T684
Test name
Test status
Simulation time 348587627 ps
CPU time 3.55 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 198288 kb
Host smart-3a1d63e0-5761-4917-b3e6-79a702433b18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636894180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2636894180
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2845430547
Short name T379
Test name
Test status
Simulation time 349657245 ps
CPU time 2.29 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:22 PM PDT 24
Peak memory 197096 kb
Host smart-a24f11a8-6b87-4604-85ec-f250937eb426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845430547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2845430547
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3810195409
Short name T678
Test name
Test status
Simulation time 1018704153 ps
CPU time 1.32 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 196040 kb
Host smart-830b8540-dcfc-48bd-9d4d-05203549f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810195409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3810195409
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3745633616
Short name T281
Test name
Test status
Simulation time 30739584 ps
CPU time 0.63 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 194440 kb
Host smart-993b1903-c2f1-4a3e-9056-76c603563a85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745633616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3745633616
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3160366624
Short name T9
Test name
Test status
Simulation time 657183429 ps
CPU time 2.18 seconds
Started Apr 04 03:40:11 PM PDT 24
Finished Apr 04 03:40:14 PM PDT 24
Peak memory 198148 kb
Host smart-a28fb16e-2810-4403-b270-0bb5a686e33c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160366624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3160366624
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2299845946
Short name T125
Test name
Test status
Simulation time 82353109 ps
CPU time 0.81 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 195448 kb
Host smart-b78c339e-af7d-4cab-b199-0479db978499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299845946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2299845946
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1640604756
Short name T696
Test name
Test status
Simulation time 54889801 ps
CPU time 0.97 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 196620 kb
Host smart-e3814061-5cd5-480d-9ba3-78f9e08dfc48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640604756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1640604756
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3914227688
Short name T580
Test name
Test status
Simulation time 1790397518 ps
CPU time 21.72 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:40 PM PDT 24
Peak memory 198348 kb
Host smart-629fedfb-3c92-4c45-a9ab-d4e20aab634f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914227688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3914227688
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.528204124
Short name T550
Test name
Test status
Simulation time 72675091 ps
CPU time 0.58 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 194296 kb
Host smart-7ad845b4-343c-434b-9755-c5677a4ebffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528204124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.528204124
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1733782312
Short name T368
Test name
Test status
Simulation time 32906354 ps
CPU time 0.83 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 196312 kb
Host smart-ce5fe5cf-2663-4357-a07b-90ca4db16381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733782312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1733782312
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3264745595
Short name T201
Test name
Test status
Simulation time 1333179868 ps
CPU time 14.71 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:32 PM PDT 24
Peak memory 197028 kb
Host smart-7208135e-eef3-4f9a-bc59-6716a87c2a5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264745595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3264745595
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2399109269
Short name T322
Test name
Test status
Simulation time 20747403 ps
CPU time 0.64 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 195468 kb
Host smart-87e392a9-025f-4239-96e5-0f3c8cb6de56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399109269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2399109269
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1905801703
Short name T421
Test name
Test status
Simulation time 94503758 ps
CPU time 0.85 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 196368 kb
Host smart-1109b26b-f830-4d36-9fe6-fe4309f9c5d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905801703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1905801703
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2582889394
Short name T267
Test name
Test status
Simulation time 46639926 ps
CPU time 1.42 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 197072 kb
Host smart-176c4889-de0b-43cc-b871-912ea11a9b49
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582889394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2582889394
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1465593903
Short name T122
Test name
Test status
Simulation time 108190562 ps
CPU time 3.23 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 196768 kb
Host smart-fb4a6a04-a53e-47fc-9d8f-75ab42134498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465593903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1465593903
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1039394717
Short name T479
Test name
Test status
Simulation time 117509567 ps
CPU time 1.21 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 197132 kb
Host smart-fd7a757d-e038-44a2-92b6-a055a4db1b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039394717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1039394717
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.125833256
Short name T181
Test name
Test status
Simulation time 20900657 ps
CPU time 0.8 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:18 PM PDT 24
Peak memory 196644 kb
Host smart-a408587b-a5aa-4ec7-82d9-6770e7bc79c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125833256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.125833256
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1501955521
Short name T553
Test name
Test status
Simulation time 115902900 ps
CPU time 4.77 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 198156 kb
Host smart-4eeda101-a72a-4ac7-abc9-6c515f844e36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501955521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1501955521
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1797957646
Short name T166
Test name
Test status
Simulation time 43231939 ps
CPU time 1.23 seconds
Started Apr 04 03:40:16 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 195976 kb
Host smart-c6de8406-c23e-47d4-9c33-5cc6effcfeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797957646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1797957646
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3272782062
Short name T73
Test name
Test status
Simulation time 93482357 ps
CPU time 0.82 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 196240 kb
Host smart-dcffd582-187a-4113-b410-77820a165c50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272782062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3272782062
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2404866967
Short name T296
Test name
Test status
Simulation time 25304235014 ps
CPU time 94.13 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:41:53 PM PDT 24
Peak memory 198256 kb
Host smart-1947e21a-36b7-43a7-99a2-7f87dd4d58e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404866967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2404866967
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.43011855
Short name T408
Test name
Test status
Simulation time 74734820 ps
CPU time 0.57 seconds
Started Apr 04 03:40:22 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 194768 kb
Host smart-1928add2-b399-4bf8-be58-14b041e56ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43011855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.43011855
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.193960398
Short name T68
Test name
Test status
Simulation time 18567673 ps
CPU time 0.62 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 194192 kb
Host smart-a4d2a6b9-d542-472a-903e-4228a0fc9a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193960398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.193960398
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2423990314
Short name T472
Test name
Test status
Simulation time 1916249194 ps
CPU time 7.79 seconds
Started Apr 04 03:40:17 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 197240 kb
Host smart-8647eb97-da23-4e5b-8799-0bed5728453e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423990314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2423990314
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3250780832
Short name T162
Test name
Test status
Simulation time 104505040 ps
CPU time 0.81 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 196756 kb
Host smart-99f93015-5310-42f6-91eb-577ae75a0f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250780832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3250780832
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2285739043
Short name T493
Test name
Test status
Simulation time 63848242 ps
CPU time 0.79 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 195588 kb
Host smart-dca4d09c-86ae-4e23-a147-2728b590deca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285739043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2285739043
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.180707781
Short name T180
Test name
Test status
Simulation time 570516126 ps
CPU time 2.96 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 196568 kb
Host smart-24e74c36-43ea-49c4-aa5a-6b5ad7885120
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180707781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.180707781
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3136039096
Short name T480
Test name
Test status
Simulation time 122866555 ps
CPU time 0.96 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 195620 kb
Host smart-97324ba9-b3da-4358-abd4-9e04c19c2f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136039096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3136039096
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3614703713
Short name T300
Test name
Test status
Simulation time 60798004 ps
CPU time 1.18 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:20 PM PDT 24
Peak memory 195968 kb
Host smart-0c15ab77-e68b-4209-b55b-e2a0cb65e97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614703713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3614703713
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.889808858
Short name T366
Test name
Test status
Simulation time 41576264 ps
CPU time 0.92 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 195424 kb
Host smart-25a25505-f974-4126-a525-73a5954b8be2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889808858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.889808858
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3883217229
Short name T265
Test name
Test status
Simulation time 460859691 ps
CPU time 4.15 seconds
Started Apr 04 03:40:19 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 198164 kb
Host smart-54f0a1c3-d66d-49ab-8b03-ddec213a3acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883217229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3883217229
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1101224750
Short name T434
Test name
Test status
Simulation time 57932805 ps
CPU time 0.78 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 195332 kb
Host smart-dba3784c-5f5b-48ea-bd59-f3ee18297e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101224750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1101224750
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.380875297
Short name T286
Test name
Test status
Simulation time 132034598 ps
CPU time 0.87 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:40:19 PM PDT 24
Peak memory 196044 kb
Host smart-7877a3d1-3255-4e55-9c83-a2238370202f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380875297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.380875297
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1731859092
Short name T354
Test name
Test status
Simulation time 38151602547 ps
CPU time 95.62 seconds
Started Apr 04 03:40:18 PM PDT 24
Finished Apr 04 03:41:54 PM PDT 24
Peak memory 198212 kb
Host smart-710f95ef-d7fd-4aaf-a958-13b442a2a6dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731859092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1731859092
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.180290805
Short name T577
Test name
Test status
Simulation time 14238520 ps
CPU time 0.55 seconds
Started Apr 04 03:40:27 PM PDT 24
Finished Apr 04 03:40:28 PM PDT 24
Peak memory 194116 kb
Host smart-dbec0aa4-4324-4ddb-b490-1cbbd7e7d336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180290805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.180290805
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1416030097
Short name T254
Test name
Test status
Simulation time 20284583 ps
CPU time 0.7 seconds
Started Apr 04 03:40:22 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 194280 kb
Host smart-1ae35187-35e3-40f3-9d2b-c37815ff6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416030097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1416030097
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1636194927
Short name T545
Test name
Test status
Simulation time 1610049171 ps
CPU time 11.14 seconds
Started Apr 04 03:40:20 PM PDT 24
Finished Apr 04 03:40:32 PM PDT 24
Peak memory 197072 kb
Host smart-4c7d4abd-a2d7-4ed5-a39f-13a5bcaf3de7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636194927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1636194927
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3439950785
Short name T154
Test name
Test status
Simulation time 25385596 ps
CPU time 0.74 seconds
Started Apr 04 03:40:20 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 194744 kb
Host smart-50db2a87-8dab-4689-9b2a-8d1bd994e914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439950785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3439950785
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3228865113
Short name T175
Test name
Test status
Simulation time 101240663 ps
CPU time 1.17 seconds
Started Apr 04 03:40:23 PM PDT 24
Finished Apr 04 03:40:24 PM PDT 24
Peak memory 196176 kb
Host smart-e2e83b48-3215-4088-a0e5-d79bd858502f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228865113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3228865113
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3733224504
Short name T586
Test name
Test status
Simulation time 642037533 ps
CPU time 1.84 seconds
Started Apr 04 03:40:22 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 198272 kb
Host smart-43e517b2-1f1a-4b4b-8d6e-0651161b6d3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733224504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3733224504
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1020212881
Short name T587
Test name
Test status
Simulation time 84493066 ps
CPU time 2.46 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:17 PM PDT 24
Peak memory 197384 kb
Host smart-f6eb3bd2-715c-4b45-83b7-36f286077dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020212881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1020212881
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3240645482
Short name T628
Test name
Test status
Simulation time 47476392 ps
CPU time 0.75 seconds
Started Apr 04 03:40:23 PM PDT 24
Finished Apr 04 03:40:24 PM PDT 24
Peak memory 195564 kb
Host smart-6bbb6058-9218-477c-b18c-7e78159a07f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240645482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3240645482
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3665318871
Short name T141
Test name
Test status
Simulation time 73837968 ps
CPU time 1.33 seconds
Started Apr 04 03:40:22 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 197332 kb
Host smart-a2055194-3dbc-4f3e-9c7e-75925097e4f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665318871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3665318871
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1624765502
Short name T4
Test name
Test status
Simulation time 1343661687 ps
CPU time 3.92 seconds
Started Apr 04 03:40:21 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 198168 kb
Host smart-e3c7be02-f1b4-4dc3-b3ba-d8cb7a11c15c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624765502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1624765502
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1732355106
Short name T554
Test name
Test status
Simulation time 179691009 ps
CPU time 1.24 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:40:16 PM PDT 24
Peak memory 196824 kb
Host smart-61ba5f9a-6b3a-4168-9d94-4b717e7c675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732355106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1732355106
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3454931294
Short name T465
Test name
Test status
Simulation time 28056974 ps
CPU time 0.93 seconds
Started Apr 04 03:40:14 PM PDT 24
Finished Apr 04 03:40:15 PM PDT 24
Peak memory 196580 kb
Host smart-881f4f67-c20f-42f6-9491-4aa5e4f1a916
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454931294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3454931294
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.4049016123
Short name T131
Test name
Test status
Simulation time 15135726133 ps
CPU time 178.12 seconds
Started Apr 04 03:40:15 PM PDT 24
Finished Apr 04 03:43:13 PM PDT 24
Peak memory 198308 kb
Host smart-7a09fd7c-2919-462e-bc9b-23a506d99558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049016123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.4049016123
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1993559346
Short name T551
Test name
Test status
Simulation time 270698407453 ps
CPU time 1867.72 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 04:11:32 PM PDT 24
Peak memory 198404 kb
Host smart-c4709960-5bbb-453c-8707-482e5e8b7073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1993559346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1993559346
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.242162067
Short name T686
Test name
Test status
Simulation time 37893459 ps
CPU time 0.6 seconds
Started Apr 04 03:40:34 PM PDT 24
Finished Apr 04 03:40:35 PM PDT 24
Peak memory 194952 kb
Host smart-e3f64729-35ca-495e-a312-0b03dfe3669a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242162067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.242162067
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3330377693
Short name T283
Test name
Test status
Simulation time 86192409 ps
CPU time 0.76 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 196040 kb
Host smart-5f37069e-5253-4cb0-b134-ee9d2c56484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330377693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3330377693
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2565442461
Short name T420
Test name
Test status
Simulation time 776477087 ps
CPU time 5.86 seconds
Started Apr 04 03:40:32 PM PDT 24
Finished Apr 04 03:40:38 PM PDT 24
Peak memory 197060 kb
Host smart-0f788867-33b1-4a67-840b-2616d059d117
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565442461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2565442461
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.309383711
Short name T414
Test name
Test status
Simulation time 211023715 ps
CPU time 0.92 seconds
Started Apr 04 03:40:26 PM PDT 24
Finished Apr 04 03:40:27 PM PDT 24
Peak memory 196548 kb
Host smart-e9981974-442c-4374-a57f-fd3c24cb05cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309383711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.309383711
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3888134110
Short name T474
Test name
Test status
Simulation time 103983571 ps
CPU time 0.75 seconds
Started Apr 04 03:40:27 PM PDT 24
Finished Apr 04 03:40:28 PM PDT 24
Peak memory 195752 kb
Host smart-1bf5ff11-51b7-4b43-91be-e6765e21515d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888134110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3888134110
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.4205920067
Short name T453
Test name
Test status
Simulation time 261000907 ps
CPU time 2.82 seconds
Started Apr 04 03:40:33 PM PDT 24
Finished Apr 04 03:40:36 PM PDT 24
Peak memory 196732 kb
Host smart-7072986a-10ad-414b-8a27-6d18ee7e23d8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205920067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.4205920067
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.352128256
Short name T610
Test name
Test status
Simulation time 238184857 ps
CPU time 3.46 seconds
Started Apr 04 03:40:25 PM PDT 24
Finished Apr 04 03:40:28 PM PDT 24
Peak memory 197328 kb
Host smart-7e1341e2-fc8a-47d6-b661-268e037087d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352128256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
352128256
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2064613485
Short name T633
Test name
Test status
Simulation time 33958896 ps
CPU time 1.09 seconds
Started Apr 04 03:40:38 PM PDT 24
Finished Apr 04 03:40:40 PM PDT 24
Peak memory 196212 kb
Host smart-b6d3c7ad-da0e-438f-adac-6d2599c42362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064613485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2064613485
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4043112966
Short name T51
Test name
Test status
Simulation time 30574968 ps
CPU time 1.13 seconds
Started Apr 04 03:40:38 PM PDT 24
Finished Apr 04 03:40:40 PM PDT 24
Peak memory 197060 kb
Host smart-a37dc4bb-37d9-466d-a5ce-14382cb3af3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043112966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4043112966
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1663506732
Short name T715
Test name
Test status
Simulation time 262841042 ps
CPU time 3.27 seconds
Started Apr 04 03:40:33 PM PDT 24
Finished Apr 04 03:40:37 PM PDT 24
Peak memory 198208 kb
Host smart-db024daa-5c78-4235-a961-253bb6f4edc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663506732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1663506732
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1237356801
Short name T350
Test name
Test status
Simulation time 28235935 ps
CPU time 0.86 seconds
Started Apr 04 03:40:25 PM PDT 24
Finished Apr 04 03:40:26 PM PDT 24
Peak memory 195548 kb
Host smart-f515ef48-18ec-42f0-b2b6-6c8afc6ea1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237356801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1237356801
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2285764107
Short name T496
Test name
Test status
Simulation time 85308333 ps
CPU time 1.44 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:26 PM PDT 24
Peak memory 195812 kb
Host smart-83ffc934-3829-4d2e-9a48-d10a5747df73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285764107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2285764107
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2638374352
Short name T3
Test name
Test status
Simulation time 44055790243 ps
CPU time 125.99 seconds
Started Apr 04 03:40:34 PM PDT 24
Finished Apr 04 03:42:40 PM PDT 24
Peak memory 198256 kb
Host smart-4fbca7ad-9d4e-4398-84fc-b3d94b615c00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638374352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2638374352
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.192778270
Short name T372
Test name
Test status
Simulation time 38332777 ps
CPU time 0.54 seconds
Started Apr 04 03:40:38 PM PDT 24
Finished Apr 04 03:40:39 PM PDT 24
Peak memory 194080 kb
Host smart-46a73052-7c78-49d0-93f7-684fe72fb49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192778270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.192778270
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2367484868
Short name T264
Test name
Test status
Simulation time 81715625 ps
CPU time 0.77 seconds
Started Apr 04 03:40:33 PM PDT 24
Finished Apr 04 03:40:34 PM PDT 24
Peak memory 194292 kb
Host smart-502bc241-a3f9-46c2-9154-7049dd42329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367484868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2367484868
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.622206894
Short name T457
Test name
Test status
Simulation time 777814763 ps
CPU time 10.56 seconds
Started Apr 04 03:40:39 PM PDT 24
Finished Apr 04 03:40:49 PM PDT 24
Peak memory 197028 kb
Host smart-ca73c306-5f6a-491a-9fd1-4ae00b79f818
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622206894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.622206894
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1919659100
Short name T418
Test name
Test status
Simulation time 68084210 ps
CPU time 0.75 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 196264 kb
Host smart-aeb65523-d626-495c-96f5-9f739aab4559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919659100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1919659100
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2083816467
Short name T315
Test name
Test status
Simulation time 228188921 ps
CPU time 1.4 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 198256 kb
Host smart-f93f21fb-607c-424d-8126-d266ba39e7d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083816467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2083816467
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1216173539
Short name T532
Test name
Test status
Simulation time 110697496 ps
CPU time 1.36 seconds
Started Apr 04 03:40:34 PM PDT 24
Finished Apr 04 03:40:36 PM PDT 24
Peak memory 195700 kb
Host smart-5d28b5b9-1ee6-4b62-a472-f46ea8fbd3fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216173539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1216173539
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3655600526
Short name T359
Test name
Test status
Simulation time 818254274 ps
CPU time 3.08 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:27 PM PDT 24
Peak memory 197124 kb
Host smart-c90bbc2c-1398-4c0a-8681-830686bb9ae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655600526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3655600526
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1971346959
Short name T592
Test name
Test status
Simulation time 68066772 ps
CPU time 0.76 seconds
Started Apr 04 03:40:34 PM PDT 24
Finished Apr 04 03:40:35 PM PDT 24
Peak memory 195620 kb
Host smart-b4f85e5a-2e9a-420f-80ed-b3e5a86901d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971346959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1971346959
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3537836816
Short name T682
Test name
Test status
Simulation time 48130076 ps
CPU time 0.62 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 195180 kb
Host smart-dba43259-a1d5-486f-8a89-7d5d6aa25e18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537836816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3537836816
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1651238154
Short name T647
Test name
Test status
Simulation time 606819426 ps
CPU time 4.26 seconds
Started Apr 04 03:40:25 PM PDT 24
Finished Apr 04 03:40:29 PM PDT 24
Peak memory 198236 kb
Host smart-f75225eb-8cf7-4a18-bdf0-70d39953493b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651238154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1651238154
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.633180556
Short name T361
Test name
Test status
Simulation time 304034711 ps
CPU time 1.17 seconds
Started Apr 04 03:40:34 PM PDT 24
Finished Apr 04 03:40:36 PM PDT 24
Peak memory 194996 kb
Host smart-5362a651-39ce-43a1-84fe-058fb4cb3eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633180556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.633180556
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3447903171
Short name T607
Test name
Test status
Simulation time 102214293 ps
CPU time 1.14 seconds
Started Apr 04 03:40:27 PM PDT 24
Finished Apr 04 03:40:28 PM PDT 24
Peak memory 195776 kb
Host smart-6b9b8cbd-e200-49c5-aa2e-25e0956564c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447903171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3447903171
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2382794428
Short name T632
Test name
Test status
Simulation time 62068560696 ps
CPU time 166.49 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:43:11 PM PDT 24
Peak memory 198408 kb
Host smart-b7365b44-8b92-45a5-aa05-82cbcb8d872a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382794428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2382794428
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2645614416
Short name T78
Test name
Test status
Simulation time 102744398273 ps
CPU time 1567.49 seconds
Started Apr 04 03:40:26 PM PDT 24
Finished Apr 04 04:06:34 PM PDT 24
Peak memory 198392 kb
Host smart-a46edc25-6e60-4565-a6b5-7e04bb63df63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2645614416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2645614416
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3342895037
Short name T308
Test name
Test status
Simulation time 36978193 ps
CPU time 0.57 seconds
Started Apr 04 03:40:40 PM PDT 24
Finished Apr 04 03:40:41 PM PDT 24
Peak memory 194100 kb
Host smart-cba903ab-a136-41e9-98b7-29faa3663db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342895037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3342895037
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1821659154
Short name T270
Test name
Test status
Simulation time 28621327 ps
CPU time 0.8 seconds
Started Apr 04 03:40:24 PM PDT 24
Finished Apr 04 03:40:25 PM PDT 24
Peak memory 195412 kb
Host smart-b0211180-6d15-49da-8e6f-3d558e184861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821659154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1821659154
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3822447186
Short name T145
Test name
Test status
Simulation time 505350505 ps
CPU time 15.73 seconds
Started Apr 04 03:40:41 PM PDT 24
Finished Apr 04 03:40:57 PM PDT 24
Peak memory 198220 kb
Host smart-ec4209e3-3ff4-4b2a-848c-55d6497f185a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822447186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3822447186
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2516938109
Short name T340
Test name
Test status
Simulation time 111894296 ps
CPU time 0.98 seconds
Started Apr 04 03:40:39 PM PDT 24
Finished Apr 04 03:40:40 PM PDT 24
Peak memory 196792 kb
Host smart-fe186076-e22f-412b-8320-5b719b8541ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516938109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2516938109
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2736663453
Short name T172
Test name
Test status
Simulation time 189028018 ps
CPU time 0.82 seconds
Started Apr 04 03:40:33 PM PDT 24
Finished Apr 04 03:40:34 PM PDT 24
Peak memory 195764 kb
Host smart-b33157f3-00a5-41ae-b2d8-1da862a9905a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736663453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2736663453
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2683493839
Short name T106
Test name
Test status
Simulation time 59645349 ps
CPU time 0.91 seconds
Started Apr 04 03:40:37 PM PDT 24
Finished Apr 04 03:40:38 PM PDT 24
Peak memory 196180 kb
Host smart-af9f385e-3111-4293-9866-924f66762b44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683493839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2683493839
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2740319193
Short name T21
Test name
Test status
Simulation time 110328562 ps
CPU time 1.74 seconds
Started Apr 04 03:40:39 PM PDT 24
Finished Apr 04 03:40:41 PM PDT 24
Peak memory 195972 kb
Host smart-18f3ac25-56b6-4c2b-9b4b-b9ed90888daf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740319193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2740319193
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.492688804
Short name T385
Test name
Test status
Simulation time 17694247 ps
CPU time 0.79 seconds
Started Apr 04 03:40:38 PM PDT 24
Finished Apr 04 03:40:39 PM PDT 24
Peak memory 195528 kb
Host smart-54aaf330-a884-46e5-8af2-57364cfb784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492688804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.492688804
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4084694638
Short name T211
Test name
Test status
Simulation time 18586366 ps
CPU time 0.68 seconds
Started Apr 04 03:40:33 PM PDT 24
Finished Apr 04 03:40:33 PM PDT 24
Peak memory 194528 kb
Host smart-a61c64a6-1151-4b75-9a1d-be08202cb924
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084694638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4084694638
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.593184776
Short name T709
Test name
Test status
Simulation time 165860373 ps
CPU time 3.94 seconds
Started Apr 04 03:40:37 PM PDT 24
Finished Apr 04 03:40:41 PM PDT 24
Peak memory 198140 kb
Host smart-ee022d94-175a-4a78-b448-c176297587fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593184776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.593184776
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4211495852
Short name T690
Test name
Test status
Simulation time 52295401 ps
CPU time 0.73 seconds
Started Apr 04 03:40:25 PM PDT 24
Finished Apr 04 03:40:26 PM PDT 24
Peak memory 195456 kb
Host smart-5dcdfc90-d215-46d5-baf1-90bc3c47c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211495852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4211495852
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3237081619
Short name T462
Test name
Test status
Simulation time 179181918 ps
CPU time 1.07 seconds
Started Apr 04 03:40:25 PM PDT 24
Finished Apr 04 03:40:26 PM PDT 24
Peak memory 195736 kb
Host smart-600af333-760f-4f57-9d91-9abfc5dafdad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237081619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3237081619
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.959614925
Short name T530
Test name
Test status
Simulation time 16924588370 ps
CPU time 123.01 seconds
Started Apr 04 03:40:38 PM PDT 24
Finished Apr 04 03:42:41 PM PDT 24
Peak memory 198284 kb
Host smart-8932e708-cee9-421f-aee8-710538507b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959614925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.959614925
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.303210802
Short name T348
Test name
Test status
Simulation time 21752087 ps
CPU time 0.59 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 194240 kb
Host smart-612d5931-c4e4-46a8-8dad-dd596b6d365b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303210802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.303210802
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1506981427
Short name T484
Test name
Test status
Simulation time 30690155 ps
CPU time 0.86 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 196516 kb
Host smart-b325e0dd-3ea7-4326-a82f-1fb3ef3c792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506981427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1506981427
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.481378186
Short name T147
Test name
Test status
Simulation time 831782850 ps
CPU time 13.09 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:20 PM PDT 24
Peak memory 196800 kb
Host smart-87751f48-bdf0-420e-9c35-9c18b9554999
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481378186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.481378186
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3978513402
Short name T305
Test name
Test status
Simulation time 56909670 ps
CPU time 0.66 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 195444 kb
Host smart-e472f3cb-0b34-4ef0-a013-51423e4dab35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978513402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3978513402
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1272407701
Short name T225
Test name
Test status
Simulation time 144185345 ps
CPU time 1.11 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196288 kb
Host smart-b4a171c9-69f9-4a6f-b314-b23aeee2516c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272407701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1272407701
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.486984203
Short name T117
Test name
Test status
Simulation time 23160848 ps
CPU time 0.96 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196240 kb
Host smart-f2a67a12-d752-400a-8e7a-3beefec702d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486984203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.486984203
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2244161062
Short name T466
Test name
Test status
Simulation time 40328290 ps
CPU time 1.13 seconds
Started Apr 04 03:38:10 PM PDT 24
Finished Apr 04 03:38:13 PM PDT 24
Peak memory 196612 kb
Host smart-1a677c64-0892-4918-a8d9-1c7e1a714d1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244161062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2244161062
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3815447440
Short name T153
Test name
Test status
Simulation time 73205419 ps
CPU time 1 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 196268 kb
Host smart-649fc2e1-ba02-427c-b1f4-e5c254218776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815447440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3815447440
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1182518740
Short name T565
Test name
Test status
Simulation time 175514931 ps
CPU time 1.11 seconds
Started Apr 04 03:38:01 PM PDT 24
Finished Apr 04 03:38:02 PM PDT 24
Peak memory 197012 kb
Host smart-d81a4ac1-b947-48dd-96ff-097266e913e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182518740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1182518740
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3821085164
Short name T437
Test name
Test status
Simulation time 1829828584 ps
CPU time 5.97 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 198088 kb
Host smart-277e48be-71d7-4ce6-a20c-0dc829fba1d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821085164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3821085164
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4279094466
Short name T333
Test name
Test status
Simulation time 132953661 ps
CPU time 1.11 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 196744 kb
Host smart-cda45171-b2e4-4003-aef1-118297dceb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279094466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4279094466
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1164549228
Short name T312
Test name
Test status
Simulation time 582025248 ps
CPU time 1 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 195656 kb
Host smart-d3870d93-3479-40bc-8826-42f594fb1362
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164549228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1164549228
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.98021832
Short name T121
Test name
Test status
Simulation time 36149847121 ps
CPU time 189.46 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:41:16 PM PDT 24
Peak memory 198316 kb
Host smart-cfd0bde9-b9e4-4836-b465-9eb345f6078a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98021832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpi
o_stress_all.98021832
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1698138498
Short name T27
Test name
Test status
Simulation time 55745162043 ps
CPU time 828.56 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:51:55 PM PDT 24
Peak memory 198372 kb
Host smart-e1b2f609-2903-49e0-a8a3-1c32895522d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1698138498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1698138498
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3072777404
Short name T168
Test name
Test status
Simulation time 13672580 ps
CPU time 0.58 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 194756 kb
Host smart-0750e880-7a1c-4635-8d44-5efe35fdfd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072777404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3072777404
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1182618535
Short name T449
Test name
Test status
Simulation time 154178388 ps
CPU time 0.94 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 196244 kb
Host smart-d54c049e-4cec-48c3-9014-060ccd66c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182618535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1182618535
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1188774423
Short name T303
Test name
Test status
Simulation time 344652532 ps
CPU time 16.53 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:23 PM PDT 24
Peak memory 196704 kb
Host smart-ac50c4aa-9644-4e20-a83c-0704e2c548dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188774423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1188774423
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2596155507
Short name T391
Test name
Test status
Simulation time 317161489 ps
CPU time 0.95 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 198104 kb
Host smart-b7838ed4-2f4e-4b58-a60c-93631e9eabed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596155507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2596155507
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1445954617
Short name T396
Test name
Test status
Simulation time 30304854 ps
CPU time 0.9 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 196884 kb
Host smart-f353c5fc-1e1d-44f3-8b4e-e4367547fcbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445954617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1445954617
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3349979025
Short name T271
Test name
Test status
Simulation time 108721874 ps
CPU time 1.33 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 198076 kb
Host smart-242309c1-4011-42ed-8052-f996102307aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349979025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3349979025
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3951564732
Short name T663
Test name
Test status
Simulation time 25532415 ps
CPU time 0.91 seconds
Started Apr 04 03:38:03 PM PDT 24
Finished Apr 04 03:38:04 PM PDT 24
Peak memory 195740 kb
Host smart-2a832328-f2f3-46fb-9f15-07b1636eee82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951564732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3951564732
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1755828308
Short name T510
Test name
Test status
Simulation time 372408317 ps
CPU time 1.17 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 196888 kb
Host smart-0ab9ef72-a641-40d6-a836-892a13cc4f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755828308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1755828308
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1514347100
Short name T538
Test name
Test status
Simulation time 563806609 ps
CPU time 0.91 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196016 kb
Host smart-eff9e0ab-b371-4d1f-be29-5bb806033018
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514347100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1514347100
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2411150780
Short name T504
Test name
Test status
Simulation time 218783840 ps
CPU time 3.52 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 198084 kb
Host smart-0fedb877-f6d0-4098-bec9-2cbb0b217faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411150780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2411150780
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.425606127
Short name T672
Test name
Test status
Simulation time 170814359 ps
CPU time 1.35 seconds
Started Apr 04 03:38:04 PM PDT 24
Finished Apr 04 03:38:06 PM PDT 24
Peak memory 198104 kb
Host smart-83cddf02-cb15-4c70-9148-56ef7bdb1e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425606127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.425606127
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3440177871
Short name T654
Test name
Test status
Simulation time 184326276 ps
CPU time 1.37 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196996 kb
Host smart-ff385de0-19d7-4422-82c9-613124b91e81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440177871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3440177871
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.918677260
Short name T240
Test name
Test status
Simulation time 10200053985 ps
CPU time 144.73 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:40:34 PM PDT 24
Peak memory 198340 kb
Host smart-42b10cfb-baa2-4e6b-9924-48f5b136c9d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918677260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.918677260
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2589565510
Short name T113
Test name
Test status
Simulation time 450571857825 ps
CPU time 2529.59 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 04:20:19 PM PDT 24
Peak memory 198428 kb
Host smart-897d656d-030b-456a-bb32-ec716688e17d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2589565510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2589565510
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3104590576
Short name T277
Test name
Test status
Simulation time 25204939 ps
CPU time 0.57 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:07 PM PDT 24
Peak memory 194248 kb
Host smart-bda91e20-944a-472e-9383-69427c024a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104590576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3104590576
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2408634899
Short name T706
Test name
Test status
Simulation time 160158829 ps
CPU time 0.95 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 196772 kb
Host smart-b6e2e3e0-51af-447b-a0b8-6d2f2e255de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408634899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2408634899
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3226607400
Short name T403
Test name
Test status
Simulation time 232309965 ps
CPU time 11.89 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:21 PM PDT 24
Peak memory 196896 kb
Host smart-6e28de2e-8532-4599-a326-1bf252d43365
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226607400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3226607400
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.893515878
Short name T517
Test name
Test status
Simulation time 82403409 ps
CPU time 1.01 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 196908 kb
Host smart-94a1bc12-2206-4efc-abcf-8192c97450c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893515878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.893515878
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2193620457
Short name T645
Test name
Test status
Simulation time 204116803 ps
CPU time 1 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 197080 kb
Host smart-ba497eec-fc76-4ab7-a7f2-45769b8d7770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193620457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2193620457
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3217419319
Short name T570
Test name
Test status
Simulation time 66726845 ps
CPU time 2.46 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 198324 kb
Host smart-9fc0b3b3-8101-4def-b6d5-29718b42279d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217419319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3217419319
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1993068398
Short name T187
Test name
Test status
Simulation time 1286258790 ps
CPU time 2.14 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 197132 kb
Host smart-85e2ce39-8e43-49ed-9a74-cadd5e11214e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993068398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1993068398
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4052898790
Short name T393
Test name
Test status
Simulation time 121077890 ps
CPU time 1 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196124 kb
Host smart-9210229c-cf72-466d-8b6e-7fd2086ab6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052898790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4052898790
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1741947101
Short name T579
Test name
Test status
Simulation time 296599306 ps
CPU time 1.34 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196040 kb
Host smart-c31ad2b9-c320-488c-beca-0db7942279df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741947101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1741947101
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1661982574
Short name T572
Test name
Test status
Simulation time 557752641 ps
CPU time 6.08 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:13 PM PDT 24
Peak memory 198180 kb
Host smart-1e546ee9-875a-4a15-a88b-2f3570bc053e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661982574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1661982574
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1988058392
Short name T159
Test name
Test status
Simulation time 55451241 ps
CPU time 1.36 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 196388 kb
Host smart-4aa77b60-9025-47d1-8e3b-692331b1628f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988058392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1988058392
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1417831897
Short name T642
Test name
Test status
Simulation time 88227970 ps
CPU time 1 seconds
Started Apr 04 03:38:06 PM PDT 24
Finished Apr 04 03:38:08 PM PDT 24
Peak memory 196040 kb
Host smart-4f7dc9ad-fbc6-40fb-a66e-75b8ca35b7dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417831897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1417831897
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3278791038
Short name T216
Test name
Test status
Simulation time 22580424912 ps
CPU time 118.63 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:40:08 PM PDT 24
Peak memory 198368 kb
Host smart-31049402-f3c2-4c3a-af8c-70067f46d74e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278791038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3278791038
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4232172791
Short name T445
Test name
Test status
Simulation time 42175695584 ps
CPU time 465.63 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:45:55 PM PDT 24
Peak memory 198368 kb
Host smart-ce6bf76a-787d-4722-8964-ee41bd8a1461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4232172791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4232172791
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.77509464
Short name T382
Test name
Test status
Simulation time 51953825 ps
CPU time 0.62 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:25 PM PDT 24
Peak memory 194984 kb
Host smart-68c77519-6b81-4db4-9cd9-5c759cde6425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77509464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.77509464
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2714079526
Short name T213
Test name
Test status
Simulation time 28548151 ps
CPU time 0.77 seconds
Started Apr 04 03:38:10 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 195352 kb
Host smart-3a824e9a-5497-4268-9795-4b50845ad9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714079526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2714079526
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4087329539
Short name T200
Test name
Test status
Simulation time 154402446 ps
CPU time 4.19 seconds
Started Apr 04 03:38:23 PM PDT 24
Finished Apr 04 03:38:27 PM PDT 24
Peak memory 195764 kb
Host smart-38baf38d-1272-4f1c-b5e1-b4360349c055
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087329539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4087329539
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.929935834
Short name T568
Test name
Test status
Simulation time 67616383 ps
CPU time 1.03 seconds
Started Apr 04 03:38:21 PM PDT 24
Finished Apr 04 03:38:22 PM PDT 24
Peak memory 196804 kb
Host smart-8be24b7c-f2b3-4fa6-85c1-310cf39b3468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929935834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.929935834
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1347453538
Short name T196
Test name
Test status
Simulation time 324585240 ps
CPU time 1.34 seconds
Started Apr 04 03:38:07 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 196008 kb
Host smart-62e1a9d3-b5b8-47c0-93d9-49641dade663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347453538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1347453538
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4250285570
Short name T298
Test name
Test status
Simulation time 111690450 ps
CPU time 2.11 seconds
Started Apr 04 03:38:05 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 198288 kb
Host smart-04d779d9-0f0c-4838-aa0a-21dc6fac0707
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250285570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4250285570
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.911752364
Short name T641
Test name
Test status
Simulation time 291475638 ps
CPU time 1.87 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:12 PM PDT 24
Peak memory 196308 kb
Host smart-3726c316-b3ac-486c-a91a-05b5979c1400
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911752364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.911752364
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4195620059
Short name T345
Test name
Test status
Simulation time 44622179 ps
CPU time 0.71 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:10 PM PDT 24
Peak memory 196360 kb
Host smart-34406d00-c765-4b4b-a7ef-4bdc039d41b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195620059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4195620059
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.666718688
Short name T656
Test name
Test status
Simulation time 31595858 ps
CPU time 0.83 seconds
Started Apr 04 03:38:08 PM PDT 24
Finished Apr 04 03:38:09 PM PDT 24
Peak memory 196820 kb
Host smart-ff42bd4e-1cd4-402c-aa08-95a16fbd8638
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666718688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.666718688
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.950988820
Short name T710
Test name
Test status
Simulation time 73905121 ps
CPU time 3.6 seconds
Started Apr 04 03:38:20 PM PDT 24
Finished Apr 04 03:38:24 PM PDT 24
Peak memory 198064 kb
Host smart-c93124bb-3cd0-4d6a-839e-6f2cbeafa906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950988820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.950988820
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1630840901
Short name T351
Test name
Test status
Simulation time 62548866 ps
CPU time 1.2 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 195848 kb
Host smart-9c38b27e-4c07-4164-9030-fe98525bb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630840901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1630840901
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2802041107
Short name T17
Test name
Test status
Simulation time 153559425 ps
CPU time 1.02 seconds
Started Apr 04 03:38:09 PM PDT 24
Finished Apr 04 03:38:11 PM PDT 24
Peak memory 196764 kb
Host smart-1665db03-bfae-46c6-8e40-42bb7497852c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802041107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2802041107
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.245838700
Short name T221
Test name
Test status
Simulation time 37253065510 ps
CPU time 113.97 seconds
Started Apr 04 03:38:26 PM PDT 24
Finished Apr 04 03:40:21 PM PDT 24
Peak memory 198268 kb
Host smart-77993b46-9db2-41c5-9783-180f1517227f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245838700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.245838700
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2153332320
Short name T395
Test name
Test status
Simulation time 13127211 ps
CPU time 0.57 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 194296 kb
Host smart-1adbf187-4b76-45c0-8574-12b8a75d96b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153332320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2153332320
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.4155443949
Short name T492
Test name
Test status
Simulation time 48848286 ps
CPU time 0.83 seconds
Started Apr 04 03:38:20 PM PDT 24
Finished Apr 04 03:38:21 PM PDT 24
Peak memory 196016 kb
Host smart-73a64773-6308-4cc5-815f-8e4ad62d4880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155443949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.4155443949
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.986428614
Short name T314
Test name
Test status
Simulation time 98385951 ps
CPU time 5.29 seconds
Started Apr 04 03:38:18 PM PDT 24
Finished Apr 04 03:38:24 PM PDT 24
Peak memory 198140 kb
Host smart-f797f56c-230d-4aa8-8176-f8e95e281604
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986428614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.986428614
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.885788166
Short name T328
Test name
Test status
Simulation time 65859222 ps
CPU time 0.75 seconds
Started Apr 04 03:38:16 PM PDT 24
Finished Apr 04 03:38:17 PM PDT 24
Peak memory 196684 kb
Host smart-196026aa-72a3-4124-9d44-be0aec66ae18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885788166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.885788166
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3419889865
Short name T560
Test name
Test status
Simulation time 24116693 ps
CPU time 0.79 seconds
Started Apr 04 03:38:19 PM PDT 24
Finished Apr 04 03:38:20 PM PDT 24
Peak memory 196436 kb
Host smart-3658d3d6-6926-4861-959e-6e5ccbb1cc18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419889865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3419889865
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2002341526
Short name T369
Test name
Test status
Simulation time 456360116 ps
CPU time 2.79 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:28 PM PDT 24
Peak memory 198080 kb
Host smart-325277a4-63d7-4f6b-8f99-8113cb7a54a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002341526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2002341526
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2913331831
Short name T650
Test name
Test status
Simulation time 130571121 ps
CPU time 2.94 seconds
Started Apr 04 03:38:23 PM PDT 24
Finished Apr 04 03:38:26 PM PDT 24
Peak memory 198300 kb
Host smart-9d0abe74-305b-4481-b04c-d71f593870bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913331831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2913331831
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.487355887
Short name T444
Test name
Test status
Simulation time 76487990 ps
CPU time 1.39 seconds
Started Apr 04 03:38:16 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 197192 kb
Host smart-99a4e940-f0d6-454a-851e-437d45e5f77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487355887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.487355887
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1723011937
Short name T209
Test name
Test status
Simulation time 419923646 ps
CPU time 1.32 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:18 PM PDT 24
Peak memory 198328 kb
Host smart-c26fad3e-109a-49eb-bb39-b7b0ecb8e62a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723011937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1723011937
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3950164766
Short name T279
Test name
Test status
Simulation time 50758824 ps
CPU time 2.37 seconds
Started Apr 04 03:38:17 PM PDT 24
Finished Apr 04 03:38:20 PM PDT 24
Peak memory 197920 kb
Host smart-ecad26f9-a30b-49fa-874c-187954392089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950164766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3950164766
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3781257543
Short name T605
Test name
Test status
Simulation time 141422147 ps
CPU time 1.26 seconds
Started Apr 04 03:38:28 PM PDT 24
Finished Apr 04 03:38:30 PM PDT 24
Peak memory 196616 kb
Host smart-96530689-24fb-4dd6-a6a2-05d96b5e2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781257543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3781257543
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2515812799
Short name T521
Test name
Test status
Simulation time 231912893 ps
CPU time 1.12 seconds
Started Apr 04 03:38:25 PM PDT 24
Finished Apr 04 03:38:27 PM PDT 24
Peak memory 195816 kb
Host smart-bd3cb757-21ef-4453-ab9d-d7fcdc598c36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515812799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2515812799
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.838544629
Short name T417
Test name
Test status
Simulation time 11441131184 ps
CPU time 158.72 seconds
Started Apr 04 03:38:26 PM PDT 24
Finished Apr 04 03:41:05 PM PDT 24
Peak memory 198336 kb
Host smart-0b91fe8c-ad3c-4ae8-8d69-d6d8c18c5b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838544629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.838544629
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.680277549
Short name T942
Test name
Test status
Simulation time 300321267 ps
CPU time 1.01 seconds
Started Apr 04 02:02:58 PM PDT 24
Finished Apr 04 02:03:04 PM PDT 24
Peak memory 191660 kb
Host smart-6386f9d5-f09a-4dc0-84d5-a1f00b9dd4a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=680277549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.680277549
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.161923824
Short name T855
Test name
Test status
Simulation time 79880664 ps
CPU time 1.02 seconds
Started Apr 04 02:03:01 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 197792 kb
Host smart-62904d2c-3c35-4a07-af3a-c6dafae04257
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161923824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.161923824
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1933015851
Short name T878
Test name
Test status
Simulation time 50564504 ps
CPU time 1 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191616 kb
Host smart-9ec7129c-2430-4cc5-b3ff-2cba19fceb47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1933015851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1933015851
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1503726056
Short name T912
Test name
Test status
Simulation time 309565781 ps
CPU time 1.18 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:08 PM PDT 24
Peak memory 197428 kb
Host smart-fe4d0ac2-4b92-4b4b-96b5-4f03873c6d09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503726056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1503726056
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3885357236
Short name T853
Test name
Test status
Simulation time 56808824 ps
CPU time 1.03 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191460 kb
Host smart-c270d65f-2dd3-480c-9fce-2686daa075c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3885357236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3885357236
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012580202
Short name T862
Test name
Test status
Simulation time 279924859 ps
CPU time 1.18 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191548 kb
Host smart-7cbaf8bd-c69a-4c9b-98df-0cda99167b7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012580202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3012580202
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3863156554
Short name T919
Test name
Test status
Simulation time 270100417 ps
CPU time 1.01 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 197912 kb
Host smart-404096d6-6b9f-44f8-926b-dd8b7b6b23aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3863156554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3863156554
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.223176425
Short name T882
Test name
Test status
Simulation time 80016105 ps
CPU time 1.05 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:08 PM PDT 24
Peak memory 191596 kb
Host smart-8498d13c-d268-4229-ab18-8f353f128b49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223176425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.223176425
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2344558916
Short name T871
Test name
Test status
Simulation time 1182342757 ps
CPU time 1.17 seconds
Started Apr 04 02:03:03 PM PDT 24
Finished Apr 04 02:03:08 PM PDT 24
Peak memory 191568 kb
Host smart-c5544647-2ccf-47a2-b94c-8a8be9ebaa20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2344558916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2344558916
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.108017336
Short name T858
Test name
Test status
Simulation time 64003154 ps
CPU time 1.25 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191656 kb
Host smart-d06916bc-42e0-4a5f-99b0-37d98f4e633e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108017336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.108017336
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.753415202
Short name T864
Test name
Test status
Simulation time 80231829 ps
CPU time 0.9 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 197112 kb
Host smart-afac1b17-9480-4689-826a-149c718bddd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=753415202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.753415202
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3455789870
Short name T852
Test name
Test status
Simulation time 71183677 ps
CPU time 0.88 seconds
Started Apr 04 02:02:59 PM PDT 24
Finished Apr 04 02:03:04 PM PDT 24
Peak memory 195992 kb
Host smart-969d6fd8-2426-46a0-b37a-a49892f4cd99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455789870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3455789870
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3937239717
Short name T854
Test name
Test status
Simulation time 384742192 ps
CPU time 1.34 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 196300 kb
Host smart-97f83645-648b-4ee9-8cd2-fe2b8c1e1fa7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3937239717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3937239717
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.410164913
Short name T857
Test name
Test status
Simulation time 269759424 ps
CPU time 1.43 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:13 PM PDT 24
Peak memory 191636 kb
Host smart-a5fa6e69-aeca-4ea7-b5d1-4d7457166386
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410164913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.410164913
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2670715681
Short name T868
Test name
Test status
Simulation time 102345689 ps
CPU time 1.38 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 197752 kb
Host smart-48276832-cc8f-469c-8c51-df009ba5d755
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2670715681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2670715681
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2476590416
Short name T874
Test name
Test status
Simulation time 80187741 ps
CPU time 1.22 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191636 kb
Host smart-e614bb9b-171c-4f53-9533-75b35bbb7e39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476590416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2476590416
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.937781562
Short name T888
Test name
Test status
Simulation time 266967876 ps
CPU time 1.16 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:13 PM PDT 24
Peak memory 197852 kb
Host smart-19bc5003-1c48-42e3-bca5-d6d7e738b282
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=937781562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.937781562
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.977319849
Short name T931
Test name
Test status
Simulation time 351383054 ps
CPU time 1.3 seconds
Started Apr 04 02:03:13 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 197744 kb
Host smart-2f7c07b5-c1e4-49ad-a8e0-38ebd28775c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977319849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.977319849
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2441829480
Short name T873
Test name
Test status
Simulation time 225963305 ps
CPU time 1.02 seconds
Started Apr 04 02:03:15 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191516 kb
Host smart-11dc7315-eb29-418f-b644-801ec2915748
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2441829480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2441829480
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3552073034
Short name T848
Test name
Test status
Simulation time 374230006 ps
CPU time 0.84 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191356 kb
Host smart-dd330f5d-9af3-462f-970f-ceec14392479
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552073034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3552073034
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1933260524
Short name T917
Test name
Test status
Simulation time 48326034 ps
CPU time 1.27 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191496 kb
Host smart-86af57ce-1a1c-49b3-8fe4-10e37758d21f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1933260524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1933260524
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2289273215
Short name T875
Test name
Test status
Simulation time 92086735 ps
CPU time 1.33 seconds
Started Apr 04 02:03:13 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191472 kb
Host smart-953cc7e9-8892-4bde-8fad-d80fe26af3af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289273215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2289273215
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.10281548
Short name T845
Test name
Test status
Simulation time 952868392 ps
CPU time 1.33 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 198024 kb
Host smart-60a32569-a5fa-4db8-bd6d-ec473d0f3992
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=10281548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.10281548
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.957628686
Short name T891
Test name
Test status
Simulation time 93669507 ps
CPU time 1.37 seconds
Started Apr 04 02:03:15 PM PDT 24
Finished Apr 04 02:03:17 PM PDT 24
Peak memory 191480 kb
Host smart-21b01faa-d06a-4f75-8913-0a89957b1232
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957628686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.957628686
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.538399260
Short name T903
Test name
Test status
Simulation time 317068048 ps
CPU time 1.42 seconds
Started Apr 04 02:03:01 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191612 kb
Host smart-cb3480d7-3169-43e7-b01c-7b5f40f3b4c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=538399260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.538399260
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128103256
Short name T861
Test name
Test status
Simulation time 177123000 ps
CPU time 1.25 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191580 kb
Host smart-72c6d4a5-794a-472d-9728-52db16b679ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128103256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2128103256
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.78168652
Short name T936
Test name
Test status
Simulation time 91168633 ps
CPU time 1 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:13 PM PDT 24
Peak memory 191560 kb
Host smart-6201ba2b-a412-4f50-82f1-06f648f81cff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=78168652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.78168652
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3591314938
Short name T929
Test name
Test status
Simulation time 78799019 ps
CPU time 0.78 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 196112 kb
Host smart-91f8fbb8-ad43-4f44-bf31-f2b552f50ddb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591314938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3591314938
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1871249394
Short name T939
Test name
Test status
Simulation time 167365181 ps
CPU time 1.17 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:13 PM PDT 24
Peak memory 191588 kb
Host smart-b0c3e71e-dff5-4627-bc84-1b432a53a368
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1871249394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1871249394
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2697580990
Short name T883
Test name
Test status
Simulation time 161138701 ps
CPU time 0.82 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:12 PM PDT 24
Peak memory 195984 kb
Host smart-12e43f60-b8f1-4f2e-a01a-7e6f51ddc756
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697580990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2697580990
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3629893615
Short name T880
Test name
Test status
Simulation time 87761730 ps
CPU time 0.84 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 196956 kb
Host smart-6240d021-53cc-4278-9975-364fc28973fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3629893615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3629893615
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1816196312
Short name T913
Test name
Test status
Simulation time 53653981 ps
CPU time 0.97 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:12 PM PDT 24
Peak memory 191576 kb
Host smart-33ed5038-2e44-4bdb-a2e4-c8b776832147
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816196312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1816196312
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.184397782
Short name T872
Test name
Test status
Simulation time 49824857 ps
CPU time 1.3 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191572 kb
Host smart-83f65867-82a6-4da6-b090-fa40e056b148
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=184397782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.184397782
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2199734037
Short name T914
Test name
Test status
Simulation time 58300572 ps
CPU time 1.51 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191600 kb
Host smart-95ca8a11-b1c3-43b9-9632-160f26c3ef6b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199734037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2199734037
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3642748939
Short name T899
Test name
Test status
Simulation time 117966531 ps
CPU time 1.35 seconds
Started Apr 04 02:03:15 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191580 kb
Host smart-18038291-2feb-400b-b92d-dd8eedaa6fc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3642748939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3642748939
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1364418979
Short name T877
Test name
Test status
Simulation time 264300009 ps
CPU time 1.26 seconds
Started Apr 04 02:03:15 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191644 kb
Host smart-da9c9a26-3141-4aee-871a-2f0d389dc67b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364418979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1364418979
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1681161550
Short name T866
Test name
Test status
Simulation time 49127174 ps
CPU time 0.9 seconds
Started Apr 04 02:03:16 PM PDT 24
Finished Apr 04 02:03:17 PM PDT 24
Peak memory 191540 kb
Host smart-8a8dd788-f4e6-4a53-8d5b-8c8731396178
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1681161550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1681161550
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2802818510
Short name T894
Test name
Test status
Simulation time 71597510 ps
CPU time 0.97 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:14 PM PDT 24
Peak memory 196240 kb
Host smart-062c3628-60b5-4001-bc42-816f646f2f6a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802818510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2802818510
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1657823167
Short name T916
Test name
Test status
Simulation time 49360914 ps
CPU time 1 seconds
Started Apr 04 02:03:11 PM PDT 24
Finished Apr 04 02:03:12 PM PDT 24
Peak memory 191504 kb
Host smart-818e9982-507e-4b14-b42d-c7dbbae20e09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1657823167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1657823167
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3324530829
Short name T863
Test name
Test status
Simulation time 86493213 ps
CPU time 1.35 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 197924 kb
Host smart-7847df28-bb0a-4d1c-97ae-2f344cd3aa18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324530829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3324530829
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3911678140
Short name T890
Test name
Test status
Simulation time 126603330 ps
CPU time 1.12 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191612 kb
Host smart-04d5fba0-95b2-40f6-a539-ecd34a9cd5b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3911678140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3911678140
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2022946540
Short name T889
Test name
Test status
Simulation time 85809447 ps
CPU time 1.07 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191624 kb
Host smart-64587550-1022-421c-823b-32b3e70a96bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022946540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2022946540
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.966350168
Short name T908
Test name
Test status
Simulation time 145317446 ps
CPU time 1.8 seconds
Started Apr 04 02:03:13 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191544 kb
Host smart-16a5da7e-1253-4295-8e33-e81ce1185442
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=966350168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.966350168
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1691459078
Short name T930
Test name
Test status
Simulation time 95904408 ps
CPU time 0.72 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:14 PM PDT 24
Peak memory 195924 kb
Host smart-bd619302-f591-4e70-81de-1c9b9c75b233
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691459078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1691459078
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2277784407
Short name T921
Test name
Test status
Simulation time 37690655 ps
CPU time 0.8 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191528 kb
Host smart-90f6c61d-8140-49c1-baf8-770d19c8323f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2277784407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2277784407
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3252877359
Short name T902
Test name
Test status
Simulation time 141233490 ps
CPU time 1.19 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 191460 kb
Host smart-e9410d23-582e-4075-abf3-86f2cc82bc4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252877359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3252877359
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.953404323
Short name T911
Test name
Test status
Simulation time 67422373 ps
CPU time 1.09 seconds
Started Apr 04 02:03:03 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191560 kb
Host smart-75758077-c865-4f50-bd38-ccbd6adfec19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=953404323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.953404323
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3175450319
Short name T897
Test name
Test status
Simulation time 247089124 ps
CPU time 1.13 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 197952 kb
Host smart-fb753729-6546-430c-910d-c61e4482950a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175450319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3175450319
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3400930123
Short name T923
Test name
Test status
Simulation time 69110484 ps
CPU time 1.23 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:15 PM PDT 24
Peak memory 191420 kb
Host smart-2397c004-2930-429b-8329-1dfdb90c5733
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3400930123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3400930123
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3340080559
Short name T904
Test name
Test status
Simulation time 139199558 ps
CPU time 0.87 seconds
Started Apr 04 02:03:12 PM PDT 24
Finished Apr 04 02:03:14 PM PDT 24
Peak memory 197916 kb
Host smart-d6efbb52-064e-47b2-91f5-344d827c8402
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340080559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3340080559
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1213102663
Short name T937
Test name
Test status
Simulation time 162459971 ps
CPU time 1.03 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 197376 kb
Host smart-2320251a-8842-4a58-83bc-d2a6555c3ec0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1213102663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1213102663
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3689336559
Short name T940
Test name
Test status
Simulation time 142165587 ps
CPU time 1.46 seconds
Started Apr 04 02:03:14 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 197900 kb
Host smart-fadf21cb-c66b-4838-ab5f-713e102d4cc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689336559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3689336559
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.543436261
Short name T898
Test name
Test status
Simulation time 24298204 ps
CPU time 0.69 seconds
Started Apr 04 02:03:15 PM PDT 24
Finished Apr 04 02:03:16 PM PDT 24
Peak memory 194872 kb
Host smart-0125cadc-e9dc-4c83-811a-0f685ab6960f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=543436261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.543436261
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.550383462
Short name T915
Test name
Test status
Simulation time 48143733 ps
CPU time 1 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191596 kb
Host smart-3f0327a9-71cf-4e28-a38a-4b78873c88eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550383462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.550383462
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.460249608
Short name T905
Test name
Test status
Simulation time 33903884 ps
CPU time 0.79 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:22 PM PDT 24
Peak memory 191520 kb
Host smart-44c3a5cd-0c4f-4f90-9d34-259089919242
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=460249608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.460249608
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2247564694
Short name T850
Test name
Test status
Simulation time 252659040 ps
CPU time 1.3 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191488 kb
Host smart-af9f62a5-d64b-4ec8-b42a-33ee837417fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247564694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2247564694
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3470929191
Short name T895
Test name
Test status
Simulation time 253651935 ps
CPU time 1.14 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191476 kb
Host smart-af7574a8-fff9-4bf9-8b17-5588d64b4e33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3470929191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3470929191
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2176488102
Short name T900
Test name
Test status
Simulation time 42933369 ps
CPU time 1.14 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191588 kb
Host smart-20072b58-35f4-495b-af97-c48297072796
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176488102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2176488102
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3160034584
Short name T907
Test name
Test status
Simulation time 77541124 ps
CPU time 1.19 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191572 kb
Host smart-ba6bbcdf-5a58-4a41-9285-4c532b2fa99c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3160034584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3160034584
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925307410
Short name T901
Test name
Test status
Simulation time 151558368 ps
CPU time 1.38 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:26 PM PDT 24
Peak memory 191652 kb
Host smart-ac2637cf-10fd-4f56-aad1-1e263ddf23ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925307410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.925307410
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.427192572
Short name T856
Test name
Test status
Simulation time 218686910 ps
CPU time 0.96 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 197864 kb
Host smart-3a21627e-0f1d-4633-9c3c-f6b581a78a62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=427192572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.427192572
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3120891676
Short name T933
Test name
Test status
Simulation time 122295685 ps
CPU time 0.91 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 191436 kb
Host smart-7f3bcec7-a91d-4345-a0c6-c0b8bef0c2fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120891676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3120891676
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.289470812
Short name T867
Test name
Test status
Simulation time 59194236 ps
CPU time 1.22 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 197832 kb
Host smart-10d1bc6d-4df9-4d68-b0b6-c61197c2c5b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289470812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.289470812
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3956531505
Short name T918
Test name
Test status
Simulation time 60701241 ps
CPU time 1.07 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 191624 kb
Host smart-b48c3973-cf19-48eb-a795-2fadd70085da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956531505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3956531505
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1473402841
Short name T943
Test name
Test status
Simulation time 46851353 ps
CPU time 1.1 seconds
Started Apr 04 02:03:21 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 191552 kb
Host smart-98076e68-36b5-49c3-9245-b8576ecf0d97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1473402841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1473402841
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3616103077
Short name T886
Test name
Test status
Simulation time 286334331 ps
CPU time 1.35 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 191588 kb
Host smart-5278729e-cc49-4496-942e-0d5fb825dfd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616103077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3616103077
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3486125403
Short name T844
Test name
Test status
Simulation time 31465628 ps
CPU time 0.81 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191484 kb
Host smart-0cba1e3f-8734-46b5-b4fd-fa7f6a5885d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3486125403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3486125403
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.596159408
Short name T922
Test name
Test status
Simulation time 255280062 ps
CPU time 1.13 seconds
Started Apr 04 02:03:28 PM PDT 24
Finished Apr 04 02:03:29 PM PDT 24
Peak memory 197508 kb
Host smart-17b93546-c276-4aa4-89b1-26886b1871d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596159408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.596159408
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2987336334
Short name T860
Test name
Test status
Simulation time 147076132 ps
CPU time 1.12 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191616 kb
Host smart-799ed3f7-2ae2-41f4-950c-71f1817ce19a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2987336334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2987336334
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2092555579
Short name T920
Test name
Test status
Simulation time 333404500 ps
CPU time 1.34 seconds
Started Apr 04 02:02:59 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191604 kb
Host smart-fd53fc02-8482-4325-9671-df689c9c85ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092555579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2092555579
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.180064634
Short name T934
Test name
Test status
Simulation time 172707650 ps
CPU time 0.67 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191416 kb
Host smart-3ca4057d-a803-4c3e-8c7e-5ae7ae8a2a00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=180064634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.180064634
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693944639
Short name T928
Test name
Test status
Simulation time 127421476 ps
CPU time 1.04 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:25 PM PDT 24
Peak memory 191600 kb
Host smart-8f3991a8-0488-452b-b269-5d4c582be551
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693944639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.693944639
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1200189938
Short name T926
Test name
Test status
Simulation time 23060390 ps
CPU time 0.71 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:23 PM PDT 24
Peak memory 195892 kb
Host smart-2fc5c601-b1e3-443f-9b19-12562a9db4c8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1200189938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1200189938
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3445357952
Short name T859
Test name
Test status
Simulation time 109444162 ps
CPU time 1.37 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191580 kb
Host smart-637cd6ae-f314-4dd6-81ce-ba94917a536d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445357952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3445357952
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1681402655
Short name T876
Test name
Test status
Simulation time 40791835 ps
CPU time 1.25 seconds
Started Apr 04 02:03:26 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191548 kb
Host smart-f3db2d2b-3a6b-40a5-b3d1-e5b0d93dc6b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1681402655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1681402655
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2232601322
Short name T932
Test name
Test status
Simulation time 69153589 ps
CPU time 1.15 seconds
Started Apr 04 02:03:22 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191612 kb
Host smart-3631cc8b-420a-4feb-9ccc-0c788253a7f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232601322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2232601322
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.87307093
Short name T892
Test name
Test status
Simulation time 86448439 ps
CPU time 1.29 seconds
Started Apr 04 02:03:26 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191548 kb
Host smart-c70c912d-4601-4a2b-927c-3b72fe242dca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=87307093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.87307093
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.522141611
Short name T846
Test name
Test status
Simulation time 279155820 ps
CPU time 0.91 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191608 kb
Host smart-09ee5071-c6af-45a2-b527-eb999c2eb75d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522141611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.522141611
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1500282115
Short name T870
Test name
Test status
Simulation time 159123848 ps
CPU time 0.84 seconds
Started Apr 04 02:03:28 PM PDT 24
Finished Apr 04 02:03:29 PM PDT 24
Peak memory 197308 kb
Host smart-fce407ad-0362-40a2-a782-29eff0517c2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1500282115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1500282115
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.362015453
Short name T847
Test name
Test status
Simulation time 81280796 ps
CPU time 0.92 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:25 PM PDT 24
Peak memory 197208 kb
Host smart-0bcd5335-b836-4d6c-89f0-404515a1b775
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362015453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.362015453
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1786212039
Short name T938
Test name
Test status
Simulation time 201489824 ps
CPU time 1.45 seconds
Started Apr 04 02:03:26 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191624 kb
Host smart-28acf1ef-bc1e-43e9-b6f4-a1ba11c14bdb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1786212039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1786212039
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.340892138
Short name T925
Test name
Test status
Simulation time 22028124 ps
CPU time 0.73 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:25 PM PDT 24
Peak memory 191512 kb
Host smart-5aa08c18-a991-4dd0-816e-6f8d783b0286
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340892138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.340892138
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3314450490
Short name T885
Test name
Test status
Simulation time 198813086 ps
CPU time 1.06 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:25 PM PDT 24
Peak memory 191572 kb
Host smart-87731320-d085-46f0-bcb9-7d5b565dbe63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3314450490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3314450490
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2440286544
Short name T909
Test name
Test status
Simulation time 359585049 ps
CPU time 1.1 seconds
Started Apr 04 02:03:26 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191620 kb
Host smart-c1e98713-bf96-48a4-9fcd-0714f979da09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440286544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2440286544
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.312181982
Short name T879
Test name
Test status
Simulation time 30637522 ps
CPU time 0.74 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 191372 kb
Host smart-2c07ae16-1648-4612-8910-7db92280e07b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=312181982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.312181982
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1360908790
Short name T851
Test name
Test status
Simulation time 216819219 ps
CPU time 1.12 seconds
Started Apr 04 02:03:26 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191564 kb
Host smart-c216e351-ab67-4061-ac0e-7bc2b119fe64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360908790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1360908790
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3814513883
Short name T869
Test name
Test status
Simulation time 115671184 ps
CPU time 0.89 seconds
Started Apr 04 02:03:25 PM PDT 24
Finished Apr 04 02:03:27 PM PDT 24
Peak memory 191548 kb
Host smart-e226a437-5514-42a6-91fb-656909cbfe0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3814513883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3814513883
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2569987766
Short name T924
Test name
Test status
Simulation time 206313131 ps
CPU time 0.97 seconds
Started Apr 04 02:03:23 PM PDT 24
Finished Apr 04 02:03:24 PM PDT 24
Peak memory 197780 kb
Host smart-2d5015e2-0f2c-4873-85e4-262d864cbe33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569987766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2569987766
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1153541576
Short name T935
Test name
Test status
Simulation time 144754645 ps
CPU time 1.03 seconds
Started Apr 04 02:03:24 PM PDT 24
Finished Apr 04 02:03:26 PM PDT 24
Peak memory 197896 kb
Host smart-1c2630e3-1f14-4104-abdf-bd8fb44b2d4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1153541576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1153541576
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2167108201
Short name T910
Test name
Test status
Simulation time 370073275 ps
CPU time 1 seconds
Started Apr 04 02:03:35 PM PDT 24
Finished Apr 04 02:03:36 PM PDT 24
Peak memory 197764 kb
Host smart-2d6d6aa1-2d83-43bc-bc01-2d67f853dd08
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167108201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2167108201
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3865960093
Short name T896
Test name
Test status
Simulation time 41658445 ps
CPU time 0.89 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:05 PM PDT 24
Peak memory 191432 kb
Host smart-607878c6-f01d-4f22-a609-d01ce0c7038e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3865960093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3865960093
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398645926
Short name T927
Test name
Test status
Simulation time 111067146 ps
CPU time 0.78 seconds
Started Apr 04 02:03:01 PM PDT 24
Finished Apr 04 02:03:05 PM PDT 24
Peak memory 196128 kb
Host smart-057cc3b7-0ec3-44da-8ad2-7247bf9b559b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398645926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3398645926
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2997973017
Short name T906
Test name
Test status
Simulation time 168179359 ps
CPU time 1.37 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191492 kb
Host smart-4c5eb8a3-e9b3-4bbb-a762-7d48ba3328bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2997973017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2997973017
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2653177491
Short name T881
Test name
Test status
Simulation time 56276103 ps
CPU time 1.11 seconds
Started Apr 04 02:03:02 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191624 kb
Host smart-be90c18a-bb89-4be7-aef9-d5cb0ab94c8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653177491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2653177491
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2533356756
Short name T865
Test name
Test status
Simulation time 460140920 ps
CPU time 0.96 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191464 kb
Host smart-18e2884c-924a-443d-a95d-77017a4f410f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2533356756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2533356756
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1126445691
Short name T893
Test name
Test status
Simulation time 296779903 ps
CPU time 1.08 seconds
Started Apr 04 02:02:59 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 197820 kb
Host smart-58faf4d8-3cf6-4fc7-89d7-a6a870b62171
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126445691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1126445691
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3418913360
Short name T941
Test name
Test status
Simulation time 186756563 ps
CPU time 0.69 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:05 PM PDT 24
Peak memory 194996 kb
Host smart-c5d9057a-cd91-48ec-9c34-a484a9252bcd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3418913360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3418913360
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1626475784
Short name T884
Test name
Test status
Simulation time 32147865 ps
CPU time 0.99 seconds
Started Apr 04 02:03:00 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191592 kb
Host smart-c438391a-3104-4c7b-89f5-b2467255e32f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626475784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1626475784
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2612211179
Short name T849
Test name
Test status
Simulation time 128448163 ps
CPU time 0.99 seconds
Started Apr 04 02:03:01 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191576 kb
Host smart-e0628b9f-632b-4682-b712-38d898daef1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2612211179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2612211179
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3737840981
Short name T887
Test name
Test status
Simulation time 272164240 ps
CPU time 1.05 seconds
Started Apr 04 02:03:03 PM PDT 24
Finished Apr 04 02:03:06 PM PDT 24
Peak memory 191544 kb
Host smart-74a38f35-60b4-40d0-b58c-e879e4bfee11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737840981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3737840981
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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