Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3443158	1			T25	1		T26	68		T27	1
all_pins[1]	3443158	1			T25	1		T26	68		T27	1
all_pins[2]	3443158	1			T25	1		T26	68		T27	1
all_pins[3]	3443158	1			T25	1		T26	68		T27	1
all_pins[4]	3443158	1			T25	1		T26	68		T27	1
all_pins[5]	3443158	1			T25	1		T26	68		T27	1
all_pins[6]	3443158	1			T25	1		T26	68		T27	1
all_pins[7]	3443158	1			T25	1		T26	68		T27	1
all_pins[8]	3443158	1			T25	1		T26	68		T27	1
all_pins[9]	3443158	1			T25	1		T26	68		T27	1
all_pins[10]	3443158	1			T25	1		T26	68		T27	1
all_pins[11]	3443158	1			T25	1		T26	68		T27	1
all_pins[12]	3443158	1			T25	1		T26	68		T27	1
all_pins[13]	3443158	1			T25	1		T26	68		T27	1
all_pins[14]	3443158	1			T25	1		T26	68		T27	1
all_pins[15]	3443158	1			T25	1		T26	68		T27	1
all_pins[16]	3443158	1			T25	1		T26	68		T27	1
all_pins[17]	3443158	1			T25	1		T26	68		T27	1
all_pins[18]	3443158	1			T25	1		T26	68		T27	1
all_pins[19]	3443158	1			T25	1		T26	68		T27	1
all_pins[20]	3443158	1			T25	1		T26	68		T27	1
all_pins[21]	3443158	1			T25	1		T26	68		T27	1
all_pins[22]	3443158	1			T25	1		T26	68		T27	1
all_pins[23]	3443158	1			T25	1		T26	68		T27	1
all_pins[24]	3443158	1			T25	1		T26	68		T27	1
all_pins[25]	3443158	1			T25	1		T26	68		T27	1
all_pins[26]	3443158	1			T25	1		T26	68		T27	1
all_pins[27]	3443158	1			T25	1		T26	68		T27	1
all_pins[28]	3443158	1			T25	1		T26	68		T27	1
all_pins[29]	3443158	1			T25	1		T26	68		T27	1
all_pins[30]	3443158	1			T25	1		T26	68		T27	1
all_pins[31]	3443158	1			T25	1		T26	68		T27	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	68404766	1			T25	32		T26	1182		T27	32
values[0x1]	41776290	1			T26	994		T29	344		T30	4383
transitions[0x0=>0x1]	25018894	1			T26	531		T29	205		T30	2646
transitions[0x1=>0x0]	25018749	1			T26	531		T29	205		T30	2645

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2138175	1			T25	1		T26	34		T27	1
all_pins[0]	values[0x1]	1304983	1			T26	34		T29	9		T30	117
all_pins[0]	transitions[0x0=>0x1]	806684	1			T26	19		T29	6		T30	57
all_pins[0]	transitions[0x1=>0x0]	811640	1			T26	17		T29	11		T30	111
all_pins[1]	values[0x0]	2142413	1			T25	1		T26	38		T27	1
all_pins[1]	values[0x1]	1300745	1			T26	30		T29	16		T30	153
all_pins[1]	transitions[0x0=>0x1]	778954	1			T26	14		T29	9		T30	115
all_pins[1]	transitions[0x1=>0x0]	783192	1			T26	18		T29	2		T30	79
all_pins[2]	values[0x0]	2138529	1			T25	1		T26	44		T27	1
all_pins[2]	values[0x1]	1304629	1			T26	24		T29	13		T30	116
all_pins[2]	transitions[0x0=>0x1]	781571	1			T26	12		T29	3		T30	54
all_pins[2]	transitions[0x1=>0x0]	777687	1			T26	18		T29	6		T30	91
all_pins[3]	values[0x0]	2134092	1			T25	1		T26	44		T27	1
all_pins[3]	values[0x1]	1309066	1			T26	24		T29	10		T30	162
all_pins[3]	transitions[0x0=>0x1]	782468	1			T26	16		T29	5		T30	113
all_pins[3]	transitions[0x1=>0x0]	778031	1			T26	16		T29	8		T30	67
all_pins[4]	values[0x0]	2137772	1			T25	1		T26	37		T27	1
all_pins[4]	values[0x1]	1305386	1			T26	31		T29	3		T30	154
all_pins[4]	transitions[0x0=>0x1]	779114	1			T26	21		T29	2		T30	75
all_pins[4]	transitions[0x1=>0x0]	782794	1			T26	14		T29	9		T30	83
all_pins[5]	values[0x0]	2139672	1			T25	1		T26	39		T27	1
all_pins[5]	values[0x1]	1303486	1			T26	29		T29	15		T30	171
all_pins[5]	transitions[0x0=>0x1]	780923	1			T26	20		T29	12		T30	90
all_pins[5]	transitions[0x1=>0x0]	782823	1			T26	22		T30	73		T32	20
all_pins[6]	values[0x0]	2135497	1			T25	1		T26	36		T27	1
all_pins[6]	values[0x1]	1307661	1			T26	32		T29	14		T30	120
all_pins[6]	transitions[0x0=>0x1]	781805	1			T26	14		T29	9		T30	67
all_pins[6]	transitions[0x1=>0x0]	777630	1			T26	11		T29	10		T30	118
all_pins[7]	values[0x0]	2140520	1			T25	1		T26	39		T27	1
all_pins[7]	values[0x1]	1302638	1			T26	29		T29	16		T30	135
all_pins[7]	transitions[0x0=>0x1]	778068	1			T26	15		T29	8		T30	96
all_pins[7]	transitions[0x1=>0x0]	783091	1			T26	18		T29	6		T30	81
all_pins[8]	values[0x0]	2135500	1			T25	1		T26	37		T27	1
all_pins[8]	values[0x1]	1307658	1			T26	31		T29	14		T30	154
all_pins[8]	transitions[0x0=>0x1]	782747	1			T26	17		T29	6		T30	107
all_pins[8]	transitions[0x1=>0x0]	777727	1			T26	15		T29	8		T30	88
all_pins[9]	values[0x0]	2137627	1			T25	1		T26	22		T27	1
all_pins[9]	values[0x1]	1305531	1			T26	46		T29	7		T30	122
all_pins[9]	transitions[0x0=>0x1]	780277	1			T26	23		T29	2		T30	74
all_pins[9]	transitions[0x1=>0x0]	782404	1			T26	8		T29	9		T30	106
all_pins[10]	values[0x0]	2135458	1			T25	1		T26	37		T27	1
all_pins[10]	values[0x1]	1307700	1			T26	31		T29	14		T30	177
all_pins[10]	transitions[0x0=>0x1]	782565	1			T26	11		T29	12		T30	127
all_pins[10]	transitions[0x1=>0x0]	780396	1			T26	26		T29	5		T30	72
all_pins[11]	values[0x0]	2136135	1			T25	1		T26	38		T27	1
all_pins[11]	values[0x1]	1307023	1			T26	30		T29	8		T30	129
all_pins[11]	transitions[0x0=>0x1]	783840	1			T26	17		T29	4		T30	53
all_pins[11]	transitions[0x1=>0x0]	784517	1			T26	18		T29	10		T30	101
all_pins[12]	values[0x0]	2132766	1			T25	1		T26	40		T27	1
all_pins[12]	values[0x1]	1310392	1			T26	28		T29	12		T30	133
all_pins[12]	transitions[0x0=>0x1]	783005	1			T26	15		T29	7		T30	78
all_pins[12]	transitions[0x1=>0x0]	779636	1			T26	17		T29	3		T30	74
all_pins[13]	values[0x0]	2137385	1			T25	1		T26	36		T27	1
all_pins[13]	values[0x1]	1305773	1			T26	32		T29	10		T30	130
all_pins[13]	transitions[0x0=>0x1]	778069	1			T26	18		T29	4		T30	65
all_pins[13]	transitions[0x1=>0x0]	782688	1			T26	14		T29	6		T30	68
all_pins[14]	values[0x0]	2138911	1			T25	1		T26	39		T27	1
all_pins[14]	values[0x1]	1304247	1			T26	29		T29	13		T30	156
all_pins[14]	transitions[0x0=>0x1]	779870	1			T26	19		T29	8		T30	108
all_pins[14]	transitions[0x1=>0x0]	781396	1			T26	22		T29	5		T30	82
all_pins[15]	values[0x0]	2140700	1			T25	1		T26	39		T27	1
all_pins[15]	values[0x1]	1302458	1			T26	29		T29	11		T30	111
all_pins[15]	transitions[0x0=>0x1]	779005	1			T26	17		T29	3		T30	72
all_pins[15]	transitions[0x1=>0x0]	780794	1			T26	17		T29	5		T30	117
all_pins[16]	values[0x0]	2140130	1			T25	1		T26	40		T27	1
all_pins[16]	values[0x1]	1303028	1			T26	28		T29	10		T30	129
all_pins[16]	transitions[0x0=>0x1]	782901	1			T26	16		T29	6		T30	79
all_pins[16]	transitions[0x1=>0x0]	782331	1			T26	17		T29	7		T30	61
all_pins[17]	values[0x0]	2139289	1			T25	1		T26	42		T27	1
all_pins[17]	values[0x1]	1303869	1			T26	26		T29	9		T30	112
all_pins[17]	transitions[0x0=>0x1]	779088	1			T26	16		T29	7		T30	81
all_pins[17]	transitions[0x1=>0x0]	778247	1			T26	18		T29	8		T30	98
all_pins[18]	values[0x0]	2139883	1			T25	1		T26	34		T27	1
all_pins[18]	values[0x1]	1303275	1			T26	34		T29	8		T30	109
all_pins[18]	transitions[0x0=>0x1]	781706	1			T26	21		T29	5		T30	70
all_pins[18]	transitions[0x1=>0x0]	782300	1			T26	13		T29	6		T30	73
all_pins[19]	values[0x0]	2134155	1			T25	1		T26	31		T27	1
all_pins[19]	values[0x1]	1309003	1			T26	37		T29	5		T30	161
all_pins[19]	transitions[0x0=>0x1]	782741	1			T26	16		T29	4		T30	128
all_pins[19]	transitions[0x1=>0x0]	777013	1			T26	13		T29	7		T30	76
all_pins[20]	values[0x0]	2140911	1			T25	1		T26	41		T27	1
all_pins[20]	values[0x1]	1302247	1			T26	27		T29	16		T30	156
all_pins[20]	transitions[0x0=>0x1]	776259	1			T26	13		T29	15		T30	74
all_pins[20]	transitions[0x1=>0x0]	783015	1			T26	23		T29	4		T30	79
all_pins[21]	values[0x0]	2138224	1			T25	1		T26	29		T27	1
all_pins[21]	values[0x1]	1304934	1			T26	39		T29	11		T30	118
all_pins[21]	transitions[0x0=>0x1]	783224	1			T26	24		T29	4		T30	65
all_pins[21]	transitions[0x1=>0x0]	780537	1			T26	12		T29	9		T30	103
all_pins[22]	values[0x0]	2136093	1			T25	1		T26	38		T27	1
all_pins[22]	values[0x1]	1307065	1			T26	30		T29	7		T30	91
all_pins[22]	transitions[0x0=>0x1]	783002	1			T26	13		T29	4		T30	65
all_pins[22]	transitions[0x1=>0x0]	780871	1			T26	22		T29	8		T30	92
all_pins[23]	values[0x0]	2140003	1			T25	1		T26	34		T27	1
all_pins[23]	values[0x1]	1303155	1			T26	34		T29	8		T30	144
all_pins[23]	transitions[0x0=>0x1]	779619	1			T26	16		T29	6		T30	115
all_pins[23]	transitions[0x1=>0x0]	783529	1			T26	12		T29	5		T30	62
all_pins[24]	values[0x0]	2137226	1			T25	1		T26	39		T27	1
all_pins[24]	values[0x1]	1305932	1			T26	29		T29	15		T30	163
all_pins[24]	transitions[0x0=>0x1]	781362	1			T26	10		T29	8		T30	91
all_pins[24]	transitions[0x1=>0x0]	778585	1			T26	15		T29	1		T30	72
all_pins[25]	values[0x0]	2139185	1			T25	1		T26	33		T27	1
all_pins[25]	values[0x1]	1303973	1			T26	35		T29	5		T30	157
all_pins[25]	transitions[0x0=>0x1]	778219	1			T26	20		T29	3		T30	87
all_pins[25]	transitions[0x1=>0x0]	780178	1			T26	14		T29	13		T30	93
all_pins[26]	values[0x0]	2138674	1			T25	1		T26	36		T27	1
all_pins[26]	values[0x1]	1304484	1			T26	32		T29	9		T30	120
all_pins[26]	transitions[0x0=>0x1]	781763	1			T26	13		T29	5		T30	59
all_pins[26]	transitions[0x1=>0x0]	781252	1			T26	16		T29	1		T30	96
all_pins[27]	values[0x0]	2136712	1			T25	1		T26	40		T27	1
all_pins[27]	values[0x1]	1306446	1			T26	28		T29	8		T30	96
all_pins[27]	transitions[0x0=>0x1]	782743	1			T26	16		T29	4		T30	50
all_pins[27]	transitions[0x1=>0x0]	780781	1			T26	20		T29	5		T30	74
all_pins[28]	values[0x0]	2138162	1			T25	1		T26	38		T27	1
all_pins[28]	values[0x1]	1304996	1			T26	30		T29	14		T30	136
all_pins[28]	transitions[0x0=>0x1]	782013	1			T26	13		T29	10		T30	80
all_pins[28]	transitions[0x1=>0x0]	783463	1			T26	11		T29	4		T30	40
all_pins[29]	values[0x0]	2134977	1			T25	1		T26	35		T27	1
all_pins[29]	values[0x1]	1308181	1			T26	33		T29	11		T30	118
all_pins[29]	transitions[0x0=>0x1]	784208	1			T26	21		T29	8		T30	62
all_pins[29]	transitions[0x1=>0x0]	781023	1			T26	18		T29	11		T30	80
all_pins[30]	values[0x0]	2136916	1			T25	1		T26	37		T27	1
all_pins[30]	values[0x1]	1306242	1			T26	31		T29	9		T30	161
all_pins[30]	transitions[0x0=>0x1]	778297	1			T26	14		T29	5		T30	96
all_pins[30]	transitions[0x1=>0x0]	780236	1			T26	16		T29	7		T30	53
all_pins[31]	values[0x0]	2133074	1			T25	1		T26	36		T27	1
all_pins[31]	values[0x1]	1310084	1			T26	32		T29	14		T30	172
all_pins[31]	transitions[0x0=>0x1]	782784	1			T26	21		T29	11		T30	93
all_pins[31]	transitions[0x1=>0x0]	778942	1			T26	20		T29	6		T30	82