Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11954528	1			T25	342		T26	1119		T27	465
all_values[1]	11954528	1			T25	342		T26	1119		T27	465
all_values[2]	11954528	1			T25	342		T26	1119		T27	465
all_values[3]	11954528	1			T25	342		T26	1119		T27	465
all_values[4]	11954528	1			T25	342		T26	1119		T27	465
all_values[5]	11954528	1			T25	342		T26	1119		T27	465
all_values[6]	11954528	1			T25	342		T26	1119		T27	465
all_values[7]	11954528	1			T25	342		T26	1119		T27	465
all_values[8]	11954528	1			T25	342		T26	1119		T27	465
all_values[9]	11954528	1			T25	342		T26	1119		T27	465
all_values[10]	11954528	1			T25	342		T26	1119		T27	465
all_values[11]	11954528	1			T25	342		T26	1119		T27	465
all_values[12]	11954528	1			T25	342		T26	1119		T27	465
all_values[13]	11954528	1			T25	342		T26	1119		T27	465
all_values[14]	11954528	1			T25	342		T26	1119		T27	465
all_values[15]	11954528	1			T25	342		T26	1119		T27	465
all_values[16]	11954528	1			T25	342		T26	1119		T27	465
all_values[17]	11954528	1			T25	342		T26	1119		T27	465
all_values[18]	11954528	1			T25	342		T26	1119		T27	465
all_values[19]	11954528	1			T25	342		T26	1119		T27	465
all_values[20]	11954528	1			T25	342		T26	1119		T27	465
all_values[21]	11954528	1			T25	342		T26	1119		T27	465
all_values[22]	11954528	1			T25	342		T26	1119		T27	465
all_values[23]	11954528	1			T25	342		T26	1119		T27	465
all_values[24]	11954528	1			T25	342		T26	1119		T27	465
all_values[25]	11954528	1			T25	342		T26	1119		T27	465
all_values[26]	11954528	1			T25	342		T26	1119		T27	465
all_values[27]	11954528	1			T25	342		T26	1119		T27	465
all_values[28]	11954528	1			T25	342		T26	1119		T27	465
all_values[29]	11954528	1			T25	342		T26	1119		T27	465
all_values[30]	11954528	1			T25	342		T26	1119		T27	465
all_values[31]	11954528	1			T25	342		T26	1119		T27	465

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

226205138

1

T25

10944

T26

35808

T27

14880

auto[1]

156339758

1

T30

14495

T34

1557

T1

180528

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

99670229

1

T25

10944

T26

35808

T27

14880

auto[1]

282874667

1

T30

25260

T34

2332

T1

329205

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

378469639

1

T25

10944

T26

35808

T27

14880

auto[1]

4075257

1

T30

1075

T1

45415

T19

1814

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2639712	1			T25	342		T26	1119		T27	465
all_values[0]	auto[0]	auto[0]	auto[1]	4384088	1			T30	385		T34	40		T1	51223
all_values[0]	auto[0]	auto[1]	auto[0]	464788	1			T30	73		T34	1		T1	5411
all_values[0]	auto[0]	auto[1]	auto[1]	4338615	1			T30	310		T34	38		T1	49945
all_values[0]	auto[1]	auto[0]	auto[1]	63547	1			T30	13		T1	688		T19	36
all_values[0]	auto[1]	auto[1]	auto[1]	63778	1			T30	16		T1	717		T19	19
all_values[1]	auto[0]	auto[0]	auto[0]	2644560	1			T25	342		T26	1119		T27	465
all_values[1]	auto[0]	auto[0]	auto[1]	4380112	1			T30	345		T34	24		T1	52751
all_values[1]	auto[0]	auto[1]	auto[0]	466344	1			T30	23		T34	1		T1	4834
all_values[1]	auto[0]	auto[1]	auto[1]	4336505	1			T30	407		T34	58		T1	49062
all_values[1]	auto[1]	auto[0]	auto[1]	64119	1			T30	11		T1	742		T19	21
all_values[1]	auto[1]	auto[1]	auto[1]	62888	1			T30	26		T1	678		T19	32
all_values[2]	auto[0]	auto[0]	auto[0]	2641368	1			T25	342		T26	1119		T27	465
all_values[2]	auto[0]	auto[0]	auto[1]	4349783	1			T30	377		T34	27		T1	51187
all_values[2]	auto[0]	auto[1]	auto[0]	469837	1			T30	82		T34	1		T1	4736
all_values[2]	auto[0]	auto[1]	auto[1]	4366125	1			T30	328		T34	52		T1	51239
all_values[2]	auto[1]	auto[0]	auto[1]	63919	1			T30	18		T1	713		T19	32
all_values[2]	auto[1]	auto[1]	auto[1]	63496	1			T30	25		T1	720		T19	30
all_values[3]	auto[0]	auto[0]	auto[0]	2645132	1			T25	342		T26	1119		T27	465
all_values[3]	auto[0]	auto[0]	auto[1]	4336998	1			T30	344		T34	32		T1	51480
all_values[3]	auto[0]	auto[1]	auto[0]	476046	1			T30	42		T1	5122		T11	22
all_values[3]	auto[0]	auto[1]	auto[1]	4368869	1			T30	429		T34	44		T1	49653
all_values[3]	auto[1]	auto[0]	auto[1]	63656	1			T30	15		T1	707		T19	30
all_values[3]	auto[1]	auto[1]	auto[1]	63827	1			T30	15		T1	650		T19	32
all_values[4]	auto[0]	auto[0]	auto[0]	2649149	1			T25	342		T26	1119		T27	465
all_values[4]	auto[0]	auto[0]	auto[1]	4342932	1			T30	331		T34	43		T1	50020
all_values[4]	auto[0]	auto[1]	auto[0]	476114	1			T30	106		T1	5593		T11	12
all_values[4]	auto[0]	auto[1]	auto[1]	4358944	1			T30	397		T34	33		T1	51140
all_values[4]	auto[1]	auto[0]	auto[1]	64187	1			T30	19		T1	758		T19	34
all_values[4]	auto[1]	auto[1]	auto[1]	63202	1			T30	16		T1	687		T19	26
all_values[5]	auto[0]	auto[0]	auto[0]	2645964	1			T25	342		T26	1119		T27	465
all_values[5]	auto[0]	auto[0]	auto[1]	4353629	1			T30	355		T34	23		T1	52486
all_values[5]	auto[0]	auto[1]	auto[0]	480945	1			T30	50		T34	5		T1	4838
all_values[5]	auto[0]	auto[1]	auto[1]	4346316	1			T30	448		T34	50		T1	49512
all_values[5]	auto[1]	auto[0]	auto[1]	63617	1			T30	15		T1	665		T19	28
all_values[5]	auto[1]	auto[1]	auto[1]	64057	1			T30	17		T1	770		T19	26
all_values[6]	auto[0]	auto[0]	auto[0]	2640352	1			T25	342		T26	1119		T27	465
all_values[6]	auto[0]	auto[0]	auto[1]	4357893	1			T30	417		T34	19		T1	51529
all_values[6]	auto[0]	auto[1]	auto[0]	476929	1			T30	39		T34	1		T1	5095
all_values[6]	auto[0]	auto[1]	auto[1]	4352097	1			T30	337		T34	54		T1	50035
all_values[6]	auto[1]	auto[0]	auto[1]	63834	1			T30	22		T1	697		T19	19
all_values[6]	auto[1]	auto[1]	auto[1]	63423	1			T30	15		T1	736		T19	35
all_values[7]	auto[0]	auto[0]	auto[0]	2650175	1			T25	342		T26	1119		T27	465
all_values[7]	auto[0]	auto[0]	auto[1]	4361247	1			T30	383		T34	12		T1	49283
all_values[7]	auto[0]	auto[1]	auto[0]	473448	1			T30	43		T34	21		T1	4988
all_values[7]	auto[0]	auto[1]	auto[1]	4342412	1			T30	411		T34	41		T1	51921
all_values[7]	auto[1]	auto[0]	auto[1]	63913	1			T30	14		T1	710		T19	18
all_values[7]	auto[1]	auto[1]	auto[1]	63333	1			T30	24		T1	656		T19	30
all_values[8]	auto[0]	auto[0]	auto[0]	2651220	1			T25	342		T26	1119		T27	465
all_values[8]	auto[0]	auto[0]	auto[1]	4344849	1			T30	368		T34	17		T1	49934
all_values[8]	auto[0]	auto[1]	auto[0]	472405	1			T30	58		T34	15		T1	4997
all_values[8]	auto[0]	auto[1]	auto[1]	4358436	1			T30	403		T34	48		T1	51344
all_values[8]	auto[1]	auto[0]	auto[1]	63984	1			T30	19		T1	717		T19	30
all_values[8]	auto[1]	auto[1]	auto[1]	63634	1			T30	19		T1	673		T19	33
all_values[9]	auto[0]	auto[0]	auto[0]	2644531	1			T25	342		T26	1119		T27	465
all_values[9]	auto[0]	auto[0]	auto[1]	4360955	1			T30	405		T34	47		T1	51580
all_values[9]	auto[0]	auto[1]	auto[0]	469817	1			T30	69		T34	7		T1	4842
all_values[9]	auto[0]	auto[1]	auto[1]	4351381	1			T30	340		T34	30		T1	50262
all_values[9]	auto[1]	auto[0]	auto[1]	64279	1			T30	20		T1	716		T19	39
all_values[9]	auto[1]	auto[1]	auto[1]	63565	1			T30	14		T1	727		T19	14
all_values[10]	auto[0]	auto[0]	auto[0]	2641565	1			T25	342		T26	1119		T27	465
all_values[10]	auto[0]	auto[0]	auto[1]	4337952	1			T30	335		T34	55		T1	51482
all_values[10]	auto[0]	auto[1]	auto[0]	466971	1			T30	57		T34	4		T1	4827
all_values[10]	auto[0]	auto[1]	auto[1]	4380812	1			T30	458		T34	24		T1	50195
all_values[10]	auto[1]	auto[0]	auto[1]	63703	1			T30	18		T1	739		T19	29
all_values[10]	auto[1]	auto[1]	auto[1]	63525	1			T30	20		T1	688		T19	24
all_values[11]	auto[0]	auto[0]	auto[0]	2633352	1			T25	342		T26	1119		T27	465
all_values[11]	auto[0]	auto[0]	auto[1]	4358642	1			T30	375		T34	45		T1	50559
all_values[11]	auto[0]	auto[1]	auto[0]	474110	1			T30	44		T34	7		T1	4750
all_values[11]	auto[0]	auto[1]	auto[1]	4361197	1			T30	423		T34	23		T1	51580
all_values[11]	auto[1]	auto[0]	auto[1]	63542	1			T30	19		T1	725		T19	31
all_values[11]	auto[1]	auto[1]	auto[1]	63685	1			T30	17		T1	702		T19	37
all_values[12]	auto[0]	auto[0]	auto[0]	2639762	1			T25	342		T26	1119		T27	465
all_values[12]	auto[0]	auto[0]	auto[1]	4363814	1			T30	412		T34	23		T1	51864
all_values[12]	auto[0]	auto[1]	auto[0]	466735	1			T30	44		T34	3		T1	5358
all_values[12]	auto[0]	auto[1]	auto[1]	4356898	1			T30	388		T34	52		T1	49170
all_values[12]	auto[1]	auto[0]	auto[1]	64045	1			T30	20		T1	721		T19	37
all_values[12]	auto[1]	auto[1]	auto[1]	63274	1			T30	14		T1	737		T19	17
all_values[13]	auto[0]	auto[0]	auto[0]	2632949	1			T25	342		T26	1119		T27	465
all_values[13]	auto[0]	auto[0]	auto[1]	4362113	1			T30	429		T34	41		T1	50420
all_values[13]	auto[0]	auto[1]	auto[0]	472011	1			T30	83		T1	5262		T11	8
all_values[13]	auto[0]	auto[1]	auto[1]	4359941	1			T30	328		T34	35		T1	50882
all_values[13]	auto[1]	auto[0]	auto[1]	63904	1			T30	8		T1	679		T19	27
all_values[13]	auto[1]	auto[1]	auto[1]	63610	1			T30	15		T1	742		T19	25
all_values[14]	auto[0]	auto[0]	auto[0]	2641797	1			T25	342		T26	1119		T27	465
all_values[14]	auto[0]	auto[0]	auto[1]	4394472	1			T30	302		T34	22		T1	50620
all_values[14]	auto[0]	auto[1]	auto[0]	462750	1			T30	55		T34	20		T1	5048
all_values[14]	auto[0]	auto[1]	auto[1]	4327967	1			T30	442		T34	35		T1	51488
all_values[14]	auto[1]	auto[0]	auto[1]	63877	1			T30	15		T1	713		T19	34
all_values[14]	auto[1]	auto[1]	auto[1]	63665	1			T30	15		T1	717		T19	30
all_values[15]	auto[0]	auto[0]	auto[0]	2639773	1			T25	342		T26	1119		T27	465
all_values[15]	auto[0]	auto[0]	auto[1]	4352288	1			T30	367		T34	50		T1	49095
all_values[15]	auto[0]	auto[1]	auto[0]	476622	1			T30	94		T34	5		T1	5682
all_values[15]	auto[0]	auto[1]	auto[1]	4358418	1			T30	329		T34	26		T1	51838
all_values[15]	auto[1]	auto[0]	auto[1]	64096	1			T30	16		T1	676		T19	27
all_values[15]	auto[1]	auto[1]	auto[1]	63331	1			T30	18		T1	749		T19	32
all_values[16]	auto[0]	auto[0]	auto[0]	2639536	1			T25	342		T26	1119		T27	465
all_values[16]	auto[0]	auto[0]	auto[1]	4385176	1			T30	481		T34	35		T1	51162
all_values[16]	auto[0]	auto[1]	auto[0]	476661	1			T30	53		T34	5		T1	5059
all_values[16]	auto[0]	auto[1]	auto[1]	4325838	1			T30	303		T34	39		T1	50580
all_values[16]	auto[1]	auto[0]	auto[1]	63744	1			T30	26		T1	743		T19	22
all_values[16]	auto[1]	auto[1]	auto[1]	63573	1			T30	9		T1	671		T19	33
all_values[17]	auto[0]	auto[0]	auto[0]	2634313	1			T25	342		T26	1119		T27	465
all_values[17]	auto[0]	auto[0]	auto[1]	4391994	1			T30	387		T34	23		T1	50052
all_values[17]	auto[0]	auto[1]	auto[0]	470190	1			T30	68		T34	12		T1	5181
all_values[17]	auto[0]	auto[1]	auto[1]	4330587	1			T30	322		T34	49		T1	51301
all_values[17]	auto[1]	auto[0]	auto[1]	63571	1			T30	22		T1	660		T19	29
all_values[17]	auto[1]	auto[1]	auto[1]	63873	1			T30	13		T1	738		T19	31
all_values[18]	auto[0]	auto[0]	auto[0]	2643613	1			T25	342		T26	1119		T27	465
all_values[18]	auto[0]	auto[0]	auto[1]	4386045	1			T30	423		T34	40		T1	50938
all_values[18]	auto[0]	auto[1]	auto[0]	466495	1			T30	63		T34	12		T1	5180
all_values[18]	auto[0]	auto[1]	auto[1]	4331554	1			T30	318		T34	25		T1	50408
all_values[18]	auto[1]	auto[0]	auto[1]	64015	1			T30	21		T1	778		T19	27
all_values[18]	auto[1]	auto[1]	auto[1]	62806	1			T30	14		T1	690		T19	28
all_values[19]	auto[0]	auto[0]	auto[0]	2647266	1			T25	342		T26	1119		T27	465
all_values[19]	auto[0]	auto[0]	auto[1]	4347586	1			T30	402		T34	22		T1	50155
all_values[19]	auto[0]	auto[1]	auto[0]	470656	1			T30	20		T34	10		T1	5409
all_values[19]	auto[0]	auto[1]	auto[1]	4361529	1			T30	416		T34	46		T1	50979
all_values[19]	auto[1]	auto[0]	auto[1]	63991	1			T30	13		T1	725		T19	29
all_values[19]	auto[1]	auto[1]	auto[1]	63500	1			T30	14		T1	699		T19	28
all_values[20]	auto[0]	auto[0]	auto[0]	2637598	1			T25	342		T26	1119		T27	465
all_values[20]	auto[0]	auto[0]	auto[1]	4377948	1			T30	314		T34	35		T1	51307
all_values[20]	auto[0]	auto[1]	auto[0]	467155	1			T30	63		T34	2		T1	5148
all_values[20]	auto[0]	auto[1]	auto[1]	4344402	1			T30	434		T34	29		T1	50368
all_values[20]	auto[1]	auto[0]	auto[1]	63928	1			T30	14		T1	693		T19	23
all_values[20]	auto[1]	auto[1]	auto[1]	63497	1			T30	20		T1	733		T19	30
all_values[21]	auto[0]	auto[0]	auto[0]	2639147	1			T25	342		T26	1119		T27	465
all_values[21]	auto[0]	auto[0]	auto[1]	4365243	1			T30	461		T34	36		T1	49506
all_values[21]	auto[0]	auto[1]	auto[0]	473200	1			T30	44		T34	9		T1	4866
all_values[21]	auto[0]	auto[1]	auto[1]	4349743	1			T30	305		T34	36		T1	52636
all_values[21]	auto[1]	auto[0]	auto[1]	64006	1			T30	27		T1	751		T19	18
all_values[21]	auto[1]	auto[1]	auto[1]	63189	1			T30	7		T1	720		T19	37
all_values[22]	auto[0]	auto[0]	auto[0]	2640008	1			T25	342		T26	1119		T27	465
all_values[22]	auto[0]	auto[0]	auto[1]	4370927	1			T30	427		T34	37		T1	51623
all_values[22]	auto[0]	auto[1]	auto[0]	477741	1			T30	74		T34	5		T1	5542
all_values[22]	auto[0]	auto[1]	auto[1]	4338279	1			T30	265		T34	43		T1	49625
all_values[22]	auto[1]	auto[0]	auto[1]	64003	1			T30	15		T1	683		T19	27
all_values[22]	auto[1]	auto[1]	auto[1]	63570	1			T30	18		T1	751		T19	33
all_values[23]	auto[0]	auto[0]	auto[0]	2636065	1			T25	342		T26	1119		T27	465
all_values[23]	auto[0]	auto[0]	auto[1]	4374947	1			T30	312		T34	24		T1	51098
all_values[23]	auto[0]	auto[1]	auto[0]	470318	1			T30	72		T34	6		T1	5358
all_values[23]	auto[0]	auto[1]	auto[1]	4345638	1			T30	423		T34	55		T1	49571
all_values[23]	auto[1]	auto[0]	auto[1]	63741	1			T30	14		T1	714		T19	42
all_values[23]	auto[1]	auto[1]	auto[1]	63819	1			T30	20		T1	693		T19	29
all_values[24]	auto[0]	auto[0]	auto[0]	2642817	1			T25	342		T26	1119		T27	465
all_values[24]	auto[0]	auto[0]	auto[1]	4372790	1			T30	373		T34	10		T1	49759
all_values[24]	auto[0]	auto[1]	auto[0]	477567	1			T30	10		T34	12		T1	5577
all_values[24]	auto[0]	auto[1]	auto[1]	4333686	1			T30	436		T34	62		T1	50775
all_values[24]	auto[1]	auto[0]	auto[1]	63705	1			T30	18		T1	672		T19	25
all_values[24]	auto[1]	auto[1]	auto[1]	63963	1			T30	17		T1	755		T19	26
all_values[25]	auto[0]	auto[0]	auto[0]	2640931	1			T25	342		T26	1119		T27	465
all_values[25]	auto[0]	auto[0]	auto[1]	4361932	1			T30	261		T34	18		T1	52477
all_values[25]	auto[0]	auto[1]	auto[0]	475387	1			T30	72		T34	16		T1	5058
all_values[25]	auto[0]	auto[1]	auto[1]	4349150	1			T30	461		T34	44		T1	49408
all_values[25]	auto[1]	auto[0]	auto[1]	64033	1			T30	10		T1	738		T19	28
all_values[25]	auto[1]	auto[1]	auto[1]	63095	1			T30	22		T1	669		T19	28
all_values[26]	auto[0]	auto[0]	auto[0]	2650622	1			T25	342		T26	1119		T27	465
all_values[26]	auto[0]	auto[0]	auto[1]	4364976	1			T30	402		T34	22		T1	50801
all_values[26]	auto[0]	auto[1]	auto[0]	474381	1			T30	51		T34	6		T1	5624
all_values[26]	auto[0]	auto[1]	auto[1]	4337140	1			T30	341		T34	53		T1	50369
all_values[26]	auto[1]	auto[0]	auto[1]	63648	1			T30	17		T1	688		T19	29
all_values[26]	auto[1]	auto[1]	auto[1]	63761	1			T30	14		T1	716		T19	25
all_values[27]	auto[0]	auto[0]	auto[0]	2642460	1			T25	342		T26	1119		T27	465
all_values[27]	auto[0]	auto[0]	auto[1]	4361032	1			T30	440		T34	19		T1	52373
all_values[27]	auto[0]	auto[1]	auto[0]	474939	1			T30	71		T34	10		T1	5307
all_values[27]	auto[0]	auto[1]	auto[1]	4348967	1			T30	291		T34	57		T1	48867
all_values[27]	auto[1]	auto[0]	auto[1]	63951	1			T30	15		T1	710		T19	34
all_values[27]	auto[1]	auto[1]	auto[1]	63179	1			T30	12		T1	672		T19	23
all_values[28]	auto[0]	auto[0]	auto[0]	2648812	1			T25	342		T26	1119		T27	465
all_values[28]	auto[0]	auto[0]	auto[1]	4354716	1			T30	380		T34	39		T1	51892
all_values[28]	auto[0]	auto[1]	auto[0]	477320	1			T30	32		T34	7		T1	4779
all_values[28]	auto[0]	auto[1]	auto[1]	4346644	1			T30	406		T34	37		T1	49988
all_values[28]	auto[1]	auto[0]	auto[1]	63635	1			T30	12		T1	677		T19	16
all_values[28]	auto[1]	auto[1]	auto[1]	63401	1			T30	24		T1	747		T19	34
all_values[29]	auto[0]	auto[0]	auto[0]	2639374	1			T25	342		T26	1119		T27	465
all_values[29]	auto[0]	auto[0]	auto[1]	4357883	1			T30	422		T34	27		T1	50114
all_values[29]	auto[0]	auto[1]	auto[0]	473041	1			T30	86		T34	3		T1	5392
all_values[29]	auto[0]	auto[1]	auto[1]	4357200	1			T30	327		T34	48		T1	51054
all_values[29]	auto[1]	auto[0]	auto[1]	63588	1			T30	15		T1	701		T19	29
all_values[29]	auto[1]	auto[1]	auto[1]	63442	1			T30	16		T1	721		T19	28
all_values[30]	auto[0]	auto[0]	auto[0]	2641530	1			T25	342		T26	1119		T27	465
all_values[30]	auto[0]	auto[0]	auto[1]	4355051	1			T30	326		T34	47		T1	48642
all_values[30]	auto[0]	auto[1]	auto[0]	471882	1			T30	47		T34	3		T1	5329
all_values[30]	auto[0]	auto[1]	auto[1]	4358852	1			T30	447		T34	29		T1	52193
all_values[30]	auto[1]	auto[0]	auto[1]	63843	1			T30	17		T1	666		T19	28
all_values[30]	auto[1]	auto[1]	auto[1]	63370	1			T30	18		T1	714		T19	27
all_values[31]	auto[0]	auto[0]	auto[0]	2644616	1			T25	342		T26	1119		T27	465
all_values[31]	auto[0]	auto[0]	auto[1]	4341446	1			T30	333		T34	32		T1	51799
all_values[31]	auto[0]	auto[1]	auto[0]	477355	1			T30	56		T34	2		T1	4971
all_values[31]	auto[0]	auto[1]	auto[1]	4363809	1			T30	438		T34	51		T1	50039
all_values[31]	auto[1]	auto[0]	auto[1]	63986	1			T30	17		T1	754		T19	27
all_values[31]	auto[1]	auto[1]	auto[1]	63316	1			T30	16		T1	658		T19	27

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal