Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[1]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[2]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[3]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[4]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[5]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[6]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[7]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[8]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[9]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[10]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[11]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[12]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[13]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[14]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[15]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[16]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[17]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[18]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[19]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[20]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[21]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[22]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[23]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[24]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[25]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[26]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[27]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[28]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[29]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[30]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[31]	11792992	1			T25	666		T26	1119		T27	811

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223728065

1

T25

4587

T26

17936

T27

18456

auto[1]

153647679

1

T25

16725

T26

17872

T27

7496

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304759522

1

T25

16119

T26

35808

T27

14699

auto[1]

72616222

1

T25

5193

T27

11253

T30

11577

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283359488

1

T25

10355

T26

35808

T27

14953

auto[1]

94016256

1

T25

10957

T27

10999

T30

13948

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4403018	1			T25	31		T26	550		T27	229
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3307313	1			T25	224		T26	569		T27	59
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1141121	1			T25	70		T27	192		T30	143
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1439327	1			T25	38		T27	147		T30	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	365816	1			T25	238		T30	266		T1	19159
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1136397	1			T25	65		T27	184		T30	196
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4404153	1			T25	28		T26	573		T27	222
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3308109	1			T25	239		T26	546		T27	52
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1141718	1			T25	99		T27	145		T30	189
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1440330	1			T25	37		T27	192		T30	18
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	366867	1			T25	172		T30	276		T31	18
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1131815	1			T25	91		T27	200		T30	174
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4403442	1			T25	37		T26	570		T27	287
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3308671	1			T25	236		T26	549		T27	57
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1140184	1			T25	77		T27	187		T30	142
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1437933	1			T25	34		T27	146		T30	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	367372	1			T25	205		T30	295		T31	20
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1135390	1			T25	77		T27	134		T30	171
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4414502	1			T25	23		T26	599		T27	244
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3297203	1			T25	252		T26	520		T27	66
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1144907	1			T25	91		T27	142		T30	154
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1436312	1			T25	32		T27	205		T30	20
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	367376	1			T25	178		T30	256		T31	23
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1132692	1			T25	90		T27	154		T30	195
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4405907	1			T25	19		T26	515		T27	251
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3303820	1			T25	259		T26	604		T27	57
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1142216	1			T25	102		T27	175		T30	204
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1440264	1			T25	26		T27	150		T30	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	368439	1			T25	185		T30	214		T31	30
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1132346	1			T25	75		T27	178		T30	158
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4408955	1			T25	23		T26	579		T27	241
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3301481	1			T25	176		T26	540		T27	53
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1143274	1			T25	59		T27	178		T30	151
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1440946	1			T25	50		T27	161		T30	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	367102	1			T25	273		T30	284		T31	35
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1131234	1			T25	85		T27	178		T30	162
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4399767	1			T25	9		T26	551		T27	236
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3307753	1			T25	120		T26	568		T27	56
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1139182	1			T25	66		T27	163		T30	169
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1445638	1			T25	50		T27	170		T30	13
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	369763	1			T25	318		T30	226		T31	51
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1130889	1			T25	103		T27	186		T30	229
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4420326	1			T25	21		T26	608		T27	217
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3299058	1			T25	218		T26	511		T27	57
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1141226	1			T25	82		T27	190		T30	247
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1436649	1			T25	42		T27	180		T30	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	367869	1			T25	221		T30	140		T31	39
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1127864	1			T25	82		T27	167		T30	134
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4401507	1			T25	27		T26	639		T27	271
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3304198	1			T25	241		T26	480		T27	59
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1144008	1			T25	101		T27	126		T30	190
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1441919	1			T25	25		T27	177		T30	15
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	367852	1			T25	199		T30	299		T31	27
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1133508	1			T25	73		T27	178		T30	134
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4411182	1			T25	47		T26	581		T27	234
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3301280	1			T25	224		T26	538		T27	46
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1143520	1			T25	83		T27	212		T30	217
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1440799	1			T25	18		T27	150		T30	15
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	367321	1			T25	204		T30	159		T31	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1128890	1			T25	90		T27	169		T30	115
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4401677	1			T25	17		T26	501		T27	278
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3310360	1			T25	205		T26	618		T27	64
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1143466	1			T25	51		T27	189		T30	171
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1439474	1			T25	45		T27	132		T30	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	365528	1			T25	262		T30	239		T31	29
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1132487	1			T25	86		T27	148		T30	228
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4412541	1			T25	38		T26	577		T27	205
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3300319	1			T25	213		T26	542		T27	63
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1133644	1			T25	105		T27	155		T30	209
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1444801	1			T25	13		T27	174		T30	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	368821	1			T25	216		T30	161		T31	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1132866	1			T25	81		T27	214		T30	175
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4415626	1			T25	46		T26	555		T27	218
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3299654	1			T25	265		T26	564		T27	52
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1140366	1			T25	97		T27	214		T30	170
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1439052	1			T25	18		T27	156		T30	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	366004	1			T25	172		T30	223		T31	33
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1132290	1			T25	68		T27	171		T30	205
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4414920	1			T25	36		T26	581		T27	233
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3303973	1			T25	164		T26	538		T27	57
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1140137	1			T25	80		T27	198		T30	138
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1438888	1			T25	38		T27	177		T30	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	366414	1			T25	232		T30	254		T31	41
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1128660	1			T25	116		T27	146		T30	241
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4391547	1			T25	31		T26	590		T27	245
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3315076	1			T25	237		T26	529		T27	61
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1140909	1			T25	91		T27	190		T30	180
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1440757	1			T25	28		T27	145		T30	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	366663	1			T25	208		T30	218		T31	31
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1138040	1			T25	71		T27	170		T30	205
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4408381	1			T25	40		T26	529		T27	230
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3311110	1			T25	253		T26	590		T27	57
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1144963	1			T25	123		T27	188		T30	155
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1439778	1			T25	21		T27	148		T30	8
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	366091	1			T25	208		T30	293		T31	40
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1122669	1			T25	21		T27	188		T30	169
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4410405	1			T25	27		T26	601		T27	269
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3306773	1			T25	215		T26	518		T27	59
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1138957	1			T25	72		T27	160		T30	194
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1441786	1			T25	25		T27	158		T30	12
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	368788	1			T25	251		T30	196		T31	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1126283	1			T25	76		T27	165		T30	228
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4413514	1			T25	22		T26	538		T27	216
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3300763	1			T25	201		T26	581		T27	54
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1140069	1			T25	72		T27	138		T30	77
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1440649	1			T25	50		T27	208		T30	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	369879	1			T25	215		T30	341		T31	39
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1128118	1			T25	106		T27	195		T30	293
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4414300	1			T25	21		T26	575		T27	226
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3301057	1			T25	214		T26	544		T27	76
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1137085	1			T25	71		T27	154		T30	208
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1443267	1			T25	39		T27	193		T30	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	369354	1			T25	248		T30	260		T31	19
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1127929	1			T25	73		T27	162		T30	194
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4405931	1			T25	17		T26	533		T27	226
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3305807	1			T25	153		T26	586		T27	50
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1140775	1			T25	71		T27	163		T30	156
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1445341	1			T25	39		T27	170		T30	14
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	368391	1			T25	303		T30	292		T1	18974
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1126747	1			T25	83		T27	202		T30	147
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4408753	1			T25	16		T26	539		T27	232
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3307548	1			T25	217		T26	580		T27	55
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1137415	1			T25	61		T27	176		T30	166
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1441796	1			T25	47		T27	180		T30	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	368719	1			T25	238		T30	242		T31	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1128761	1			T25	87		T27	168		T30	136
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4412384	1			T25	26		T26	527		T27	216
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3299177	1			T25	210		T26	592		T27	61
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1133858	1			T25	102		T27	190		T30	211
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1447300	1			T25	26		T27	166		T30	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	369459	1			T25	218		T30	196		T31	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1130814	1			T25	84		T27	178		T30	106
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4422969	1			T25	23		T26	601		T27	205
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3305537	1			T25	245		T26	518		T27	53
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1135579	1			T25	84		T27	181		T30	135
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1438410	1			T25	39		T27	172		T30	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	367431	1			T25	214		T30	272		T31	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1123066	1			T25	61		T27	200		T30	187
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4407649	1			T25	28		T26	542		T27	250
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3312761	1			T25	225		T26	577		T27	57
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1140669	1			T25	63		T27	156		T30	211
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1442953	1			T25	28		T27	160		T30	17
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	366011	1			T25	237		T30	274		T31	47
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1122949	1			T25	85		T27	188		T30	141
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4411881	1			T25	36		T26	570		T27	229
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3304114	1			T25	211		T26	549		T27	53
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1140724	1			T25	106		T27	226		T30	192
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1443008	1			T25	28		T27	141		T30	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	367516	1			T25	219		T30	210		T31	25
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1125749	1			T25	66		T27	162		T30	224
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4403189	1			T25	26		T26	587		T27	227
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3311583	1			T25	208		T26	532		T27	61
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1132197	1			T25	70		T27	187		T30	150
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1448372	1			T25	43		T27	170		T30	17
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	369978	1			T25	212		T30	338		T31	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1127673	1			T25	107		T27	166		T30	211
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4426101	1			T25	34		T26	542		T27	227
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3295635	1			T25	246		T26	577		T27	63
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1140140	1			T25	79		T27	142		T30	201
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1438933	1			T25	33		T27	197		T30	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	367308	1			T25	220		T30	268		T31	22
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1124875	1			T25	54		T27	182		T30	136
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4414252	1			T25	25		T26	598		T27	194
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3305592	1			T25	192		T26	521		T27	62
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1143144	1			T25	78		T27	203		T30	206
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1434152	1			T25	22		T27	142		T30	18
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	367043	1			T25	271		T30	251		T31	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1128809	1			T25	78		T27	210		T30	152
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4411567	1			T25	24		T26	527		T27	216
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3299079	1			T25	182		T26	592		T27	66
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1140219	1			T25	68		T27	198		T30	170
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1442464	1			T25	32		T27	152		T30	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	368913	1			T25	259		T30	240		T31	42
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1130750	1			T25	101		T27	179		T30	185
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4422231	1			T25	35		T26	544		T27	209
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3300900	1			T25	235		T26	575		T27	59
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1141300	1			T25	83		T27	199		T30	274
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1437615	1			T25	30		T27	154		T30	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	366209	1			T25	238		T30	185		T31	37
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1124737	1			T25	45		T27	190		T30	135
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4418138	1			T25	40		T26	518		T27	229
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3303900	1			T25	232		T26	601		T27	63
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1137132	1			T25	99		T27	148		T30	149
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1439160	1			T25	25		T27	211		T30	21
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	367899	1			T25	182		T30	262		T31	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1126763	1			T25	88		T27	160		T30	264
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4411080	1			T25	19		T26	496		T27	252
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3306578	1			T25	123		T26	623		T27	58
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1137407	1			T25	72		T27	158		T30	278
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1446686	1			T25	46		T27	185		T30	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	368590	1			T25	309		T30	143		T31	37
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1122651	1			T25	97		T27	158		T30	140

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal