Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[1]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[2]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[3]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[4]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[5]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[6]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[7]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[8]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[9]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[10]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[11]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[12]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[13]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[14]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[15]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[16]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[17]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[18]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[19]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[20]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[21]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[22]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[23]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[24]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[25]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[26]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[27]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[28]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[29]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[30]	11792992	1			T25	666		T26	1119		T27	811
bins_for_gpio_bits[31]	11792992	1			T25	666		T26	1119		T27	811

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223728065

1

T25

4587

T26

17936

T27

18456

auto[1]

153647679

1

T25

16725

T26

17872

T27

7496

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223719083

1

T25

4592

T26

17936

T27

18450

auto[1]

153656661

1

T25

16720

T26

17872

T27

7502

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6779832	1			T25	127		T26	550		T27	525
bins_for_gpio_bits[0]	auto[0]	auto[1]	203343	1			T25	12		T27	43		T30	24
bins_for_gpio_bits[0]	auto[1]	auto[0]	203634	1			T25	12		T27	43		T30	24
bins_for_gpio_bits[0]	auto[1]	auto[1]	4606183	1			T25	515		T26	569		T27	200
bins_for_gpio_bits[1]	auto[0]	auto[0]	6783094	1			T25	147		T26	573		T27	509
bins_for_gpio_bits[1]	auto[0]	auto[1]	202806	1			T25	17		T27	50		T30	24
bins_for_gpio_bits[1]	auto[1]	auto[0]	203107	1			T25	17		T27	50		T30	24
bins_for_gpio_bits[1]	auto[1]	auto[1]	4603985	1			T25	485		T26	546		T27	202
bins_for_gpio_bits[2]	auto[0]	auto[0]	6777691	1			T25	133		T26	570		T27	581
bins_for_gpio_bits[2]	auto[0]	auto[1]	203619	1			T25	15		T27	39		T30	26
bins_for_gpio_bits[2]	auto[1]	auto[0]	203868	1			T25	15		T27	39		T30	26
bins_for_gpio_bits[2]	auto[1]	auto[1]	4607814	1			T25	503		T26	549		T27	152
bins_for_gpio_bits[3]	auto[0]	auto[0]	6792114	1			T25	127		T26	599		T27	554
bins_for_gpio_bits[3]	auto[0]	auto[1]	203342	1			T25	20		T27	37		T30	17
bins_for_gpio_bits[3]	auto[1]	auto[0]	203607	1			T25	19		T27	37		T30	17
bins_for_gpio_bits[3]	auto[1]	auto[1]	4593929	1			T25	500		T26	520		T27	183
bins_for_gpio_bits[4]	auto[0]	auto[0]	6785395	1			T25	131		T26	515		T27	532
bins_for_gpio_bits[4]	auto[0]	auto[1]	202726	1			T25	16		T27	44		T30	27
bins_for_gpio_bits[4]	auto[1]	auto[0]	202992	1			T25	16		T27	44		T30	27
bins_for_gpio_bits[4]	auto[1]	auto[1]	4601879	1			T25	503		T26	604		T27	191
bins_for_gpio_bits[5]	auto[0]	auto[0]	6789561	1			T25	121		T26	579		T27	529
bins_for_gpio_bits[5]	auto[0]	auto[1]	203307	1			T25	11		T27	51		T30	22
bins_for_gpio_bits[5]	auto[1]	auto[0]	203614	1			T25	11		T27	51		T30	22
bins_for_gpio_bits[5]	auto[1]	auto[1]	4596510	1			T25	523		T26	540		T27	180
bins_for_gpio_bits[6]	auto[0]	auto[0]	6781242	1			T25	115		T26	551		T27	527
bins_for_gpio_bits[6]	auto[0]	auto[1]	203100	1			T25	10		T27	42		T30	29
bins_for_gpio_bits[6]	auto[1]	auto[0]	203345	1			T25	10		T27	42		T30	29
bins_for_gpio_bits[6]	auto[1]	auto[1]	4605305	1			T25	531		T26	568		T27	200
bins_for_gpio_bits[7]	auto[0]	auto[0]	6795359	1			T25	128		T26	608		T27	539
bins_for_gpio_bits[7]	auto[0]	auto[1]	202583	1			T25	17		T27	47		T30	40
bins_for_gpio_bits[7]	auto[1]	auto[0]	202842	1			T25	17		T27	48		T30	40
bins_for_gpio_bits[7]	auto[1]	auto[1]	4592208	1			T25	504		T26	511		T27	177
bins_for_gpio_bits[8]	auto[0]	auto[0]	6783914	1			T25	134		T26	639		T27	528
bins_for_gpio_bits[8]	auto[0]	auto[1]	203195	1			T25	19		T27	46		T30	23
bins_for_gpio_bits[8]	auto[1]	auto[0]	203520	1			T25	19		T27	46		T30	23
bins_for_gpio_bits[8]	auto[1]	auto[1]	4602363	1			T25	494		T26	480		T27	191
bins_for_gpio_bits[9]	auto[0]	auto[0]	6792432	1			T25	135		T26	581		T27	554
bins_for_gpio_bits[9]	auto[0]	auto[1]	202800	1			T25	13		T27	41		T30	33
bins_for_gpio_bits[9]	auto[1]	auto[0]	203069	1			T25	13		T27	42		T30	33
bins_for_gpio_bits[9]	auto[1]	auto[1]	4594691	1			T25	505		T26	538		T27	174
bins_for_gpio_bits[10]	auto[0]	auto[0]	6781462	1			T25	101		T26	501		T27	564
bins_for_gpio_bits[10]	auto[0]	auto[1]	202894	1			T25	13		T27	35		T30	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	203155	1			T25	12		T27	35		T30	27
bins_for_gpio_bits[10]	auto[1]	auto[1]	4605481	1			T25	540		T26	618		T27	177
bins_for_gpio_bits[11]	auto[0]	auto[0]	6787626	1			T25	140		T26	577		T27	485
bins_for_gpio_bits[11]	auto[0]	auto[1]	203072	1			T25	16		T27	49		T30	30
bins_for_gpio_bits[11]	auto[1]	auto[0]	203360	1			T25	16		T27	49		T30	30
bins_for_gpio_bits[11]	auto[1]	auto[1]	4598934	1			T25	494		T26	542		T27	228
bins_for_gpio_bits[12]	auto[0]	auto[0]	6791626	1			T25	143		T26	555		T27	539
bins_for_gpio_bits[12]	auto[0]	auto[1]	203164	1			T25	18		T27	48		T30	23
bins_for_gpio_bits[12]	auto[1]	auto[0]	203418	1			T25	18		T27	49		T30	23
bins_for_gpio_bits[12]	auto[1]	auto[1]	4594784	1			T25	487		T26	564		T27	175
bins_for_gpio_bits[13]	auto[0]	auto[0]	6791000	1			T25	141		T26	581		T27	564
bins_for_gpio_bits[13]	auto[0]	auto[1]	202665	1			T25	13		T27	44		T30	26
bins_for_gpio_bits[13]	auto[1]	auto[0]	202945	1			T25	13		T27	44		T30	26
bins_for_gpio_bits[13]	auto[1]	auto[1]	4596382	1			T25	499		T26	538		T27	159
bins_for_gpio_bits[14]	auto[0]	auto[0]	6769428	1			T25	130		T26	590		T27	543
bins_for_gpio_bits[14]	auto[0]	auto[1]	203494	1			T25	20		T27	37		T30	34
bins_for_gpio_bits[14]	auto[1]	auto[0]	203785	1			T25	20		T27	37		T30	34
bins_for_gpio_bits[14]	auto[1]	auto[1]	4616285	1			T25	496		T26	529		T27	194
bins_for_gpio_bits[15]	auto[0]	auto[0]	6790393	1			T25	169		T26	529		T27	523
bins_for_gpio_bits[15]	auto[0]	auto[1]	202512	1			T25	15		T27	43		T30	22
bins_for_gpio_bits[15]	auto[1]	auto[0]	202729	1			T25	15		T27	43		T30	22
bins_for_gpio_bits[15]	auto[1]	auto[1]	4597358	1			T25	467		T26	590		T27	202
bins_for_gpio_bits[16]	auto[0]	auto[0]	6788155	1			T25	111		T26	601		T27	543
bins_for_gpio_bits[16]	auto[0]	auto[1]	202714	1			T25	13		T27	43		T30	28
bins_for_gpio_bits[16]	auto[1]	auto[0]	202993	1			T25	13		T27	44		T30	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	4599130	1			T25	529		T26	518		T27	181
bins_for_gpio_bits[17]	auto[0]	auto[0]	6791495	1			T25	131		T26	538		T27	518
bins_for_gpio_bits[17]	auto[0]	auto[1]	202452	1			T25	13		T27	43		T30	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	202737	1			T25	13		T27	44		T30	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	4596308	1			T25	509		T26	581		T27	206
bins_for_gpio_bits[18]	auto[0]	auto[0]	6792016	1			T25	116		T26	575		T27	535
bins_for_gpio_bits[18]	auto[0]	auto[1]	202366	1			T25	15		T27	38		T30	23
bins_for_gpio_bits[18]	auto[1]	auto[0]	202636	1			T25	15		T27	38		T30	23
bins_for_gpio_bits[18]	auto[1]	auto[1]	4595974	1			T25	520		T26	544		T27	200
bins_for_gpio_bits[19]	auto[0]	auto[0]	6788483	1			T25	115		T26	533		T27	509
bins_for_gpio_bits[19]	auto[0]	auto[1]	203293	1			T25	12		T27	50		T30	22
bins_for_gpio_bits[19]	auto[1]	auto[0]	203564	1			T25	12		T27	50		T30	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	4597652	1			T25	527		T26	586		T27	202
bins_for_gpio_bits[20]	auto[0]	auto[0]	6784639	1			T25	109		T26	539		T27	551
bins_for_gpio_bits[20]	auto[0]	auto[1]	203033	1			T25	15		T27	37		T30	27
bins_for_gpio_bits[20]	auto[1]	auto[0]	203325	1			T25	15		T27	37		T30	27
bins_for_gpio_bits[20]	auto[1]	auto[1]	4601995	1			T25	527		T26	580		T27	186
bins_for_gpio_bits[21]	auto[0]	auto[0]	6790133	1			T25	140		T26	527		T27	527
bins_for_gpio_bits[21]	auto[0]	auto[1]	203070	1			T25	14		T27	45		T30	33
bins_for_gpio_bits[21]	auto[1]	auto[0]	203409	1			T25	14		T27	45		T30	33
bins_for_gpio_bits[21]	auto[1]	auto[1]	4596380	1			T25	498		T26	592		T27	194
bins_for_gpio_bits[22]	auto[0]	auto[0]	6794459	1			T25	133		T26	601		T27	511
bins_for_gpio_bits[22]	auto[0]	auto[1]	202213	1			T25	13		T27	47		T30	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	202499	1			T25	13		T27	47		T30	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	4593821	1			T25	507		T26	518		T27	206
bins_for_gpio_bits[23]	auto[0]	auto[0]	6788476	1			T25	107		T26	542		T27	526
bins_for_gpio_bits[23]	auto[0]	auto[1]	202490	1			T25	12		T27	40		T30	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	202795	1			T25	12		T27	40		T30	28
bins_for_gpio_bits[23]	auto[1]	auto[1]	4599231	1			T25	535		T26	577		T27	205
bins_for_gpio_bits[24]	auto[0]	auto[0]	6792951	1			T25	151		T26	570		T27	552
bins_for_gpio_bits[24]	auto[0]	auto[1]	202401	1			T25	20		T27	44		T30	29
bins_for_gpio_bits[24]	auto[1]	auto[0]	202662	1			T25	19		T27	44		T30	29
bins_for_gpio_bits[24]	auto[1]	auto[1]	4594978	1			T25	476		T26	549		T27	171
bins_for_gpio_bits[25]	auto[0]	auto[0]	6780615	1			T25	126		T26	587		T27	542
bins_for_gpio_bits[25]	auto[0]	auto[1]	202861	1			T25	14		T27	42		T30	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	203143	1			T25	13		T27	42		T30	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	4606373	1			T25	513		T26	532		T27	185
bins_for_gpio_bits[26]	auto[0]	auto[0]	6802470	1			T25	129		T26	542		T27	523
bins_for_gpio_bits[26]	auto[0]	auto[1]	202415	1			T25	17		T27	43		T30	30
bins_for_gpio_bits[26]	auto[1]	auto[0]	202704	1			T25	17		T27	43		T30	30
bins_for_gpio_bits[26]	auto[1]	auto[1]	4585403	1			T25	503		T26	577		T27	202
bins_for_gpio_bits[27]	auto[0]	auto[0]	6788086	1			T25	110		T26	598		T27	491
bins_for_gpio_bits[27]	auto[0]	auto[1]	203170	1			T25	15		T27	48		T30	23
bins_for_gpio_bits[27]	auto[1]	auto[0]	203462	1			T25	15		T27	48		T30	23
bins_for_gpio_bits[27]	auto[1]	auto[1]	4598274	1			T25	526		T26	521		T27	224
bins_for_gpio_bits[28]	auto[0]	auto[0]	6789884	1			T25	108		T26	527		T27	520
bins_for_gpio_bits[28]	auto[0]	auto[1]	204091	1			T25	16		T27	45		T30	27
bins_for_gpio_bits[28]	auto[1]	auto[0]	204366	1			T25	16		T27	46		T30	27
bins_for_gpio_bits[28]	auto[1]	auto[1]	4594651	1			T25	526		T26	592		T27	200
bins_for_gpio_bits[29]	auto[0]	auto[0]	6797560	1			T25	134		T26	544		T27	512
bins_for_gpio_bits[29]	auto[0]	auto[1]	203310	1			T25	14		T27	50		T30	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	203586	1			T25	14		T27	50		T30	29
bins_for_gpio_bits[29]	auto[1]	auto[1]	4588536	1			T25	504		T26	575		T27	199
bins_for_gpio_bits[30]	auto[0]	auto[0]	6791642	1			T25	149		T26	518		T27	549
bins_for_gpio_bits[30]	auto[0]	auto[1]	202455	1			T25	16		T27	39		T30	20
bins_for_gpio_bits[30]	auto[1]	auto[0]	202788	1			T25	15		T27	39		T30	20
bins_for_gpio_bits[30]	auto[1]	auto[1]	4596107	1			T25	486		T26	601		T27	184
bins_for_gpio_bits[31]	auto[0]	auto[0]	6792284	1			T25	125		T26	496		T27	553
bins_for_gpio_bits[31]	auto[0]	auto[1]	202610	1			T25	12		T27	42		T30	34
bins_for_gpio_bits[31]	auto[1]	auto[0]	202889	1			T25	12		T27	42		T30	34
bins_for_gpio_bits[31]	auto[1]	auto[1]	4595209	1			T25	517		T26	623		T27	174