Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7088791 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4865737 |
1 |
|
|
T30 |
456 |
|
T34 |
59 |
|
T1 |
54574 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9927735 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
2026793 |
1 |
|
|
T30 |
304 |
|
T34 |
29 |
|
T1 |
34784 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7061079 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4893449 |
1 |
|
|
T30 |
392 |
|
T34 |
51 |
|
T1 |
58395 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1447200 |
1 |
|
|
T30 |
29 |
|
T34 |
6 |
|
T1 |
12388 |
| auto[1] |
auto[0] |
auto[1] |
1017451 |
1 |
|
|
T30 |
145 |
|
T34 |
3 |
|
T1 |
18111 |
| auto[1] |
auto[1] |
auto[0] |
1419456 |
1 |
|
|
T30 |
59 |
|
T34 |
16 |
|
T1 |
11223 |
| auto[1] |
auto[1] |
auto[1] |
1009342 |
1 |
|
|
T30 |
159 |
|
T34 |
26 |
|
T1 |
16673 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |