Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7056157 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4898371 |
1 |
|
|
T30 |
441 |
|
T34 |
31 |
|
T1 |
58269 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9929759 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
2024769 |
1 |
|
|
T30 |
340 |
|
T34 |
8 |
|
T1 |
31872 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7059221 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4895307 |
1 |
|
|
T30 |
431 |
|
T34 |
47 |
|
T1 |
53714 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1433964 |
1 |
|
|
T30 |
41 |
|
T34 |
28 |
|
T1 |
10955 |
| auto[1] |
auto[0] |
auto[1] |
1016803 |
1 |
|
|
T30 |
164 |
|
T34 |
6 |
|
T1 |
15929 |
| auto[1] |
auto[1] |
auto[0] |
1436574 |
1 |
|
|
T30 |
50 |
|
T34 |
11 |
|
T1 |
10887 |
| auto[1] |
auto[1] |
auto[1] |
1007966 |
1 |
|
|
T30 |
176 |
|
T34 |
2 |
|
T1 |
15943 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |