Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7093673 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4860855 |
1 |
|
|
T30 |
395 |
|
T34 |
37 |
|
T1 |
56278 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9925922 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
2028606 |
1 |
|
|
T30 |
377 |
|
T34 |
13 |
|
T1 |
34627 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7059015 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4895513 |
1 |
|
|
T30 |
472 |
|
T34 |
30 |
|
T1 |
57436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1454981 |
1 |
|
|
T30 |
41 |
|
T34 |
12 |
|
T1 |
11244 |
| auto[1] |
auto[0] |
auto[1] |
1028242 |
1 |
|
|
T30 |
212 |
|
T34 |
8 |
|
T1 |
17824 |
| auto[1] |
auto[1] |
auto[0] |
1411926 |
1 |
|
|
T30 |
54 |
|
T34 |
5 |
|
T1 |
11565 |
| auto[1] |
auto[1] |
auto[1] |
1000364 |
1 |
|
|
T30 |
165 |
|
T34 |
5 |
|
T1 |
16803 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |