Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079474 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4875054 |
1 |
|
|
T30 |
517 |
|
T34 |
31 |
|
T1 |
56249 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9944839 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
2009689 |
1 |
|
|
T30 |
294 |
|
T34 |
11 |
|
T1 |
33127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7115828 |
1 |
|
|
T25 |
342 |
|
T26 |
1119 |
|
T27 |
465 |
| auto[1] |
4838700 |
1 |
|
|
T30 |
365 |
|
T34 |
14 |
|
T1 |
55248 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1425909 |
1 |
|
|
T30 |
29 |
|
T34 |
1 |
|
T1 |
11099 |
| auto[1] |
auto[0] |
auto[1] |
1008907 |
1 |
|
|
T30 |
152 |
|
T1 |
17052 |
|
T11 |
12 |
| auto[1] |
auto[1] |
auto[0] |
1403102 |
1 |
|
|
T30 |
42 |
|
T34 |
2 |
|
T1 |
11022 |
| auto[1] |
auto[1] |
auto[1] |
1000782 |
1 |
|
|
T30 |
142 |
|
T34 |
11 |
|
T1 |
16075 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |