Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T93 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2732569974 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 14076861 ps
T762 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3996319314 Apr 15 12:20:04 PM PDT 24 Apr 15 12:20:05 PM PDT 24 16673380 ps
T47 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3700954922 Apr 15 12:19:30 PM PDT 24 Apr 15 12:19:31 PM PDT 24 352675364 ps
T113 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3254271308 Apr 15 12:19:42 PM PDT 24 Apr 15 12:19:44 PM PDT 24 248460436 ps
T763 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3067295665 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 31225543 ps
T764 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1361796515 Apr 15 12:20:58 PM PDT 24 Apr 15 12:21:01 PM PDT 24 486488823 ps
T765 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4198918696 Apr 15 12:19:47 PM PDT 24 Apr 15 12:19:50 PM PDT 24 59579380 ps
T50 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.185668259 Apr 15 12:19:40 PM PDT 24 Apr 15 12:19:42 PM PDT 24 413601558 ps
T103 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.216790822 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:55 PM PDT 24 66757828 ps
T766 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1664380552 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 14452625 ps
T767 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2688083879 Apr 15 12:20:19 PM PDT 24 Apr 15 12:20:22 PM PDT 24 42091363 ps
T768 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3775135208 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 32157453 ps
T769 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3892674310 Apr 15 12:19:41 PM PDT 24 Apr 15 12:19:42 PM PDT 24 13956272 ps
T770 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2810257537 Apr 15 12:19:22 PM PDT 24 Apr 15 12:19:23 PM PDT 24 224936418 ps
T771 /workspace/coverage/cover_reg_top/39.gpio_intr_test.997888500 Apr 15 12:19:54 PM PDT 24 Apr 15 12:19:57 PM PDT 24 14463543 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.870906233 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 23251590 ps
T773 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.577838297 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:56 PM PDT 24 104325789 ps
T774 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2340061353 Apr 15 12:19:49 PM PDT 24 Apr 15 12:19:51 PM PDT 24 13118731 ps
T775 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4051524977 Apr 15 12:19:32 PM PDT 24 Apr 15 12:19:33 PM PDT 24 18821569 ps
T776 /workspace/coverage/cover_reg_top/8.gpio_intr_test.1059775776 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:53 PM PDT 24 36229138 ps
T94 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2657686915 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 150788414 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1854298518 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 152177231 ps
T778 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.807883954 Apr 15 12:20:04 PM PDT 24 Apr 15 12:20:06 PM PDT 24 52416316 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3068192224 Apr 15 12:19:53 PM PDT 24 Apr 15 12:19:58 PM PDT 24 248870892 ps
T780 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1831410262 Apr 15 12:19:49 PM PDT 24 Apr 15 12:19:51 PM PDT 24 19408695 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1421139884 Apr 15 12:19:22 PM PDT 24 Apr 15 12:19:23 PM PDT 24 50255709 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2216525349 Apr 15 12:19:48 PM PDT 24 Apr 15 12:19:50 PM PDT 24 35820369 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4053514637 Apr 15 12:19:42 PM PDT 24 Apr 15 12:19:43 PM PDT 24 30173494 ps
T783 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2082361769 Apr 15 12:20:18 PM PDT 24 Apr 15 12:20:20 PM PDT 24 16287625 ps
T46 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3501725966 Apr 15 12:19:47 PM PDT 24 Apr 15 12:19:50 PM PDT 24 258365028 ps
T784 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2508982328 Apr 15 12:19:47 PM PDT 24 Apr 15 12:19:49 PM PDT 24 94259053 ps
T785 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1555568157 Apr 15 12:18:52 PM PDT 24 Apr 15 12:18:53 PM PDT 24 26743410 ps
T786 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2463822324 Apr 15 12:19:30 PM PDT 24 Apr 15 12:19:31 PM PDT 24 26810002 ps
T787 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1413664483 Apr 15 12:20:59 PM PDT 24 Apr 15 12:21:00 PM PDT 24 18685382 ps
T788 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2795260065 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:12 PM PDT 24 37690797 ps
T789 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3108149653 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:55 PM PDT 24 10251916 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2963845991 Apr 15 12:19:32 PM PDT 24 Apr 15 12:19:33 PM PDT 24 18896759 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1237075015 Apr 15 12:19:41 PM PDT 24 Apr 15 12:19:43 PM PDT 24 35485760 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2870707049 Apr 15 12:19:42 PM PDT 24 Apr 15 12:19:44 PM PDT 24 167945939 ps
T793 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1152942973 Apr 15 12:18:52 PM PDT 24 Apr 15 12:18:53 PM PDT 24 14244193 ps
T794 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2658085965 Apr 15 12:19:42 PM PDT 24 Apr 15 12:19:44 PM PDT 24 16939631 ps
T795 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3940330663 Apr 15 12:19:42 PM PDT 24 Apr 15 12:19:44 PM PDT 24 193123108 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2916527170 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:55 PM PDT 24 91800505 ps
T49 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2106535655 Apr 15 12:19:43 PM PDT 24 Apr 15 12:19:45 PM PDT 24 163397145 ps
T797 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4230400311 Apr 15 12:20:56 PM PDT 24 Apr 15 12:20:57 PM PDT 24 63306240 ps
T798 /workspace/coverage/cover_reg_top/23.gpio_intr_test.634683847 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 14688194 ps
T799 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1392227974 Apr 15 12:19:53 PM PDT 24 Apr 15 12:19:57 PM PDT 24 493174041 ps
T800 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1241921779 Apr 15 12:19:19 PM PDT 24 Apr 15 12:19:20 PM PDT 24 18701811 ps
T801 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.877256478 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:55 PM PDT 24 101130066 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1665741660 Apr 15 12:19:37 PM PDT 24 Apr 15 12:19:38 PM PDT 24 33149848 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_intr_test.533950061 Apr 15 12:19:49 PM PDT 24 Apr 15 12:19:51 PM PDT 24 11208736 ps
T804 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3499101712 Apr 15 12:19:52 PM PDT 24 Apr 15 12:19:55 PM PDT 24 326919042 ps
T805 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3535790724 Apr 15 12:19:55 PM PDT 24 Apr 15 12:19:59 PM PDT 24 336269016 ps
T806 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.644181152 Apr 15 12:19:58 PM PDT 24 Apr 15 12:20:00 PM PDT 24 1224159874 ps
T807 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.304490875 Apr 15 12:20:56 PM PDT 24 Apr 15 12:20:58 PM PDT 24 37252033 ps
T808 /workspace/coverage/cover_reg_top/11.gpio_intr_test.936505999 Apr 15 12:19:49 PM PDT 24 Apr 15 12:19:51 PM PDT 24 26441578 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1045281940 Apr 15 12:19:52 PM PDT 24 Apr 15 12:19:55 PM PDT 24 29405290 ps
T810 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3308522358 Apr 15 12:20:07 PM PDT 24 Apr 15 12:20:09 PM PDT 24 181841313 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.718579531 Apr 15 12:19:22 PM PDT 24 Apr 15 12:19:24 PM PDT 24 34400047 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3062827916 Apr 15 12:19:54 PM PDT 24 Apr 15 12:19:57 PM PDT 24 16081581 ps
T112 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2579230132 Apr 15 12:20:18 PM PDT 24 Apr 15 12:20:20 PM PDT 24 90438766 ps
T813 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2417212157 Apr 15 12:20:05 PM PDT 24 Apr 15 12:20:07 PM PDT 24 18478238 ps
T814 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.365187874 Apr 15 12:20:56 PM PDT 24 Apr 15 12:20:57 PM PDT 24 14365729 ps
T815 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3159573524 Apr 15 12:19:41 PM PDT 24 Apr 15 12:19:44 PM PDT 24 178783259 ps
T816 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3173256869 Apr 15 12:19:46 PM PDT 24 Apr 15 12:19:47 PM PDT 24 12507285 ps
T817 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1266469910 Apr 15 12:20:56 PM PDT 24 Apr 15 12:20:57 PM PDT 24 37876900 ps
T818 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1916957826 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:53 PM PDT 24 15517063 ps
T819 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.661008147 Apr 15 12:20:56 PM PDT 24 Apr 15 12:20:57 PM PDT 24 18886927 ps
T820 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1246565743 Apr 15 12:19:25 PM PDT 24 Apr 15 12:19:27 PM PDT 24 72791569 ps
T821 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1569659688 Apr 15 12:19:46 PM PDT 24 Apr 15 12:19:48 PM PDT 24 35288522 ps
T822 /workspace/coverage/cover_reg_top/13.gpio_intr_test.548082107 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 29991867 ps
T823 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2041790862 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 71114972 ps
T96 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1399311640 Apr 15 12:19:37 PM PDT 24 Apr 15 12:19:38 PM PDT 24 17674681 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1709502040 Apr 15 12:19:32 PM PDT 24 Apr 15 12:19:33 PM PDT 24 86929780 ps
T825 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1663553211 Apr 15 12:19:56 PM PDT 24 Apr 15 12:19:59 PM PDT 24 43370067 ps
T826 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.42372550 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:54 PM PDT 24 109212430 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3300339613 Apr 15 12:19:19 PM PDT 24 Apr 15 12:19:21 PM PDT 24 18736204 ps
T828 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2428659182 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:54 PM PDT 24 55007078 ps
T829 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2657955225 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:54 PM PDT 24 93864995 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2513272309 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:12 PM PDT 24 32051571 ps
T831 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2393054026 Apr 15 12:19:37 PM PDT 24 Apr 15 12:19:38 PM PDT 24 137679678 ps
T832 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.946159469 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:56 PM PDT 24 146742743 ps
T833 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1538669640 Apr 15 12:19:54 PM PDT 24 Apr 15 12:19:57 PM PDT 24 96060679 ps
T834 /workspace/coverage/cover_reg_top/40.gpio_intr_test.224307327 Apr 15 12:19:55 PM PDT 24 Apr 15 12:19:58 PM PDT 24 12349428 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1950168435 Apr 15 12:19:51 PM PDT 24 Apr 15 12:19:54 PM PDT 24 450141842 ps
T836 /workspace/coverage/cover_reg_top/41.gpio_intr_test.3553180468 Apr 15 12:19:50 PM PDT 24 Apr 15 12:19:53 PM PDT 24 33697275 ps
T837 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1876254356 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 13984237 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2957546916 Apr 15 12:19:48 PM PDT 24 Apr 15 12:19:51 PM PDT 24 15737244 ps
T839 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2114328797 Apr 15 12:19:48 PM PDT 24 Apr 15 12:19:52 PM PDT 24 470873923 ps
T840 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3407910520 Apr 15 12:19:47 PM PDT 24 Apr 15 12:19:49 PM PDT 24 17970574 ps
T841 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4182319779 Apr 15 12:17:02 PM PDT 24 Apr 15 12:17:03 PM PDT 24 31106504 ps
T842 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2923150280 Apr 15 12:19:06 PM PDT 24 Apr 15 12:19:08 PM PDT 24 265653304 ps
T843 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2300548021 Apr 15 12:18:48 PM PDT 24 Apr 15 12:18:50 PM PDT 24 150601240 ps
T844 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1042794162 Apr 15 12:19:31 PM PDT 24 Apr 15 12:19:33 PM PDT 24 44946357 ps
T845 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1967279432 Apr 15 12:18:51 PM PDT 24 Apr 15 12:18:53 PM PDT 24 136904695 ps
T846 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3632993065 Apr 15 12:19:44 PM PDT 24 Apr 15 12:19:47 PM PDT 24 20934872 ps
T847 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1946235679 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 84904586 ps
T848 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430478366 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 259430800 ps
T849 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124035449 Apr 15 12:19:19 PM PDT 24 Apr 15 12:19:21 PM PDT 24 83238870 ps
T850 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.944596223 Apr 15 12:18:57 PM PDT 24 Apr 15 12:18:59 PM PDT 24 67968869 ps
T851 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2088508286 Apr 15 12:19:12 PM PDT 24 Apr 15 12:19:14 PM PDT 24 86945057 ps
T852 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509792144 Apr 15 12:18:50 PM PDT 24 Apr 15 12:18:53 PM PDT 24 149974059 ps
T853 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4087197554 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 71576067 ps
T854 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2659217112 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:11 PM PDT 24 699054748 ps
T855 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966908724 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:08 PM PDT 24 72892606 ps
T856 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1515341522 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 93418400 ps
T857 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463169252 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:10 PM PDT 24 78929184 ps
T858 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466046610 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 108611813 ps
T859 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232240542 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:12 PM PDT 24 133887972 ps
T860 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1561814010 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 146533013 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2624625776 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:11 PM PDT 24 342337716 ps
T862 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3098835413 Apr 15 12:19:30 PM PDT 24 Apr 15 12:19:32 PM PDT 24 118089700 ps
T863 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2509724637 Apr 15 12:18:51 PM PDT 24 Apr 15 12:18:53 PM PDT 24 95444307 ps
T864 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1426243435 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 136309558 ps
T865 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243738869 Apr 15 12:19:08 PM PDT 24 Apr 15 12:19:09 PM PDT 24 76352305 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1579082762 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 49455253 ps
T867 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1326682584 Apr 15 12:18:59 PM PDT 24 Apr 15 12:19:01 PM PDT 24 344313555 ps
T868 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.338736815 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 113933200 ps
T869 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660558385 Apr 15 12:19:44 PM PDT 24 Apr 15 12:19:47 PM PDT 24 31503248 ps
T870 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.674898908 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:08 PM PDT 24 145670620 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3379563372 Apr 15 12:18:57 PM PDT 24 Apr 15 12:18:59 PM PDT 24 278429402 ps
T872 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1699634139 Apr 15 12:17:22 PM PDT 24 Apr 15 12:17:24 PM PDT 24 301600562 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1169433021 Apr 15 12:19:07 PM PDT 24 Apr 15 12:19:09 PM PDT 24 237054865 ps
T874 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2263591181 Apr 15 12:18:57 PM PDT 24 Apr 15 12:18:59 PM PDT 24 169648950 ps
T875 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.486274389 Apr 15 12:18:58 PM PDT 24 Apr 15 12:18:59 PM PDT 24 25435040 ps
T876 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4154869488 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:11 PM PDT 24 218296248 ps
T877 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3147484125 Apr 15 12:18:25 PM PDT 24 Apr 15 12:18:27 PM PDT 24 130440451 ps
T878 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2350032705 Apr 15 12:19:08 PM PDT 24 Apr 15 12:19:10 PM PDT 24 465748047 ps
T879 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2297036786 Apr 15 12:18:50 PM PDT 24 Apr 15 12:18:52 PM PDT 24 106381809 ps
T880 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2042398736 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 319353567 ps
T881 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2502966933 Apr 15 12:17:11 PM PDT 24 Apr 15 12:17:12 PM PDT 24 89233576 ps
T882 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3203714979 Apr 15 12:19:44 PM PDT 24 Apr 15 12:19:46 PM PDT 24 157910195 ps
T883 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744512061 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 78624906 ps
T884 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1299657181 Apr 15 12:19:43 PM PDT 24 Apr 15 12:19:45 PM PDT 24 53656301 ps
T885 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2783749458 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:11 PM PDT 24 174722573 ps
T886 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1638111422 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:12 PM PDT 24 86929448 ps
T887 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.600382159 Apr 15 12:19:43 PM PDT 24 Apr 15 12:19:45 PM PDT 24 147426759 ps
T888 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2491656180 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:13 PM PDT 24 198867749 ps
T889 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1294110982 Apr 15 12:18:48 PM PDT 24 Apr 15 12:18:50 PM PDT 24 37414684 ps
T890 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4284218935 Apr 15 12:17:41 PM PDT 24 Apr 15 12:17:42 PM PDT 24 78247244 ps
T891 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3525173245 Apr 15 12:19:01 PM PDT 24 Apr 15 12:19:03 PM PDT 24 29977776 ps
T892 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3763713665 Apr 15 12:19:08 PM PDT 24 Apr 15 12:19:10 PM PDT 24 444298600 ps
T893 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3495828021 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 215646961 ps
T894 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577430017 Apr 15 12:18:12 PM PDT 24 Apr 15 12:18:14 PM PDT 24 90846718 ps
T895 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1452925510 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:14 PM PDT 24 59820469 ps
T896 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779715340 Apr 15 12:19:12 PM PDT 24 Apr 15 12:19:14 PM PDT 24 158922188 ps
T897 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89371335 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 138389489 ps
T898 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3665503242 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:07 PM PDT 24 45497349 ps
T899 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3901180020 Apr 15 12:19:31 PM PDT 24 Apr 15 12:19:32 PM PDT 24 43511483 ps
T900 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3622772287 Apr 15 12:18:58 PM PDT 24 Apr 15 12:19:00 PM PDT 24 35385547 ps
T901 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.971451734 Apr 15 12:18:48 PM PDT 24 Apr 15 12:18:50 PM PDT 24 114382971 ps
T902 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3433090172 Apr 15 12:19:12 PM PDT 24 Apr 15 12:19:14 PM PDT 24 23638660 ps
T903 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1197086093 Apr 15 12:18:53 PM PDT 24 Apr 15 12:18:55 PM PDT 24 212401778 ps
T904 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.215252620 Apr 15 12:19:32 PM PDT 24 Apr 15 12:19:34 PM PDT 24 63150803 ps
T905 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3574710327 Apr 15 12:19:07 PM PDT 24 Apr 15 12:19:09 PM PDT 24 308289149 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3048953344 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:11 PM PDT 24 104145998 ps
T907 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.924776563 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 34003539 ps
T908 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.213491574 Apr 15 12:18:57 PM PDT 24 Apr 15 12:18:59 PM PDT 24 100812787 ps
T909 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.188077038 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:12 PM PDT 24 40660150 ps
T910 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.146092049 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:13 PM PDT 24 101214223 ps
T911 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833645593 Apr 15 12:19:15 PM PDT 24 Apr 15 12:19:16 PM PDT 24 68738406 ps
T912 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.505553983 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 62045190 ps
T913 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.393017082 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:14 PM PDT 24 127643597 ps
T914 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4185102883 Apr 15 12:19:07 PM PDT 24 Apr 15 12:19:09 PM PDT 24 77738301 ps
T915 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605370635 Apr 15 12:19:44 PM PDT 24 Apr 15 12:19:46 PM PDT 24 83623866 ps
T916 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1949873756 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 44851466 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680566294 Apr 15 12:18:59 PM PDT 24 Apr 15 12:19:00 PM PDT 24 56148984 ps
T918 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2364656921 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 439274546 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2548300728 Apr 15 12:19:10 PM PDT 24 Apr 15 12:19:12 PM PDT 24 664144680 ps
T920 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3728991575 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 44226396 ps
T921 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587843553 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:07 PM PDT 24 94893404 ps
T922 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2471587362 Apr 15 12:19:11 PM PDT 24 Apr 15 12:19:13 PM PDT 24 399568186 ps
T923 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037500581 Apr 15 12:19:30 PM PDT 24 Apr 15 12:19:32 PM PDT 24 51926376 ps
T924 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292177286 Apr 15 12:18:55 PM PDT 24 Apr 15 12:18:57 PM PDT 24 46752312 ps
T925 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616966828 Apr 15 12:17:03 PM PDT 24 Apr 15 12:17:04 PM PDT 24 43301277 ps
T926 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1953389420 Apr 15 12:19:08 PM PDT 24 Apr 15 12:19:10 PM PDT 24 22862218 ps
T927 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2903646207 Apr 15 12:19:05 PM PDT 24 Apr 15 12:19:07 PM PDT 24 53795951 ps
T928 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223932561 Apr 15 12:19:45 PM PDT 24 Apr 15 12:19:47 PM PDT 24 49451132 ps
T929 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1874852940 Apr 15 12:19:31 PM PDT 24 Apr 15 12:19:33 PM PDT 24 93074671 ps
T930 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2581083686 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 913389861 ps
T931 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.158207448 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 93762700 ps
T932 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1959735614 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:11 PM PDT 24 234866396 ps
T933 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2885370616 Apr 15 12:18:51 PM PDT 24 Apr 15 12:18:53 PM PDT 24 209502564 ps
T934 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1692637799 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 40485685 ps
T935 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3435210443 Apr 15 12:19:13 PM PDT 24 Apr 15 12:19:15 PM PDT 24 519534110 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983297759 Apr 15 12:19:04 PM PDT 24 Apr 15 12:19:06 PM PDT 24 188469181 ps
T937 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399305035 Apr 15 12:19:09 PM PDT 24 Apr 15 12:19:10 PM PDT 24 42422695 ps
T938 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1475265622 Apr 15 12:19:19 PM PDT 24 Apr 15 12:19:21 PM PDT 24 51022085 ps
T939 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044839338 Apr 15 12:18:49 PM PDT 24 Apr 15 12:18:50 PM PDT 24 22199785 ps
T940 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812209196 Apr 15 12:17:03 PM PDT 24 Apr 15 12:17:04 PM PDT 24 67457664 ps

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2177769903
Short name T30
Test name
Test status
Simulation time 62257428 ps
CPU time 2.56 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:33:09 PM PDT 24
Peak memory 198068 kb
Host smart-f7ece27a-01a6-438a-b27e-cfb046dfe7ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177769903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2177769903
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1205902957
Short name T114
Test name
Test status
Simulation time 576566349 ps
CPU time 2.69 seconds
Started Apr 15 12:32:35 PM PDT 24
Finished Apr 15 12:32:38 PM PDT 24
Peak memory 198108 kb
Host smart-817a9e7f-c73f-4fce-ba0e-fe1025f12325
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205902957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1205902957
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3812736743
Short name T17
Test name
Test status
Simulation time 84813536 ps
CPU time 0.57 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 194812 kb
Host smart-1cda5aea-faf4-454c-be2c-5a3d058e9e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812736743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3812736743
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2897829868
Short name T36
Test name
Test status
Simulation time 59910453168 ps
CPU time 1062.58 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:51:06 PM PDT 24
Peak memory 198180 kb
Host smart-f1081a9b-02b5-4173-9409-ae81d723df06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2897829868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2897829868
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3151873795
Short name T40
Test name
Test status
Simulation time 589812304 ps
CPU time 1.48 seconds
Started Apr 15 12:19:37 PM PDT 24
Finished Apr 15 12:19:39 PM PDT 24
Peak memory 198068 kb
Host smart-14cbded9-f947-4c35-b32d-56114722ba1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151873795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3151873795
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1479945153
Short name T1
Test name
Test status
Simulation time 18376148295 ps
CPU time 200.73 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:35:43 PM PDT 24
Peak memory 198076 kb
Host smart-f018206a-1b2a-4673-84b6-8463ad9a77fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479945153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1479945153
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3176092563
Short name T82
Test name
Test status
Simulation time 72172694 ps
CPU time 0.6 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 194272 kb
Host smart-71e2bcb5-9600-4ebe-ad03-13ceade1cd5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176092563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3176092563
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2946627127
Short name T54
Test name
Test status
Simulation time 402176936 ps
CPU time 1.12 seconds
Started Apr 15 12:32:10 PM PDT 24
Finished Apr 15 12:32:11 PM PDT 24
Peak memory 215052 kb
Host smart-750ccf7d-4b13-4c09-82a0-de4f7827ec94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946627127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2946627127
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2732569974
Short name T93
Test name
Test status
Simulation time 14076861 ps
CPU time 0.63 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 193840 kb
Host smart-78d2d8d5-9bc2-4dc2-938a-023ce8ac3f27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732569974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2732569974
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2106535655
Short name T49
Test name
Test status
Simulation time 163397145 ps
CPU time 0.85 seconds
Started Apr 15 12:19:43 PM PDT 24
Finished Apr 15 12:19:45 PM PDT 24
Peak memory 196940 kb
Host smart-9917fca2-8108-46ff-a2a0-788a542e3dfa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106535655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2106535655
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3312231480
Short name T100
Test name
Test status
Simulation time 22101583 ps
CPU time 0.87 seconds
Started Apr 15 12:20:08 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 195336 kb
Host smart-1343078a-3a0b-406e-beba-813b39c49eb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312231480 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3312231480
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1854298518
Short name T777
Test name
Test status
Simulation time 152177231 ps
CPU time 1.11 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 196696 kb
Host smart-7163e54e-7f73-490c-986d-0de9d8727c2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854298518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1854298518
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4169097922
Short name T25
Test name
Test status
Simulation time 71518917 ps
CPU time 1.26 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 197168 kb
Host smart-94e300d2-e8a6-40e7-8de6-7836dd9d6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169097922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4169097922
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3618580341
Short name T756
Test name
Test status
Simulation time 19971794 ps
CPU time 0.75 seconds
Started Apr 15 12:18:54 PM PDT 24
Finished Apr 15 12:18:55 PM PDT 24
Peak memory 194796 kb
Host smart-b5456b4a-0393-434e-ab1d-6c6c0173f172
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618580341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3618580341
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2414329266
Short name T85
Test name
Test status
Simulation time 222981651 ps
CPU time 2.14 seconds
Started Apr 15 12:20:19 PM PDT 24
Finished Apr 15 12:20:31 PM PDT 24
Peak memory 197708 kb
Host smart-5d8a67d6-2ffd-4ba5-b994-c2a21541c217
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414329266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2414329266
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1876254356
Short name T837
Test name
Test status
Simulation time 13984237 ps
CPU time 0.64 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 195392 kb
Host smart-5335111d-92fc-45a4-9f55-8c2f25a750fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876254356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1876254356
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1555568157
Short name T785
Test name
Test status
Simulation time 26743410 ps
CPU time 0.87 seconds
Started Apr 15 12:18:52 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 197892 kb
Host smart-c903acda-7b31-4f50-9bf6-f87a130e916a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555568157 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1555568157
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1152942973
Short name T793
Test name
Test status
Simulation time 14244193 ps
CPU time 0.64 seconds
Started Apr 15 12:18:52 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 194884 kb
Host smart-0309d5cc-40d3-40bd-a5a0-0156cde35157
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152942973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1152942973
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2082361769
Short name T783
Test name
Test status
Simulation time 16287625 ps
CPU time 0.58 seconds
Started Apr 15 12:20:18 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 193092 kb
Host smart-6c8e4245-6771-42e4-b575-9dded5914bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082361769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2082361769
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2688083879
Short name T767
Test name
Test status
Simulation time 42091363 ps
CPU time 1.94 seconds
Started Apr 15 12:20:19 PM PDT 24
Finished Apr 15 12:20:22 PM PDT 24
Peak memory 197804 kb
Host smart-2f7b9950-54ea-427d-a1ef-eb45afa4171f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688083879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2688083879
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2579230132
Short name T112
Test name
Test status
Simulation time 90438766 ps
CPU time 1.19 seconds
Started Apr 15 12:20:18 PM PDT 24
Finished Apr 15 12:20:20 PM PDT 24
Peak memory 197116 kb
Host smart-d3b07cbe-6340-4d97-8220-5ebcbc226100
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579230132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2579230132
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1241921779
Short name T800
Test name
Test status
Simulation time 18701811 ps
CPU time 0.71 seconds
Started Apr 15 12:19:19 PM PDT 24
Finished Apr 15 12:19:20 PM PDT 24
Peak memory 195364 kb
Host smart-59e3e94b-623b-4d28-94ba-c8b4e6aec2c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241921779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1241921779
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.718579531
Short name T811
Test name
Test status
Simulation time 34400047 ps
CPU time 1.34 seconds
Started Apr 15 12:19:22 PM PDT 24
Finished Apr 15 12:19:24 PM PDT 24
Peak memory 196636 kb
Host smart-e23e4f26-5441-4437-8a70-cea3df0bde2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718579531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.718579531
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3300339613
Short name T827
Test name
Test status
Simulation time 18736204 ps
CPU time 0.62 seconds
Started Apr 15 12:19:19 PM PDT 24
Finished Apr 15 12:19:21 PM PDT 24
Peak memory 194404 kb
Host smart-6c9ff4e5-1432-4358-bf41-6a5ede626a8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300339613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3300339613
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4007317631
Short name T731
Test name
Test status
Simulation time 34626753 ps
CPU time 1.5 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 198112 kb
Host smart-84198084-1cc2-4865-bb29-a1ad8f4eab4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007317631 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4007317631
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2795260065
Short name T788
Test name
Test status
Simulation time 37690797 ps
CPU time 0.63 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 195016 kb
Host smart-a801a0ff-12c3-4c9f-9711-b5e9334bbb65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795260065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2795260065
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3061363281
Short name T732
Test name
Test status
Simulation time 65848382 ps
CPU time 0.64 seconds
Started Apr 15 12:19:18 PM PDT 24
Finished Apr 15 12:19:19 PM PDT 24
Peak memory 194404 kb
Host smart-3d1edf1f-a77d-49eb-affa-d4e19a0c4782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061363281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3061363281
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2513272309
Short name T830
Test name
Test status
Simulation time 32051571 ps
CPU time 0.68 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 194844 kb
Host smart-78aff2d9-daa6-439b-83fb-4fc4e1573f83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513272309 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2513272309
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.497775903
Short name T740
Test name
Test status
Simulation time 59969449 ps
CPU time 1.62 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 198052 kb
Host smart-aabd7a30-725c-4bc2-8357-5e153e04fc99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497775903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.497775903
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2041790862
Short name T823
Test name
Test status
Simulation time 71114972 ps
CPU time 1.21 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 198068 kb
Host smart-7c25123a-6a90-4118-8c0c-5452200eece4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041790862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2041790862
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2658085965
Short name T794
Test name
Test status
Simulation time 16939631 ps
CPU time 0.86 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 197884 kb
Host smart-b1b7f907-16b2-442a-b51b-c7339f2466a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658085965 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2658085965
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1994652642
Short name T754
Test name
Test status
Simulation time 70483362 ps
CPU time 0.69 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 192112 kb
Host smart-aa4947e5-a9ae-4723-ae6d-99787429b162
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994652642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1994652642
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.533950061
Short name T803
Test name
Test status
Simulation time 11208736 ps
CPU time 0.59 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193708 kb
Host smart-681e7dd1-2dc6-459f-9409-b9f475c77677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533950061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.533950061
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3860708804
Short name T101
Test name
Test status
Simulation time 28754071 ps
CPU time 0.72 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 194872 kb
Host smart-c6589042-d1da-4e12-94e1-4e411c5593c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860708804 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3860708804
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3532044536
Short name T725
Test name
Test status
Simulation time 169997788 ps
CPU time 1.59 seconds
Started Apr 15 12:19:41 PM PDT 24
Finished Apr 15 12:19:43 PM PDT 24
Peak memory 197904 kb
Host smart-891d9c09-864f-4bfb-93f4-d6bf186b3adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532044536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3532044536
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2916527170
Short name T796
Test name
Test status
Simulation time 91800505 ps
CPU time 1.16 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 197816 kb
Host smart-6ecfd37e-986f-4a93-82c1-399e1a29e4d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916527170 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2916527170
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.936505999
Short name T808
Test name
Test status
Simulation time 26441578 ps
CPU time 0.6 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193688 kb
Host smart-6b862221-206c-499c-a1c4-98b4ac09406a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936505999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.936505999
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1810823079
Short name T102
Test name
Test status
Simulation time 36850914 ps
CPU time 0.61 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 194588 kb
Host smart-ff7585f9-03a3-4eab-9b32-94e93f274550
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810823079 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1810823079
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.966289872
Short name T757
Test name
Test status
Simulation time 99864677 ps
CPU time 2.05 seconds
Started Apr 15 12:19:37 PM PDT 24
Finished Apr 15 12:19:39 PM PDT 24
Peak memory 198068 kb
Host smart-29db94ab-a9c3-47a9-b8e6-a51bcfb8cab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966289872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.966289872
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1933167699
Short name T39
Test name
Test status
Simulation time 60301439 ps
CPU time 0.84 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 197672 kb
Host smart-20750581-18d9-46c5-ba8a-72d7125653db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933167699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1933167699
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.453624942
Short name T733
Test name
Test status
Simulation time 63615397 ps
CPU time 0.86 seconds
Started Apr 15 12:19:48 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 197868 kb
Host smart-92d15a36-cc9a-4fa7-a29b-a38340fd4b2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453624942 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.453624942
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3264222488
Short name T91
Test name
Test status
Simulation time 45553901 ps
CPU time 0.7 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 192596 kb
Host smart-0b657177-4c46-4484-80fd-e6190ca849af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264222488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3264222488
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1831410262
Short name T780
Test name
Test status
Simulation time 19408695 ps
CPU time 0.59 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193704 kb
Host smart-8edb3477-9a0c-42e8-bb3e-23b3fc67fea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831410262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1831410262
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2165188937
Short name T98
Test name
Test status
Simulation time 51105647 ps
CPU time 0.62 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 194800 kb
Host smart-31a2203b-c614-46df-bd29-502ef5bc6095
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165188937 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2165188937
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3877941260
Short name T718
Test name
Test status
Simulation time 41585331 ps
CPU time 1.14 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 197876 kb
Host smart-78733125-5fde-4dc6-bfc1-f9ea1f45ffd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877941260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3877941260
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3501725966
Short name T46
Test name
Test status
Simulation time 258365028 ps
CPU time 1.41 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 198008 kb
Host smart-f3a78a65-dfa7-42af-b7e7-a0d8597df5a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501725966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3501725966
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1505239536
Short name T722
Test name
Test status
Simulation time 28022191 ps
CPU time 1.3 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 195608 kb
Host smart-d1c39f56-1af7-4d8d-875b-ccd374435fbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505239536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1505239536
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.548082107
Short name T822
Test name
Test status
Simulation time 29991867 ps
CPU time 0.62 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 192376 kb
Host smart-8d6532ba-c362-4978-a2df-60a358b36e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548082107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.548082107
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.42372550
Short name T826
Test name
Test status
Simulation time 109212430 ps
CPU time 0.75 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 195460 kb
Host smart-5963edff-257c-4421-aaf0-73ff5a6030fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372550 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.gpio_same_csr_outstanding.42372550
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.564548714
Short name T720
Test name
Test status
Simulation time 215989891 ps
CPU time 1.83 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 195760 kb
Host smart-d720e627-7291-464d-bc24-e0802de9978d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564548714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.564548714
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2870707049
Short name T792
Test name
Test status
Simulation time 167945939 ps
CPU time 0.89 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 197480 kb
Host smart-37fc1b87-3e46-4f8d-8598-fb57b5e3a920
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870707049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2870707049
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3407910520
Short name T840
Test name
Test status
Simulation time 17970574 ps
CPU time 0.75 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 194628 kb
Host smart-83a38802-6edd-482a-88d9-0d48f1b702fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407910520 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3407910520
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.37602351
Short name T80
Test name
Test status
Simulation time 13605027 ps
CPU time 0.58 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:52 PM PDT 24
Peak memory 195320 kb
Host smart-7a26dd1d-eb2a-4768-bd63-3dcf5e33405b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37602351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.37602351
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2312114211
Short name T738
Test name
Test status
Simulation time 39787088 ps
CPU time 0.54 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:43 PM PDT 24
Peak memory 193132 kb
Host smart-d97f0ca7-ac8a-4806-9236-fa78f80ec95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312114211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2312114211
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2434190442
Short name T88
Test name
Test status
Simulation time 93207796 ps
CPU time 0.75 seconds
Started Apr 15 12:19:46 PM PDT 24
Finished Apr 15 12:19:48 PM PDT 24
Peak memory 196004 kb
Host smart-885eb23b-2a41-4351-8958-0f381464d555
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434190442 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2434190442
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4130999988
Short name T717
Test name
Test status
Simulation time 69558521 ps
CPU time 1.45 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 197812 kb
Host smart-d2fd0637-d039-4cd2-83aa-756418e65965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130999988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4130999988
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1950168435
Short name T835
Test name
Test status
Simulation time 450141842 ps
CPU time 1.11 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 197656 kb
Host smart-8b8009e8-c0fb-4352-9623-2146794b6726
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950168435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1950168435
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2657955225
Short name T829
Test name
Test status
Simulation time 93864995 ps
CPU time 0.72 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 197616 kb
Host smart-fd944057-581c-4994-b06f-fb141f8cfb59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657955225 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2657955225
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1237075015
Short name T791
Test name
Test status
Simulation time 35485760 ps
CPU time 0.64 seconds
Started Apr 15 12:19:41 PM PDT 24
Finished Apr 15 12:19:43 PM PDT 24
Peak memory 194220 kb
Host smart-750a3fa8-b62f-4dab-a4e1-999886503d3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237075015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1237075015
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3173256869
Short name T816
Test name
Test status
Simulation time 12507285 ps
CPU time 0.59 seconds
Started Apr 15 12:19:46 PM PDT 24
Finished Apr 15 12:19:47 PM PDT 24
Peak memory 193664 kb
Host smart-bc3cb8d3-8876-4f54-ab5a-a7aae83f1149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173256869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3173256869
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2508982328
Short name T784
Test name
Test status
Simulation time 94259053 ps
CPU time 0.71 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 196184 kb
Host smart-260aa305-61d2-4103-a4eb-0c6911551808
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508982328 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2508982328
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2982326486
Short name T716
Test name
Test status
Simulation time 547556737 ps
CPU time 1.95 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 197620 kb
Host smart-aa1ceb75-4bc8-423b-b409-3d90d80854ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982326486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2982326486
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2958251102
Short name T719
Test name
Test status
Simulation time 52684144 ps
CPU time 0.75 seconds
Started Apr 15 12:19:46 PM PDT 24
Finished Apr 15 12:19:47 PM PDT 24
Peak memory 197768 kb
Host smart-cc742fcf-93a1-448d-b89e-7ed22e970df5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958251102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2958251102
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3615554549
Short name T747
Test name
Test status
Simulation time 25862911 ps
CPU time 0.58 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 193264 kb
Host smart-a202694a-934d-43fa-b4a9-3866fc1604d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615554549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3615554549
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3108149653
Short name T789
Test name
Test status
Simulation time 10251916 ps
CPU time 0.61 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 193428 kb
Host smart-d2b26ff4-c626-422e-813a-a67b86285c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108149653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3108149653
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2959900804
Short name T89
Test name
Test status
Simulation time 27023821 ps
CPU time 0.87 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 193416 kb
Host smart-3ccf4826-ab29-4af0-805c-8cba7cc0caf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959900804 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2959900804
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3535790724
Short name T805
Test name
Test status
Simulation time 336269016 ps
CPU time 1.78 seconds
Started Apr 15 12:19:55 PM PDT 24
Finished Apr 15 12:19:59 PM PDT 24
Peak memory 197980 kb
Host smart-810422de-b726-46fa-ab30-04b7b4ea7d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535790724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3535790724
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3159573524
Short name T815
Test name
Test status
Simulation time 178783259 ps
CPU time 1.44 seconds
Started Apr 15 12:19:41 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 196908 kb
Host smart-4585de99-5885-43dc-8a55-1679b8c96fa0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159573524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3159573524
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1663553211
Short name T825
Test name
Test status
Simulation time 43370067 ps
CPU time 1.08 seconds
Started Apr 15 12:19:56 PM PDT 24
Finished Apr 15 12:19:59 PM PDT 24
Peak memory 198080 kb
Host smart-6e21cef4-d9d4-4ff6-9fb2-d9ec458999ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663553211 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1663553211
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1338049818
Short name T111
Test name
Test status
Simulation time 13755567 ps
CPU time 0.56 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 194984 kb
Host smart-9e159090-1c7e-4514-ae9a-ce2bceb40b63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338049818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1338049818
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1045281940
Short name T809
Test name
Test status
Simulation time 29405290 ps
CPU time 0.57 seconds
Started Apr 15 12:19:52 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 193232 kb
Host smart-416aa7d4-6b04-4d2c-9c00-0e0aead99e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045281940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1045281940
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.807883954
Short name T778
Test name
Test status
Simulation time 52416316 ps
CPU time 0.75 seconds
Started Apr 15 12:20:04 PM PDT 24
Finished Apr 15 12:20:06 PM PDT 24
Peak memory 195608 kb
Host smart-834d3c1d-0a13-45eb-9a64-84f68a97bc0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807883954 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.807883954
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.577838297
Short name T773
Test name
Test status
Simulation time 104325789 ps
CPU time 1.96 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:56 PM PDT 24
Peak memory 198032 kb
Host smart-f8b550d3-8973-4d11-85b6-73caa6b733e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577838297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.577838297
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1976041304
Short name T41
Test name
Test status
Simulation time 181376394 ps
CPU time 1.4 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 198056 kb
Host smart-d80d4176-0dd7-4999-afaa-24836ff2e82c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976041304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1976041304
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3746863010
Short name T752
Test name
Test status
Simulation time 181000159 ps
CPU time 0.99 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 197932 kb
Host smart-4e2bea36-1375-4128-bfec-09897e8436bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746863010 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3746863010
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1364895794
Short name T744
Test name
Test status
Simulation time 11720948 ps
CPU time 0.57 seconds
Started Apr 15 12:19:53 PM PDT 24
Finished Apr 15 12:20:00 PM PDT 24
Peak memory 195140 kb
Host smart-87269d4b-64e3-4914-80f9-789390988f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364895794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1364895794
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2746669824
Short name T742
Test name
Test status
Simulation time 11159632 ps
CPU time 0.57 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 192904 kb
Host smart-f0837470-9190-4b94-a5b9-a4959c277a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746669824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2746669824
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3940330663
Short name T795
Test name
Test status
Simulation time 193123108 ps
CPU time 0.65 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 194680 kb
Host smart-1c8dd20f-726a-4579-bd18-4fbe1d64e260
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940330663 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3940330663
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.946159469
Short name T832
Test name
Test status
Simulation time 146742743 ps
CPU time 1.95 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:56 PM PDT 24
Peak memory 197840 kb
Host smart-81599792-5b15-45c3-a4c2-0bdd979e66f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946159469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.946159469
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.644181152
Short name T806
Test name
Test status
Simulation time 1224159874 ps
CPU time 1.11 seconds
Started Apr 15 12:19:58 PM PDT 24
Finished Apr 15 12:20:00 PM PDT 24
Peak memory 197984 kb
Host smart-53964443-95a6-4ff9-a1c2-93da64b0f82b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644181152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.644181152
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.463286258
Short name T735
Test name
Test status
Simulation time 32078316 ps
CPU time 0.77 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 197088 kb
Host smart-3db990f2-4d26-471c-8b6b-101ae03281c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463286258 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.463286258
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4208128509
Short name T90
Test name
Test status
Simulation time 34592321 ps
CPU time 0.57 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 193684 kb
Host smart-c40787ff-1d18-4439-8833-11dddf87eaa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208128509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4208128509
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1834413430
Short name T723
Test name
Test status
Simulation time 15914953 ps
CPU time 0.57 seconds
Started Apr 15 12:19:52 PM PDT 24
Finished Apr 15 12:19:56 PM PDT 24
Peak memory 193724 kb
Host smart-d1c3deed-9237-4713-bd2e-4f5ac0650bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834413430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1834413430
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3861936239
Short name T81
Test name
Test status
Simulation time 37018493 ps
CPU time 0.65 seconds
Started Apr 15 12:20:06 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 194624 kb
Host smart-8cb47de9-efa4-4722-8a87-7fceca1319e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861936239 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3861936239
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.877256478
Short name T801
Test name
Test status
Simulation time 101130066 ps
CPU time 1.09 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 197832 kb
Host smart-d856efcb-9d61-44db-b168-e21ffffc5dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877256478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.877256478
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3499101712
Short name T804
Test name
Test status
Simulation time 326919042 ps
CPU time 0.93 seconds
Started Apr 15 12:19:52 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 195720 kb
Host smart-12942576-b69c-44b7-b606-8afa2e48d4ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499101712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3499101712
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2731449534
Short name T84
Test name
Test status
Simulation time 35088255 ps
CPU time 0.65 seconds
Started Apr 15 12:19:22 PM PDT 24
Finished Apr 15 12:19:23 PM PDT 24
Peak memory 194192 kb
Host smart-0f851feb-3165-41fe-a447-15c69c4e55c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731449534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2731449534
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1407017935
Short name T97
Test name
Test status
Simulation time 1042176546 ps
CPU time 2.51 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:35 PM PDT 24
Peak memory 196884 kb
Host smart-ab037f09-6135-4e22-b1a2-b1fd08ccfc22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407017935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1407017935
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1709502040
Short name T824
Test name
Test status
Simulation time 86929780 ps
CPU time 0.66 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 194680 kb
Host smart-a9f42943-8d8d-4300-bb9d-e9a5276566ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709502040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1709502040
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1421139884
Short name T781
Test name
Test status
Simulation time 50255709 ps
CPU time 0.68 seconds
Started Apr 15 12:19:22 PM PDT 24
Finished Apr 15 12:19:23 PM PDT 24
Peak memory 196436 kb
Host smart-bace4d22-f643-4a9f-96be-579083586209
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421139884 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1421139884
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2839112037
Short name T741
Test name
Test status
Simulation time 158788247 ps
CPU time 0.61 seconds
Started Apr 15 12:19:27 PM PDT 24
Finished Apr 15 12:19:28 PM PDT 24
Peak memory 194684 kb
Host smart-7b5f6bb6-e8d5-4a43-a32c-9a8fd6cdd31d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839112037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2839112037
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3346781814
Short name T759
Test name
Test status
Simulation time 12563219 ps
CPU time 0.62 seconds
Started Apr 15 12:20:36 PM PDT 24
Finished Apr 15 12:20:37 PM PDT 24
Peak memory 192828 kb
Host smart-77cf458a-ccce-494e-9cc8-7878eb5c0f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346781814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3346781814
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2810257537
Short name T770
Test name
Test status
Simulation time 224936418 ps
CPU time 0.87 seconds
Started Apr 15 12:19:22 PM PDT 24
Finished Apr 15 12:19:23 PM PDT 24
Peak memory 196160 kb
Host smart-4371f044-d9a2-444c-8b6a-9f116fdb7bce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810257537 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2810257537
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1246565743
Short name T820
Test name
Test status
Simulation time 72791569 ps
CPU time 1.55 seconds
Started Apr 15 12:19:25 PM PDT 24
Finished Apr 15 12:19:27 PM PDT 24
Peak memory 198088 kb
Host smart-2f5b8bd4-0d92-44f8-9ad7-59e9d0ce0df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246565743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1246565743
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3700954922
Short name T47
Test name
Test status
Simulation time 352675364 ps
CPU time 1.22 seconds
Started Apr 15 12:19:30 PM PDT 24
Finished Apr 15 12:19:31 PM PDT 24
Peak memory 197996 kb
Host smart-09fd78dd-0cf4-497b-ac54-e7d02dcf63e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700954922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3700954922
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1916957826
Short name T818
Test name
Test status
Simulation time 15517063 ps
CPU time 0.56 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 194296 kb
Host smart-25d46b87-3b0c-40e5-a590-83a9ebd9d6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916957826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1916957826
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.213994456
Short name T749
Test name
Test status
Simulation time 16690695 ps
CPU time 0.61 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 193764 kb
Host smart-28b17b2f-1572-4cbd-b5f6-62b419d61aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213994456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.213994456
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3805763658
Short name T751
Test name
Test status
Simulation time 16290635 ps
CPU time 0.73 seconds
Started Apr 15 12:19:52 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 192192 kb
Host smart-fd47e88c-d732-4121-b6ae-f2a826f679cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805763658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3805763658
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.634683847
Short name T798
Test name
Test status
Simulation time 14688194 ps
CPU time 0.63 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 192060 kb
Host smart-5b79e14b-8d2a-4d6a-9979-dd00d6948bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634683847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.634683847
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1538669640
Short name T833
Test name
Test status
Simulation time 96060679 ps
CPU time 0.59 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 193772 kb
Host smart-4d598add-d008-4ed1-91b5-0d7dc4459194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538669640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1538669640
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2340061353
Short name T774
Test name
Test status
Simulation time 13118731 ps
CPU time 0.6 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193684 kb
Host smart-d04fd88e-74ce-4006-849a-f6a376819afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340061353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2340061353
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1263056
Short name T739
Test name
Test status
Simulation time 20233973 ps
CPU time 0.6 seconds
Started Apr 15 12:20:09 PM PDT 24
Finished Apr 15 12:20:11 PM PDT 24
Peak memory 193660 kb
Host smart-a0aa2ac0-657f-4b14-ad41-4c47424a56f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1263056
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3722073677
Short name T753
Test name
Test status
Simulation time 14928801 ps
CPU time 0.63 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193692 kb
Host smart-771c8248-424d-418c-aea7-b70bb76ce737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722073677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3722073677
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2958203776
Short name T714
Test name
Test status
Simulation time 207761716 ps
CPU time 0.7 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:52 PM PDT 24
Peak memory 192748 kb
Host smart-6aa6da03-0601-4f19-bf38-f1094a080530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958203776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2958203776
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2428659182
Short name T828
Test name
Test status
Simulation time 55007078 ps
CPU time 0.61 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 192164 kb
Host smart-b08b3f1f-5718-4e17-9717-451b635d9ae6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428659182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2428659182
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1399311640
Short name T96
Test name
Test status
Simulation time 17674681 ps
CPU time 0.86 seconds
Started Apr 15 12:19:37 PM PDT 24
Finished Apr 15 12:19:38 PM PDT 24
Peak memory 195680 kb
Host smart-83539dce-568f-43fb-81b6-3ebf00553081
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399311640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1399311640
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.304490875
Short name T807
Test name
Test status
Simulation time 37252033 ps
CPU time 1.39 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:58 PM PDT 24
Peak memory 196852 kb
Host smart-7d29da28-15fa-454f-8804-2e1d2617628f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304490875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.304490875
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2216525349
Short name T95
Test name
Test status
Simulation time 35820369 ps
CPU time 0.59 seconds
Started Apr 15 12:19:48 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 194676 kb
Host smart-6f52ef46-3cec-4d77-ac76-80a555985e42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216525349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2216525349
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2963845991
Short name T790
Test name
Test status
Simulation time 18896759 ps
CPU time 0.72 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 197508 kb
Host smart-a6e79f97-0b10-4b66-8d6a-50a35e2e9b7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963845991 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2963845991
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.4051524977
Short name T775
Test name
Test status
Simulation time 18821569 ps
CPU time 0.61 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 194872 kb
Host smart-1c5a3b11-b663-4464-ba41-ecef848562b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051524977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.4051524977
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2393462670
Short name T750
Test name
Test status
Simulation time 51039846 ps
CPU time 0.6 seconds
Started Apr 15 12:19:29 PM PDT 24
Finished Apr 15 12:19:30 PM PDT 24
Peak memory 194324 kb
Host smart-4deb3d11-d48e-4ad3-9c4e-0ac3ae051395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393462670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2393462670
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2463822324
Short name T786
Test name
Test status
Simulation time 26810002 ps
CPU time 0.72 seconds
Started Apr 15 12:19:30 PM PDT 24
Finished Apr 15 12:19:31 PM PDT 24
Peak memory 195016 kb
Host smart-6bcb6b15-7d69-423e-861d-8cb553b4630c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463822324 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2463822324
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.112112611
Short name T728
Test name
Test status
Simulation time 94271617 ps
CPU time 2.03 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:35 PM PDT 24
Peak memory 198132 kb
Host smart-be3e3bc6-6aa2-4fae-a38f-45ac8ca87562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112112611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.112112611
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3990466366
Short name T48
Test name
Test status
Simulation time 70564997 ps
CPU time 1.14 seconds
Started Apr 15 12:19:29 PM PDT 24
Finished Apr 15 12:19:31 PM PDT 24
Peak memory 197996 kb
Host smart-d840645c-0faa-4c4f-94b3-9cb47a8dc305
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990466366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3990466366
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3996319314
Short name T762
Test name
Test status
Simulation time 16673380 ps
CPU time 0.55 seconds
Started Apr 15 12:20:04 PM PDT 24
Finished Apr 15 12:20:05 PM PDT 24
Peak memory 193680 kb
Host smart-f6753812-9195-41d8-8195-f87a5cffa606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996319314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3996319314
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1710094857
Short name T760
Test name
Test status
Simulation time 11111457 ps
CPU time 0.56 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 193656 kb
Host smart-c616d040-0aab-4dd0-be7c-7e9b680c0973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710094857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1710094857
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3067295665
Short name T763
Test name
Test status
Simulation time 31225543 ps
CPU time 0.64 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 193544 kb
Host smart-f3a21c63-5838-4963-a95a-d9ce301d595f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067295665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3067295665
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3308522358
Short name T810
Test name
Test status
Simulation time 181841313 ps
CPU time 0.58 seconds
Started Apr 15 12:20:07 PM PDT 24
Finished Apr 15 12:20:09 PM PDT 24
Peak memory 193812 kb
Host smart-5007053a-b485-40c6-a57a-9ef21264436a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308522358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3308522358
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1771307681
Short name T745
Test name
Test status
Simulation time 41376063 ps
CPU time 0.6 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 193760 kb
Host smart-1bc45811-2f40-4199-a3b6-fb99a8ab1582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771307681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1771307681
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2417212157
Short name T813
Test name
Test status
Simulation time 18478238 ps
CPU time 0.6 seconds
Started Apr 15 12:20:05 PM PDT 24
Finished Apr 15 12:20:07 PM PDT 24
Peak memory 193772 kb
Host smart-4aeea5eb-06e6-47c2-8823-1d399a0b4864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417212157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2417212157
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2543675173
Short name T730
Test name
Test status
Simulation time 18254962 ps
CPU time 0.59 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:49 PM PDT 24
Peak memory 193628 kb
Host smart-348b5212-aa19-4226-9783-40b2dafeea08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543675173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2543675173
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3916384288
Short name T724
Test name
Test status
Simulation time 49269810 ps
CPU time 0.59 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 193744 kb
Host smart-2a982a8f-f627-4cc5-bcb5-d7d4a23653e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916384288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3916384288
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.120953427
Short name T746
Test name
Test status
Simulation time 11226380 ps
CPU time 0.57 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 193680 kb
Host smart-cf8bd504-adb1-4ec1-952c-70801bb33b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120953427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.120953427
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.997888500
Short name T771
Test name
Test status
Simulation time 14463543 ps
CPU time 0.58 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 194384 kb
Host smart-4a4a71d6-99af-42d0-b912-e07f738f5a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997888500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.997888500
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.903185664
Short name T83
Test name
Test status
Simulation time 15409126 ps
CPU time 0.62 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 194568 kb
Host smart-40e00050-a68b-4784-a3bd-a9da4c0bd0a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903185664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.903185664
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3266948843
Short name T110
Test name
Test status
Simulation time 134644008 ps
CPU time 1.32 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:58 PM PDT 24
Peak memory 197912 kb
Host smart-c69563bc-e1e6-475d-88c8-edf14b8842c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266948843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3266948843
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.661008147
Short name T819
Test name
Test status
Simulation time 18886927 ps
CPU time 0.65 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 194532 kb
Host smart-e0291e60-1762-41c9-869d-6f1e9b3c5760
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661008147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.661008147
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1569659688
Short name T821
Test name
Test status
Simulation time 35288522 ps
CPU time 0.89 seconds
Started Apr 15 12:19:46 PM PDT 24
Finished Apr 15 12:19:48 PM PDT 24
Peak memory 197892 kb
Host smart-e1253292-6742-4559-9e3c-a521c86ef3e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569659688 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1569659688
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.365187874
Short name T814
Test name
Test status
Simulation time 14365729 ps
CPU time 0.6 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 195104 kb
Host smart-08d10430-028e-4fd0-82b9-47483baf1963
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365187874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.365187874
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4053514637
Short name T782
Test name
Test status
Simulation time 30173494 ps
CPU time 0.57 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:43 PM PDT 24
Peak memory 194272 kb
Host smart-5cf815b8-933a-4ff3-b242-2030f8ae45c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053514637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4053514637
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3128324132
Short name T99
Test name
Test status
Simulation time 61341999 ps
CPU time 0.64 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 195020 kb
Host smart-4b7278c8-fa88-4f42-9f53-fe00d3e757d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128324132 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3128324132
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1361796515
Short name T764
Test name
Test status
Simulation time 486488823 ps
CPU time 2.77 seconds
Started Apr 15 12:20:58 PM PDT 24
Finished Apr 15 12:21:01 PM PDT 24
Peak memory 197956 kb
Host smart-1d3ffc64-02f8-4977-8fb9-28108b2cf465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361796515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1361796515
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2341412259
Short name T51
Test name
Test status
Simulation time 184963553 ps
CPU time 0.85 seconds
Started Apr 15 12:19:31 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 197576 kb
Host smart-d15e5f56-ab2d-4102-be68-73e23c64d469
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341412259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2341412259
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.224307327
Short name T834
Test name
Test status
Simulation time 12349428 ps
CPU time 0.56 seconds
Started Apr 15 12:19:55 PM PDT 24
Finished Apr 15 12:19:58 PM PDT 24
Peak memory 193668 kb
Host smart-7c72f07e-1f8a-4ff1-9097-04a153869824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224307327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.224307327
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3553180468
Short name T836
Test name
Test status
Simulation time 33697275 ps
CPU time 0.6 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 194284 kb
Host smart-94a73659-b4e3-4292-9309-34f8c698671c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553180468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3553180468
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3334969968
Short name T755
Test name
Test status
Simulation time 15885065 ps
CPU time 0.56 seconds
Started Apr 15 12:20:20 PM PDT 24
Finished Apr 15 12:20:26 PM PDT 24
Peak memory 193752 kb
Host smart-e74e1605-7a94-44b6-b810-6429876cc488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334969968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3334969968
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1033629640
Short name T748
Test name
Test status
Simulation time 22761690 ps
CPU time 0.58 seconds
Started Apr 15 12:19:56 PM PDT 24
Finished Apr 15 12:19:58 PM PDT 24
Peak memory 193764 kb
Host smart-2c52b4f0-c92c-4b73-8ebc-21d30369a984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033629640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1033629640
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3892674310
Short name T769
Test name
Test status
Simulation time 13956272 ps
CPU time 0.6 seconds
Started Apr 15 12:19:41 PM PDT 24
Finished Apr 15 12:19:42 PM PDT 24
Peak memory 194692 kb
Host smart-4e2969e1-86b4-4314-8aae-9849910b1b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892674310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3892674310
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1232283407
Short name T761
Test name
Test status
Simulation time 16970730 ps
CPU time 0.69 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:52 PM PDT 24
Peak memory 192664 kb
Host smart-cd6cf992-d735-4018-b7db-940c8e7236bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232283407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1232283407
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1664380552
Short name T766
Test name
Test status
Simulation time 14452625 ps
CPU time 0.57 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 193608 kb
Host smart-9467cb58-57be-4f1f-800b-f67c5d37985f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664380552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1664380552
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1428627973
Short name T734
Test name
Test status
Simulation time 26347723 ps
CPU time 0.58 seconds
Started Apr 15 12:19:59 PM PDT 24
Finished Apr 15 12:20:00 PM PDT 24
Peak memory 193712 kb
Host smart-cfb8b0c9-d306-4b91-846a-849e616c978f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428627973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1428627973
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3775135208
Short name T768
Test name
Test status
Simulation time 32157453 ps
CPU time 0.64 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 191280 kb
Host smart-d208e115-0005-404a-b414-2f3ee9a46b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775135208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3775135208
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.857656728
Short name T737
Test name
Test status
Simulation time 55638096 ps
CPU time 0.58 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 193580 kb
Host smart-690451f5-d2ac-4c94-8e7e-364a5076a1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857656728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.857656728
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2393054026
Short name T831
Test name
Test status
Simulation time 137679678 ps
CPU time 0.93 seconds
Started Apr 15 12:19:37 PM PDT 24
Finished Apr 15 12:19:38 PM PDT 24
Peak memory 197856 kb
Host smart-aa9b6506-bc0a-4571-b13d-6c6ea68d701c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393054026 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2393054026
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1665741660
Short name T802
Test name
Test status
Simulation time 33149848 ps
CPU time 0.57 seconds
Started Apr 15 12:19:37 PM PDT 24
Finished Apr 15 12:19:38 PM PDT 24
Peak memory 193176 kb
Host smart-e908039c-26e5-4573-8f13-6d8655894270
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665741660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1665741660
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1266469910
Short name T817
Test name
Test status
Simulation time 37876900 ps
CPU time 0.57 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 193608 kb
Host smart-da499f9c-cbe4-403e-af6b-57ca596874ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266469910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1266469910
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4230400311
Short name T797
Test name
Test status
Simulation time 63306240 ps
CPU time 0.66 seconds
Started Apr 15 12:20:56 PM PDT 24
Finished Apr 15 12:20:57 PM PDT 24
Peak memory 195460 kb
Host smart-9814affb-1a47-454c-aadd-6bb7daa17a36
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230400311 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4230400311
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1836648240
Short name T727
Test name
Test status
Simulation time 218617605 ps
CPU time 1.99 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 197676 kb
Host smart-dd504406-1665-46c8-a1f9-e35d3904418c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836648240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1836648240
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.185668259
Short name T50
Test name
Test status
Simulation time 413601558 ps
CPU time 1.38 seconds
Started Apr 15 12:19:40 PM PDT 24
Finished Apr 15 12:19:42 PM PDT 24
Peak memory 197956 kb
Host smart-ab48324d-4d71-45f7-9067-f9d907272a6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185668259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.185668259
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.870906233
Short name T772
Test name
Test status
Simulation time 23251590 ps
CPU time 0.99 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 195500 kb
Host smart-be1d814e-095c-4f0a-8c08-d9c0724d3853
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870906233 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.870906233
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3062827916
Short name T812
Test name
Test status
Simulation time 16081581 ps
CPU time 0.6 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 194828 kb
Host smart-2a12f56d-d91c-40b2-b73a-e9919aad5764
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062827916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3062827916
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.258661049
Short name T729
Test name
Test status
Simulation time 13987884 ps
CPU time 0.59 seconds
Started Apr 15 12:19:54 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 193748 kb
Host smart-abd09ef0-ea97-4366-a3aa-2bb7f1cc78cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258661049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.258661049
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2957546916
Short name T838
Test name
Test status
Simulation time 15737244 ps
CPU time 0.65 seconds
Started Apr 15 12:19:48 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 194136 kb
Host smart-71644df0-1f0c-4baa-b2fb-a7f575f4c83b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957546916 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2957546916
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3215573903
Short name T736
Test name
Test status
Simulation time 21962486 ps
CPU time 1.21 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 197924 kb
Host smart-556e81e1-2c9a-4b41-86db-1ed5819d02e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215573903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3215573903
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.434664809
Short name T45
Test name
Test status
Simulation time 43572608 ps
CPU time 0.85 seconds
Started Apr 15 12:19:46 PM PDT 24
Finished Apr 15 12:19:48 PM PDT 24
Peak memory 197084 kb
Host smart-e24b48d7-81ff-4fe0-9d36-32ad2873140d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434664809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.434664809
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2114328797
Short name T839
Test name
Test status
Simulation time 470873923 ps
CPU time 1.49 seconds
Started Apr 15 12:19:48 PM PDT 24
Finished Apr 15 12:19:52 PM PDT 24
Peak memory 198088 kb
Host smart-48ec43e0-8639-46b0-a901-9f76ba84b5bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114328797 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2114328797
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1653401011
Short name T92
Test name
Test status
Simulation time 13581047 ps
CPU time 0.58 seconds
Started Apr 15 12:19:53 PM PDT 24
Finished Apr 15 12:19:56 PM PDT 24
Peak memory 194648 kb
Host smart-e3b6fa0e-36ef-438f-8678-1a4a13121f7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653401011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1653401011
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.718989761
Short name T726
Test name
Test status
Simulation time 17313965 ps
CPU time 0.64 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 191104 kb
Host smart-d0a5fb38-a46c-451b-a859-56001a6d031f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718989761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.718989761
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.661963325
Short name T86
Test name
Test status
Simulation time 16893109 ps
CPU time 0.77 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 196640 kb
Host smart-e17e173f-e203-4ea9-ba0f-a66902e3e9cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661963325 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.661963325
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3068192224
Short name T779
Test name
Test status
Simulation time 248870892 ps
CPU time 2.15 seconds
Started Apr 15 12:19:53 PM PDT 24
Finished Apr 15 12:19:58 PM PDT 24
Peak memory 197772 kb
Host smart-72965473-d431-4477-99ca-ee7ca931e907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068192224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3068192224
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3410804767
Short name T743
Test name
Test status
Simulation time 33358508 ps
CPU time 0.86 seconds
Started Apr 15 12:19:53 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 197680 kb
Host smart-4a0acf9a-0223-44aa-b42c-c5718dddaa11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410804767 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3410804767
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2657686915
Short name T94
Test name
Test status
Simulation time 150788414 ps
CPU time 0.58 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 192112 kb
Host smart-723326ff-3532-429c-a0f7-2888cffd7c9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657686915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2657686915
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1059775776
Short name T776
Test name
Test status
Simulation time 36229138 ps
CPU time 0.55 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 193524 kb
Host smart-5f350222-b83c-47f3-b44a-aab67811aec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059775776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1059775776
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1413664483
Short name T787
Test name
Test status
Simulation time 18685382 ps
CPU time 0.7 seconds
Started Apr 15 12:20:59 PM PDT 24
Finished Apr 15 12:21:00 PM PDT 24
Peak memory 196152 kb
Host smart-7c4b241a-d813-43e1-a57b-d1f9441cf6c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413664483 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1413664483
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4198918696
Short name T765
Test name
Test status
Simulation time 59579380 ps
CPU time 1.02 seconds
Started Apr 15 12:19:47 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 197876 kb
Host smart-78d96958-ad89-4052-bc3e-e29e1b2d5cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198918696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4198918696
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3254271308
Short name T113
Test name
Test status
Simulation time 248460436 ps
CPU time 1.1 seconds
Started Apr 15 12:19:42 PM PDT 24
Finished Apr 15 12:19:44 PM PDT 24
Peak memory 198044 kb
Host smart-6d89807c-e033-4593-b8af-e384f85dfed1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254271308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3254271308
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1192052902
Short name T758
Test name
Test status
Simulation time 23141534 ps
CPU time 0.76 seconds
Started Apr 15 12:19:48 PM PDT 24
Finished Apr 15 12:19:50 PM PDT 24
Peak memory 197052 kb
Host smart-be6839c1-e4b7-4d44-850f-fd26884467db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192052902 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1192052902
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.7374049
Short name T87
Test name
Test status
Simulation time 14032660 ps
CPU time 0.6 seconds
Started Apr 15 12:19:50 PM PDT 24
Finished Apr 15 12:19:54 PM PDT 24
Peak memory 195004 kb
Host smart-d2b74c94-c4b1-4f18-b895-82dee6d29615
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7374049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ
=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_cs
r_rw.7374049
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4141054921
Short name T721
Test name
Test status
Simulation time 16735943 ps
CPU time 0.59 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:51 PM PDT 24
Peak memory 194188 kb
Host smart-f2f5c584-66ab-474a-b8ff-9124cc5093f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141054921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4141054921
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.216790822
Short name T103
Test name
Test status
Simulation time 66757828 ps
CPU time 0.88 seconds
Started Apr 15 12:19:51 PM PDT 24
Finished Apr 15 12:19:55 PM PDT 24
Peak memory 196044 kb
Host smart-fdc75c2e-2b7f-4b50-b2a6-4c457c2cf22a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216790822 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.216790822
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2675221175
Short name T715
Test name
Test status
Simulation time 198792225 ps
CPU time 2.24 seconds
Started Apr 15 12:19:49 PM PDT 24
Finished Apr 15 12:19:53 PM PDT 24
Peak memory 197992 kb
Host smart-03b85b48-a968-469e-977d-d89892249b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675221175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2675221175
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1392227974
Short name T799
Test name
Test status
Simulation time 493174041 ps
CPU time 0.91 seconds
Started Apr 15 12:19:53 PM PDT 24
Finished Apr 15 12:19:57 PM PDT 24
Peak memory 197204 kb
Host smart-d983ccd2-ae78-49fd-b368-1d8304baf667
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392227974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1392227974
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3219441692
Short name T256
Test name
Test status
Simulation time 19116130 ps
CPU time 0.56 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:17 PM PDT 24
Peak memory 193896 kb
Host smart-437e5b2d-4d5a-4560-b580-5074c5ec663b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219441692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3219441692
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.229077840
Short name T453
Test name
Test status
Simulation time 17414133 ps
CPU time 0.6 seconds
Started Apr 15 12:32:08 PM PDT 24
Finished Apr 15 12:32:10 PM PDT 24
Peak memory 193920 kb
Host smart-208a3409-6de2-47af-8227-6ac9069d1c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229077840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.229077840
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1733223124
Short name T226
Test name
Test status
Simulation time 551150511 ps
CPU time 17.31 seconds
Started Apr 15 12:32:08 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 196292 kb
Host smart-aba35923-0bf5-4a28-9d26-d8580861c1c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733223124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1733223124
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.981950567
Short name T527
Test name
Test status
Simulation time 630294048 ps
CPU time 0.87 seconds
Started Apr 15 12:32:13 PM PDT 24
Finished Apr 15 12:32:14 PM PDT 24
Peak memory 196140 kb
Host smart-d6f5ad6f-f942-443a-b094-0c612bb75db7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981950567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.981950567
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.157187609
Short name T225
Test name
Test status
Simulation time 80361696 ps
CPU time 0.76 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195632 kb
Host smart-4e230c80-856c-4e9f-926e-4fb8f04adcbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157187609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.157187609
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.526002170
Short name T605
Test name
Test status
Simulation time 172664335 ps
CPU time 1.35 seconds
Started Apr 15 12:32:06 PM PDT 24
Finished Apr 15 12:32:08 PM PDT 24
Peak memory 198072 kb
Host smart-6e850d7d-2a39-4e6e-930c-adf55295a623
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526002170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.526002170
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1491134684
Short name T603
Test name
Test status
Simulation time 154424725 ps
CPU time 2.89 seconds
Started Apr 15 12:32:11 PM PDT 24
Finished Apr 15 12:32:14 PM PDT 24
Peak memory 198088 kb
Host smart-4e76f9b7-916b-4d1a-a456-588afa0fb6ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491134684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1491134684
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1650329748
Short name T185
Test name
Test status
Simulation time 28639466 ps
CPU time 0.82 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 197444 kb
Host smart-5beaf34b-8c41-46a8-8d28-d28ab5ff929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650329748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1650329748
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3232115667
Short name T201
Test name
Test status
Simulation time 50880881 ps
CPU time 1 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:16 PM PDT 24
Peak memory 195900 kb
Host smart-d5040680-3de0-43ee-a608-4da015652a47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232115667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3232115667
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.351336119
Short name T327
Test name
Test status
Simulation time 403112607 ps
CPU time 4.48 seconds
Started Apr 15 12:32:08 PM PDT 24
Finished Apr 15 12:32:13 PM PDT 24
Peak memory 198092 kb
Host smart-57e1017d-655a-4e84-a123-6158ae3cdf48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351336119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.351336119
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.2291387525
Short name T142
Test name
Test status
Simulation time 38692875 ps
CPU time 0.86 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:16 PM PDT 24
Peak memory 196104 kb
Host smart-4965f4e5-d7d5-446b-8bb1-0438a65251ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291387525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2291387525
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1283341523
Short name T158
Test name
Test status
Simulation time 48605558 ps
CPU time 1.32 seconds
Started Apr 15 12:32:09 PM PDT 24
Finished Apr 15 12:32:11 PM PDT 24
Peak memory 196284 kb
Host smart-bb45186a-4104-46b0-a698-a7ecc30238d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283341523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1283341523
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1549163069
Short name T567
Test name
Test status
Simulation time 4824973041 ps
CPU time 68.35 seconds
Started Apr 15 12:32:08 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 198188 kb
Host smart-7ff1f507-a07f-4186-a75b-1f3e2526907e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549163069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1549163069
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4127800897
Short name T37
Test name
Test status
Simulation time 216513296359 ps
CPU time 2321.44 seconds
Started Apr 15 12:32:06 PM PDT 24
Finished Apr 15 01:10:49 PM PDT 24
Peak memory 198296 kb
Host smart-dfa488fa-72bd-4dd6-8889-832a9e3c354c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4127800897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4127800897
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.584527760
Short name T473
Test name
Test status
Simulation time 12663835 ps
CPU time 0.56 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:17 PM PDT 24
Peak memory 193932 kb
Host smart-f44a4b9a-e35d-40b0-a646-e833401d0df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584527760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.584527760
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1270399397
Short name T342
Test name
Test status
Simulation time 95666304 ps
CPU time 0.79 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:15 PM PDT 24
Peak memory 195456 kb
Host smart-3e3c6f4c-0ab9-48d5-abe9-90a4278d6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270399397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1270399397
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3390179295
Short name T571
Test name
Test status
Simulation time 1703255747 ps
CPU time 24.07 seconds
Started Apr 15 12:32:12 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 196904 kb
Host smart-766518cf-190b-47e1-ab41-a286eaca4e08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390179295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3390179295
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3601583826
Short name T395
Test name
Test status
Simulation time 147599447 ps
CPU time 0.7 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 194856 kb
Host smart-94bc608c-623d-4d05-85e4-1865a81a503d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601583826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3601583826
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3595606084
Short name T448
Test name
Test status
Simulation time 21717895 ps
CPU time 0.75 seconds
Started Apr 15 12:32:23 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 195440 kb
Host smart-9baecceb-8976-45c7-b493-c2935bbf9ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595606084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3595606084
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2087552345
Short name T153
Test name
Test status
Simulation time 115641259 ps
CPU time 1.28 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:16 PM PDT 24
Peak memory 197036 kb
Host smart-05ef7483-108b-4f9c-bf5a-622f47e88f48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087552345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2087552345
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1151322316
Short name T471
Test name
Test status
Simulation time 44561526 ps
CPU time 0.77 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 194608 kb
Host smart-a1d2b416-8548-48fe-8657-689fc0c58df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151322316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1151322316
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2164798569
Short name T389
Test name
Test status
Simulation time 18078942 ps
CPU time 0.74 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:31 PM PDT 24
Peak memory 195488 kb
Host smart-59135927-fd48-41fa-acce-672ece7a83a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164798569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2164798569
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2180823495
Short name T107
Test name
Test status
Simulation time 51319167 ps
CPU time 1.09 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 196592 kb
Host smart-9921d0a5-4d75-43a5-aa16-0d8eb04e5c5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180823495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2180823495
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3751259507
Short name T6
Test name
Test status
Simulation time 862034805 ps
CPU time 2.77 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 198000 kb
Host smart-40ba22ef-19b7-49d5-89f6-a40c545926fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751259507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3751259507
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.291705658
Short name T43
Test name
Test status
Simulation time 34242047 ps
CPU time 0.78 seconds
Started Apr 15 12:32:12 PM PDT 24
Finished Apr 15 12:32:13 PM PDT 24
Peak memory 213580 kb
Host smart-7d732f25-6fe2-494e-83d4-c36d0980212d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291705658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.291705658
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2470678067
Short name T115
Test name
Test status
Simulation time 70209027 ps
CPU time 1.33 seconds
Started Apr 15 12:32:05 PM PDT 24
Finished Apr 15 12:32:06 PM PDT 24
Peak memory 196884 kb
Host smart-a44e479f-ea3b-4366-8799-6f1ae5e972ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470678067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2470678067
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3173115869
Short name T200
Test name
Test status
Simulation time 48691942 ps
CPU time 1.38 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 195720 kb
Host smart-7cc730ad-3e69-4767-a643-71b531f85566
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173115869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3173115869
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1771821746
Short name T289
Test name
Test status
Simulation time 41899001873 ps
CPU time 29.25 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 198216 kb
Host smart-8712d8cf-24a9-4399-b9df-036ac284c2f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771821746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1771821746
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.653345241
Short name T652
Test name
Test status
Simulation time 54280617 ps
CPU time 0.56 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 193916 kb
Host smart-f8e2f898-31c6-473a-976f-7dd937eab0ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653345241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.653345241
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1123654364
Short name T528
Test name
Test status
Simulation time 25298215 ps
CPU time 0.79 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196140 kb
Host smart-d5a64bb8-3894-48c0-a85b-e844f95fd19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123654364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1123654364
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3562143786
Short name T400
Test name
Test status
Simulation time 608931967 ps
CPU time 15.95 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 196516 kb
Host smart-1d5c728a-2c95-478f-8b79-20d2dc421386
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562143786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3562143786
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.4263805406
Short name T309
Test name
Test status
Simulation time 223323205 ps
CPU time 1.04 seconds
Started Apr 15 12:32:10 PM PDT 24
Finished Apr 15 12:32:12 PM PDT 24
Peak memory 196680 kb
Host smart-72fec43b-bffd-4c09-87f9-b163ce2d99f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263805406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.4263805406
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1300771347
Short name T205
Test name
Test status
Simulation time 168078865 ps
CPU time 1.37 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 197228 kb
Host smart-fb72bed3-8b8e-49eb-990d-99f00147f46e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300771347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1300771347
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.267601075
Short name T206
Test name
Test status
Simulation time 311402180 ps
CPU time 3.11 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 198168 kb
Host smart-4699cf50-395f-4cc9-8461-156fd60ae8ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267601075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.267601075
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2402624371
Short name T412
Test name
Test status
Simulation time 101789278 ps
CPU time 1.3 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195864 kb
Host smart-94be33ff-a020-483a-adaf-0775e0d83139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402624371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2402624371
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.420335709
Short name T576
Test name
Test status
Simulation time 575065666 ps
CPU time 1.01 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196092 kb
Host smart-e01f7caa-5a03-446a-921f-9228cef3041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420335709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.420335709
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2432603456
Short name T685
Test name
Test status
Simulation time 37369881 ps
CPU time 0.96 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 196024 kb
Host smart-f4df3e90-e295-4d82-b2e2-bc55dacc8bfa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432603456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2432603456
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2992093837
Short name T608
Test name
Test status
Simulation time 77727199 ps
CPU time 1.73 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 197924 kb
Host smart-c92ef738-636c-4db5-bf06-a56b82a6a48e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992093837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2992093837
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1664576639
Short name T696
Test name
Test status
Simulation time 45763347 ps
CPU time 1.06 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195640 kb
Host smart-195f2509-b2fe-45a9-97fe-39669079333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664576639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1664576639
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1340466722
Short name T514
Test name
Test status
Simulation time 173278140 ps
CPU time 1.27 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 195580 kb
Host smart-817cfe3a-7528-4ec4-b3f6-c12eccc53813
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340466722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1340466722
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.825176436
Short name T310
Test name
Test status
Simulation time 16088285383 ps
CPU time 94.47 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:33:56 PM PDT 24
Peak memory 198168 kb
Host smart-48afde3a-3d24-416e-af3d-2202e994d00e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825176436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.825176436
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3232365517
Short name T531
Test name
Test status
Simulation time 151087883847 ps
CPU time 958.48 seconds
Started Apr 15 12:32:34 PM PDT 24
Finished Apr 15 12:48:33 PM PDT 24
Peak memory 198208 kb
Host smart-08b61f35-760d-432e-a08c-eff346b041e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3232365517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3232365517
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1274367185
Short name T28
Test name
Test status
Simulation time 94532968 ps
CPU time 0.55 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 191952 kb
Host smart-b3745f7a-9cfc-4989-88f4-26f310435a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274367185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1274367185
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1478350435
Short name T146
Test name
Test status
Simulation time 167067130 ps
CPU time 0.87 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 196512 kb
Host smart-d66cb17c-ba93-4541-a972-f839540e6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478350435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1478350435
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2780592445
Short name T344
Test name
Test status
Simulation time 3088970717 ps
CPU time 23.79 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:51 PM PDT 24
Peak memory 197392 kb
Host smart-6b5e003f-2371-439a-87d9-53527e7ae3d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780592445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2780592445
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2955814555
Short name T294
Test name
Test status
Simulation time 76707113 ps
CPU time 0.62 seconds
Started Apr 15 12:32:35 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 194308 kb
Host smart-9adb917b-dde4-4c85-969c-25496938fba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955814555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2955814555
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1174680705
Short name T390
Test name
Test status
Simulation time 36153359 ps
CPU time 0.96 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195820 kb
Host smart-0be2428d-efef-47fe-90e2-096295b8a16d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174680705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1174680705
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1391563621
Short name T58
Test name
Test status
Simulation time 26629694 ps
CPU time 1.09 seconds
Started Apr 15 12:32:30 PM PDT 24
Finished Apr 15 12:32:31 PM PDT 24
Peak memory 197108 kb
Host smart-4a5aa5b0-3dec-467e-8bd6-212e18296801
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391563621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1391563621
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.737924841
Short name T361
Test name
Test status
Simulation time 462640274 ps
CPU time 2.26 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 197268 kb
Host smart-068d53b3-76bf-45a6-b05f-797f272f2583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737924841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
737924841
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3654490184
Short name T322
Test name
Test status
Simulation time 309859478 ps
CPU time 1.24 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 195940 kb
Host smart-0bad352f-e4b8-4645-b276-3eb23edbc428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654490184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3654490184
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2204071847
Short name T372
Test name
Test status
Simulation time 34612820 ps
CPU time 1.24 seconds
Started Apr 15 12:33:27 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 196800 kb
Host smart-2db8a9ac-ab43-4f7c-a4d7-b07481a116ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204071847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2204071847
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1912039033
Short name T279
Test name
Test status
Simulation time 1134147714 ps
CPU time 3.78 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 198116 kb
Host smart-3e5ecc05-e7c3-42ce-b66d-1c38f17c709e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912039033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1912039033
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3342944548
Short name T302
Test name
Test status
Simulation time 34462769 ps
CPU time 0.85 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 196060 kb
Host smart-c1ff4cf9-9828-4bf0-9f7d-fcc69414179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342944548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3342944548
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1861285357
Short name T709
Test name
Test status
Simulation time 112209976 ps
CPU time 0.97 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195760 kb
Host smart-bef67b37-128b-4ac6-bad5-339687002325
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861285357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1861285357
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3562427557
Short name T550
Test name
Test status
Simulation time 5409653347 ps
CPU time 29.63 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 198284 kb
Host smart-4b305cd3-5aed-415d-836f-a168e5ee6e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562427557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3562427557
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3922469471
Short name T664
Test name
Test status
Simulation time 14189857 ps
CPU time 0.58 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 194752 kb
Host smart-8db09189-c7e7-4e4e-850d-48f245e75f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922469471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3922469471
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.50338478
Short name T284
Test name
Test status
Simulation time 30913959 ps
CPU time 0.75 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195320 kb
Host smart-9d8c3bf4-86db-49a9-85eb-dcc39e0b4531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50338478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.50338478
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3043130331
Short name T671
Test name
Test status
Simulation time 1206372707 ps
CPU time 8.62 seconds
Started Apr 15 12:32:23 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 195560 kb
Host smart-d30c555e-6c83-45e7-ac13-c765860504b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043130331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3043130331
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3845999627
Short name T210
Test name
Test status
Simulation time 42361934 ps
CPU time 0.74 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195848 kb
Host smart-61076a61-6e0c-463c-b0e8-601825e769ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845999627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3845999627
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3796992982
Short name T71
Test name
Test status
Simulation time 200908337 ps
CPU time 1.42 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 196592 kb
Host smart-8f284d51-5b65-41bf-abb6-04bf5154eb86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796992982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3796992982
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.234930153
Short name T227
Test name
Test status
Simulation time 44012164 ps
CPU time 1.73 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 198096 kb
Host smart-e656715b-f8a6-4662-8823-ea469cdcfc4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234930153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.234930153
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2055278255
Short name T456
Test name
Test status
Simulation time 195298950 ps
CPU time 1.14 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 197368 kb
Host smart-7dd81ca5-c821-4b25-8266-ffc1fc54708b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055278255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2055278255
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2147221703
Short name T296
Test name
Test status
Simulation time 194347099 ps
CPU time 1.08 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 196584 kb
Host smart-5be95554-9a56-4f57-a3e7-cc5f54079a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147221703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2147221703
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.737531702
Short name T612
Test name
Test status
Simulation time 20852428 ps
CPU time 0.85 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 196728 kb
Host smart-c1373a6d-715a-4532-8b8a-376cd109be3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737531702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.737531702
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2117503353
Short name T506
Test name
Test status
Simulation time 119027346 ps
CPU time 2.17 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 198080 kb
Host smart-fc62220f-3e4b-49d4-be9b-71b135b2bc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117503353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2117503353
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2349955843
Short name T336
Test name
Test status
Simulation time 84159144 ps
CPU time 1.27 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195844 kb
Host smart-5ac6d989-3447-43f1-b0d9-f807767bbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349955843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2349955843
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1804096253
Short name T552
Test name
Test status
Simulation time 81163659 ps
CPU time 1.34 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196240 kb
Host smart-6d1aff94-e9ce-4c99-8693-749caabb73b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804096253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1804096253
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3916131453
Short name T143
Test name
Test status
Simulation time 8727363014 ps
CPU time 216.49 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 198220 kb
Host smart-27b589e3-cb1f-4ac8-a247-2e5c33b6c0fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916131453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3916131453
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3269204776
Short name T234
Test name
Test status
Simulation time 12850579 ps
CPU time 0.56 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 193912 kb
Host smart-6ae0eb28-2919-422c-8c21-d2c721266564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269204776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3269204776
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2284570400
Short name T145
Test name
Test status
Simulation time 206605456 ps
CPU time 0.9 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 196776 kb
Host smart-253e1328-96d3-432b-b3c6-401833b2a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284570400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2284570400
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4216220579
Short name T656
Test name
Test status
Simulation time 349819351 ps
CPU time 17.34 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:44 PM PDT 24
Peak memory 194864 kb
Host smart-8cd56209-2190-4e9f-8fc7-31ebb814fe50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216220579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4216220579
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2870639988
Short name T191
Test name
Test status
Simulation time 60898377 ps
CPU time 0.96 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 197012 kb
Host smart-d6fd8d16-4b9b-4852-969d-5e5085c31502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870639988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2870639988
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2762765711
Short name T121
Test name
Test status
Simulation time 79796104 ps
CPU time 0.84 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 195588 kb
Host smart-ccdf12eb-5943-4129-beed-e3c1847ec967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762765711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2762765711
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3180274756
Short name T399
Test name
Test status
Simulation time 71133100 ps
CPU time 0.94 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 196124 kb
Host smart-01a9c38b-3f35-42d9-b424-434efb5d5188
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180274756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3180274756
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1866755224
Short name T61
Test name
Test status
Simulation time 28889961 ps
CPU time 0.94 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 195604 kb
Host smart-fa78c892-0a4c-4238-8186-196002058c4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866755224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1866755224
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1993223025
Short name T543
Test name
Test status
Simulation time 47409274 ps
CPU time 0.75 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 195276 kb
Host smart-3a7cd577-f34c-4be0-a254-782218f5abab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993223025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1993223025
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1681216995
Short name T627
Test name
Test status
Simulation time 52131453 ps
CPU time 0.8 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195572 kb
Host smart-3e02e7be-1c0f-46b8-801f-ef3e9a89fc8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681216995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1681216995
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.199356579
Short name T595
Test name
Test status
Simulation time 210570170 ps
CPU time 1.56 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 197988 kb
Host smart-60fe010d-2516-4afd-90d5-4ef331bbf830
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199356579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.199356579
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.511757964
Short name T494
Test name
Test status
Simulation time 373737907 ps
CPU time 1.15 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195788 kb
Host smart-c1056bad-3bf7-4d5c-8505-3f7a154ede66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511757964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.511757964
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3379244120
Short name T292
Test name
Test status
Simulation time 125629409 ps
CPU time 1.21 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 195912 kb
Host smart-687a41aa-49c0-4989-8763-e2b17a2be723
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379244120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3379244120
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2298821722
Short name T391
Test name
Test status
Simulation time 12221507890 ps
CPU time 161.86 seconds
Started Apr 15 12:32:31 PM PDT 24
Finished Apr 15 12:35:14 PM PDT 24
Peak memory 198168 kb
Host smart-4492711b-d8d0-4bca-a6f5-2a53d12eff13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298821722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2298821722
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2699919088
Short name T69
Test name
Test status
Simulation time 18095513015 ps
CPU time 418.43 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:39:26 PM PDT 24
Peak memory 198332 kb
Host smart-9a6a18a3-777e-479c-974d-ac7daca3baa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2699919088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2699919088
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.267192456
Short name T303
Test name
Test status
Simulation time 13961123 ps
CPU time 0.57 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 194568 kb
Host smart-e02b29db-1753-4e92-a75d-d7c23cace1dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267192456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.267192456
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.949749598
Short name T393
Test name
Test status
Simulation time 75626018 ps
CPU time 0.77 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196024 kb
Host smart-47725c9b-38bf-4c0b-b66f-8af4f5f7d839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949749598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.949749598
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1659807163
Short name T313
Test name
Test status
Simulation time 1633546978 ps
CPU time 22.4 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 197164 kb
Host smart-b7bdd95b-cbfc-4911-9c80-1edf32a7c351
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659807163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1659807163
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3993287903
Short name T545
Test name
Test status
Simulation time 83986120 ps
CPU time 1.06 seconds
Started Apr 15 12:32:25 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 197732 kb
Host smart-009fd34b-c869-4a55-aa41-dc9fa2e4d872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993287903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3993287903
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2242992397
Short name T365
Test name
Test status
Simulation time 89196404 ps
CPU time 1.31 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 197068 kb
Host smart-45a10737-a3b1-4944-a852-aeb981e30b06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242992397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2242992397
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1455615816
Short name T188
Test name
Test status
Simulation time 320836124 ps
CPU time 3.33 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 198312 kb
Host smart-6c86378e-96d6-4661-a032-20bc67116745
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455615816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1455615816
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3381567761
Short name T475
Test name
Test status
Simulation time 908020784 ps
CPU time 1.84 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 198248 kb
Host smart-5e6b48ba-f562-4f04-91ab-99f37717289d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381567761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3381567761
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2432826809
Short name T610
Test name
Test status
Simulation time 88486017 ps
CPU time 0.74 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:17 PM PDT 24
Peak memory 195572 kb
Host smart-21074693-6032-4334-b94f-c0ffb430424b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432826809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2432826809
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4209663016
Short name T388
Test name
Test status
Simulation time 107299933 ps
CPU time 4.75 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 198040 kb
Host smart-eceba42b-b6eb-42c1-948d-bca1c39149b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209663016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4209663016
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1440757706
Short name T245
Test name
Test status
Simulation time 57758108 ps
CPU time 1.07 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 195792 kb
Host smart-e16a69bc-712e-4ca2-b7b1-e34c4d347391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440757706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1440757706
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3964563985
Short name T16
Test name
Test status
Simulation time 178445481 ps
CPU time 1.31 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 198044 kb
Host smart-07a5bebf-a20a-4ca4-8f48-509dd1ff0af1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964563985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3964563985
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3521530740
Short name T204
Test name
Test status
Simulation time 8996705379 ps
CPU time 108.82 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:34:15 PM PDT 24
Peak memory 198184 kb
Host smart-7cedf38e-252d-48b3-bcb5-320f1a25c488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521530740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3521530740
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1680223127
Short name T243
Test name
Test status
Simulation time 31130942 ps
CPU time 0.58 seconds
Started Apr 15 12:32:29 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 194032 kb
Host smart-d95acf52-b20d-4b1d-9b77-95025b47ef90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680223127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1680223127
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2482593273
Short name T615
Test name
Test status
Simulation time 122760389 ps
CPU time 0.78 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195472 kb
Host smart-190d4094-07ff-4743-beb3-95f56f5f2a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482593273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2482593273
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2906135317
Short name T275
Test name
Test status
Simulation time 2398478965 ps
CPU time 16.74 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:39 PM PDT 24
Peak memory 196928 kb
Host smart-a6649134-3591-4b4b-8e03-1a15d2dda542
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906135317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2906135317
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1647759642
Short name T7
Test name
Test status
Simulation time 280868609 ps
CPU time 0.88 seconds
Started Apr 15 12:32:42 PM PDT 24
Finished Apr 15 12:32:43 PM PDT 24
Peak memory 196168 kb
Host smart-0c2999bd-996f-4338-87f9-739aeec84e28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647759642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1647759642
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3571765729
Short name T224
Test name
Test status
Simulation time 379080720 ps
CPU time 1.29 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 197020 kb
Host smart-01f5f6bb-a54e-4261-a089-7fb977a38dc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571765729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3571765729
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.972503614
Short name T711
Test name
Test status
Simulation time 40132662 ps
CPU time 1.58 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 196516 kb
Host smart-b922b6e6-5249-4165-a856-b8bf2ba15e01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972503614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.972503614
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.390325869
Short name T428
Test name
Test status
Simulation time 43276980 ps
CPU time 1.09 seconds
Started Apr 15 12:32:35 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 195672 kb
Host smart-556118d1-d27f-421f-92d3-0990b30d1a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390325869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
390325869
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1639508152
Short name T367
Test name
Test status
Simulation time 316705351 ps
CPU time 0.92 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196144 kb
Host smart-c4dc4602-f9d4-4ee5-8084-31af2d803173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639508152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1639508152
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3775000297
Short name T519
Test name
Test status
Simulation time 40580592 ps
CPU time 0.96 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 195812 kb
Host smart-9fd08428-e98d-44b9-8828-726b6ec82e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775000297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3775000297
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4243794412
Short name T337
Test name
Test status
Simulation time 157653302 ps
CPU time 1.28 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 198052 kb
Host smart-0b791dfc-d700-4cad-8b7c-c262501bb526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243794412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4243794412
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3919066567
Short name T325
Test name
Test status
Simulation time 125236604 ps
CPU time 1.04 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 195824 kb
Host smart-7d6f0e94-7d5d-4a7e-9296-f45e63f91f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919066567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3919066567
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2354604494
Short name T118
Test name
Test status
Simulation time 252984329 ps
CPU time 1.06 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195668 kb
Host smart-bd39a4b1-43b8-4d71-845d-c2cccf809961
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354604494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2354604494
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2642923940
Short name T175
Test name
Test status
Simulation time 143456606794 ps
CPU time 103.51 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:34:11 PM PDT 24
Peak memory 198136 kb
Host smart-04d87ca1-36bb-4a2f-96ee-dffc67e8a9b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642923940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2642923940
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2830710395
Short name T626
Test name
Test status
Simulation time 17728729 ps
CPU time 0.57 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:35 PM PDT 24
Peak memory 193936 kb
Host smart-d48dcdf1-8f1c-45c4-9254-6a6e4fd28588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830710395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2830710395
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2812050286
Short name T680
Test name
Test status
Simulation time 78566966 ps
CPU time 0.81 seconds
Started Apr 15 12:32:45 PM PDT 24
Finished Apr 15 12:32:46 PM PDT 24
Peak memory 195424 kb
Host smart-b529f233-3b0d-46bf-a786-b036f0c4e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812050286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2812050286
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.789196622
Short name T131
Test name
Test status
Simulation time 1889925736 ps
CPU time 22.56 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:50 PM PDT 24
Peak memory 196596 kb
Host smart-7844ae5c-e97e-462a-b68c-4a8c0bfbf074
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789196622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.789196622
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2357012841
Short name T406
Test name
Test status
Simulation time 277947855 ps
CPU time 1.05 seconds
Started Apr 15 12:32:25 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 196412 kb
Host smart-86b2325e-fad5-4f65-9e55-dc1c1e8a14fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357012841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2357012841
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3941940511
Short name T257
Test name
Test status
Simulation time 108575852 ps
CPU time 0.84 seconds
Started Apr 15 12:32:28 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 196216 kb
Host smart-d9ffebf1-ce82-46b1-a661-608711656aea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941940511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3941940511
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2262756478
Short name T499
Test name
Test status
Simulation time 58556466 ps
CPU time 1.25 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196904 kb
Host smart-89714778-f459-44a7-b3a9-62f95bc398bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262756478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2262756478
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1796979981
Short name T18
Test name
Test status
Simulation time 45118198 ps
CPU time 1.45 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 196132 kb
Host smart-3a99c585-97e0-4028-abf2-b9b8aac3070c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796979981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1796979981
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.406527065
Short name T238
Test name
Test status
Simulation time 63648342 ps
CPU time 1.07 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 195864 kb
Host smart-88e98c44-bdd4-4b89-b06c-ee697df8a472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406527065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.406527065
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.817955675
Short name T588
Test name
Test status
Simulation time 21617411 ps
CPU time 0.69 seconds
Started Apr 15 12:32:37 PM PDT 24
Finished Apr 15 12:32:38 PM PDT 24
Peak memory 195044 kb
Host smart-c3ad71c0-72a7-4a8d-a8d7-e71b497f71e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817955675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.817955675
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1447118115
Short name T660
Test name
Test status
Simulation time 338757341 ps
CPU time 5.49 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 198032 kb
Host smart-8a08c7f7-2837-4864-a8a4-208bdfe999b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447118115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1447118115
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.485509361
Short name T416
Test name
Test status
Simulation time 200798424 ps
CPU time 1.13 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:32:56 PM PDT 24
Peak memory 195832 kb
Host smart-ead691f7-2383-40df-abf5-4ee80ce1cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485509361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.485509361
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2977355545
Short name T689
Test name
Test status
Simulation time 185938318 ps
CPU time 1.07 seconds
Started Apr 15 12:32:23 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 196520 kb
Host smart-28c0a0fe-2477-43f0-9582-9b999732d776
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977355545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2977355545
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1767773402
Short name T369
Test name
Test status
Simulation time 46195312867 ps
CPU time 116.07 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:34:24 PM PDT 24
Peak memory 198272 kb
Host smart-831898cd-ff73-44f5-b1c1-281bed873f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767773402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1767773402
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.942808029
Short name T211
Test name
Test status
Simulation time 49562852 ps
CPU time 0.53 seconds
Started Apr 15 12:32:39 PM PDT 24
Finished Apr 15 12:32:40 PM PDT 24
Peak memory 194616 kb
Host smart-f54606c0-6727-4cee-b251-a380a9e94b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942808029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.942808029
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.187285386
Short name T526
Test name
Test status
Simulation time 37003091 ps
CPU time 0.85 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 197344 kb
Host smart-cf659705-854a-4344-a6cc-e5558fd8b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187285386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.187285386
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3525012769
Short name T446
Test name
Test status
Simulation time 901598696 ps
CPU time 14.52 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:33:09 PM PDT 24
Peak memory 196328 kb
Host smart-ad43526e-1be6-4b86-bf3b-7e05722c8dbf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525012769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3525012769
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3231351457
Short name T10
Test name
Test status
Simulation time 27694395 ps
CPU time 0.66 seconds
Started Apr 15 12:32:29 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 194504 kb
Host smart-85cba670-af8c-4b47-b79a-d4b171d61690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231351457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3231351457
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1126464350
Short name T597
Test name
Test status
Simulation time 40980901 ps
CPU time 0.65 seconds
Started Apr 15 12:32:30 PM PDT 24
Finished Apr 15 12:32:31 PM PDT 24
Peak memory 194396 kb
Host smart-e4dd102a-418f-4066-9da3-b10c3376d4a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126464350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1126464350
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3593111395
Short name T126
Test name
Test status
Simulation time 50262296 ps
CPU time 1.17 seconds
Started Apr 15 12:32:42 PM PDT 24
Finished Apr 15 12:32:43 PM PDT 24
Peak memory 195644 kb
Host smart-f60508a2-3cf9-492e-bf18-e253131c46b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593111395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3593111395
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4015769408
Short name T271
Test name
Test status
Simulation time 130886224 ps
CPU time 0.8 seconds
Started Apr 15 12:32:25 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 196224 kb
Host smart-d50b7263-12f8-4ef0-bade-419c2833c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015769408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4015769408
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2135215146
Short name T333
Test name
Test status
Simulation time 68229158 ps
CPU time 0.82 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:35 PM PDT 24
Peak memory 195476 kb
Host smart-0eb117dc-0c75-4873-83cd-7084446a710f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135215146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2135215146
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3074384431
Short name T683
Test name
Test status
Simulation time 38148088 ps
CPU time 1.59 seconds
Started Apr 15 12:32:30 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 198088 kb
Host smart-d4c01502-5604-4388-9a68-d76bdc4a55e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074384431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3074384431
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.701462597
Short name T632
Test name
Test status
Simulation time 270771748 ps
CPU time 1.14 seconds
Started Apr 15 12:32:31 PM PDT 24
Finished Apr 15 12:32:33 PM PDT 24
Peak memory 196272 kb
Host smart-4efe4bbc-df83-40f0-8dea-c7337881d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701462597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.701462597
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2948766
Short name T657
Test name
Test status
Simulation time 234803155 ps
CPU time 0.92 seconds
Started Apr 15 12:32:32 PM PDT 24
Finished Apr 15 12:32:33 PM PDT 24
Peak memory 195752 kb
Host smart-b917dd76-e092-4630-b630-42759572e38a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2948766
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2724503829
Short name T301
Test name
Test status
Simulation time 72967593803 ps
CPU time 190.78 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:35:37 PM PDT 24
Peak memory 198280 kb
Host smart-c9e31d1b-c4d0-4020-9d9b-43668f0dc8de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724503829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2724503829
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.922097875
Short name T694
Test name
Test status
Simulation time 15371711 ps
CPU time 0.57 seconds
Started Apr 15 12:32:28 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 193908 kb
Host smart-3d919a18-a666-4a88-a175-24dcdb6b780c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922097875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.922097875
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3998385066
Short name T132
Test name
Test status
Simulation time 22540396 ps
CPU time 0.64 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 194720 kb
Host smart-ba2ed732-2cd7-4526-a504-711431ac3d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998385066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3998385066
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.229688748
Short name T32
Test name
Test status
Simulation time 888393996 ps
CPU time 24.89 seconds
Started Apr 15 12:32:48 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 196960 kb
Host smart-5c32f633-fd39-486b-86ad-d939869093b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229688748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.229688748
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2725125573
Short name T35
Test name
Test status
Simulation time 164528665 ps
CPU time 0.82 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:35 PM PDT 24
Peak memory 196012 kb
Host smart-4c1d990a-89dc-4df0-a348-5797b4a2d33c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725125573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2725125573
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3070727016
Short name T533
Test name
Test status
Simulation time 78706060 ps
CPU time 1.16 seconds
Started Apr 15 12:32:49 PM PDT 24
Finished Apr 15 12:32:51 PM PDT 24
Peak memory 196092 kb
Host smart-d5c2d78d-8a1b-4bee-ba71-dcb65566543f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070727016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3070727016
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3697158848
Short name T156
Test name
Test status
Simulation time 75731545 ps
CPU time 2.81 seconds
Started Apr 15 12:32:29 PM PDT 24
Finished Apr 15 12:32:33 PM PDT 24
Peak memory 198184 kb
Host smart-63af1f6d-5aea-420d-af2e-ee8e5b2b0fe3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697158848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3697158848
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1311770607
Short name T402
Test name
Test status
Simulation time 84516897 ps
CPU time 0.96 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195492 kb
Host smart-212ad31d-bed3-4844-88c6-7acca8216ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311770607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1311770607
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2360979480
Short name T560
Test name
Test status
Simulation time 43284721 ps
CPU time 1.06 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:52 PM PDT 24
Peak memory 196120 kb
Host smart-9bc8ce17-eae9-465f-88c4-228421a3eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360979480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2360979480
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1489781245
Short name T515
Test name
Test status
Simulation time 194300455 ps
CPU time 1.12 seconds
Started Apr 15 12:32:34 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 197064 kb
Host smart-eaa73a64-e4e8-4a1f-947c-0ad5080be2f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489781245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1489781245
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1054187739
Short name T442
Test name
Test status
Simulation time 372094027 ps
CPU time 4.33 seconds
Started Apr 15 12:32:31 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 198052 kb
Host smart-fd0985da-7477-4354-b08b-93d8871cc481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054187739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1054187739
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.510667696
Short name T654
Test name
Test status
Simulation time 245047899 ps
CPU time 1.2 seconds
Started Apr 15 12:32:32 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 197204 kb
Host smart-2ab596ec-5db0-4563-bb47-a7df827dfd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510667696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.510667696
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2937851535
Short name T259
Test name
Test status
Simulation time 70994993 ps
CPU time 1.24 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:52 PM PDT 24
Peak memory 195864 kb
Host smart-8e365e07-d714-4f5b-909d-650fbefc6394
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937851535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2937851535
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3914608672
Short name T611
Test name
Test status
Simulation time 6550840731 ps
CPU time 170.22 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:35:24 PM PDT 24
Peak memory 198132 kb
Host smart-751487a7-8d7b-48bd-bdef-37467977d4de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914608672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3914608672
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.555152931
Short name T68
Test name
Test status
Simulation time 51312175870 ps
CPU time 736.83 seconds
Started Apr 15 12:32:48 PM PDT 24
Finished Apr 15 12:45:06 PM PDT 24
Peak memory 198212 kb
Host smart-7573cb13-ad65-44f8-9212-7fd8f8e64238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=555152931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.555152931
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.513536385
Short name T192
Test name
Test status
Simulation time 60349376 ps
CPU time 0.58 seconds
Started Apr 15 12:33:02 PM PDT 24
Finished Apr 15 12:33:04 PM PDT 24
Peak memory 193892 kb
Host smart-60b603b4-bfc7-4051-875d-acdf8556d3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513536385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.513536385
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3276879265
Short name T491
Test name
Test status
Simulation time 24062320 ps
CPU time 0.81 seconds
Started Apr 15 12:32:50 PM PDT 24
Finished Apr 15 12:32:52 PM PDT 24
Peak memory 197184 kb
Host smart-6e766224-7bf9-4004-b184-993df6ccccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276879265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3276879265
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2053631472
Short name T62
Test name
Test status
Simulation time 3181012781 ps
CPU time 26.13 seconds
Started Apr 15 12:32:52 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 197088 kb
Host smart-8ca8d59b-5891-4de2-bdae-46de78240e1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053631472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2053631472
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.794527959
Short name T551
Test name
Test status
Simulation time 40857457 ps
CPU time 0.75 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 195992 kb
Host smart-d3dfc784-d4a9-4df2-84e7-b9cb98123ad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794527959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.794527959
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1155666604
Short name T534
Test name
Test status
Simulation time 26165287 ps
CPU time 0.83 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:32:56 PM PDT 24
Peak memory 195652 kb
Host smart-bdec94a8-e8e8-4f88-86ba-0045f9b20d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155666604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1155666604
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3901946914
Short name T386
Test name
Test status
Simulation time 289045610 ps
CPU time 2.89 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:55 PM PDT 24
Peak memory 196700 kb
Host smart-7d04756e-42e6-4489-bce0-8b467965a7cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901946914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3901946914
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2533360079
Short name T375
Test name
Test status
Simulation time 29230527 ps
CPU time 0.92 seconds
Started Apr 15 12:32:53 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 196252 kb
Host smart-796088e8-0d7f-47df-b891-3e43cc3c8e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533360079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2533360079
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.415523624
Short name T317
Test name
Test status
Simulation time 35361477 ps
CPU time 0.95 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:32:58 PM PDT 24
Peak memory 196624 kb
Host smart-68b96483-ea75-4046-8663-39939c2a8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415523624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.415523624
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1782694854
Short name T172
Test name
Test status
Simulation time 129805155 ps
CPU time 1.17 seconds
Started Apr 15 12:32:45 PM PDT 24
Finished Apr 15 12:32:47 PM PDT 24
Peak memory 195840 kb
Host smart-bd1f5485-ade7-4f90-87c6-647ed33bd3ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782694854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1782694854
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.600638781
Short name T277
Test name
Test status
Simulation time 221664955 ps
CPU time 3.79 seconds
Started Apr 15 12:33:01 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 197960 kb
Host smart-079c6870-9dfc-4960-8347-58833adce3d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600638781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.600638781
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.893221669
Short name T55
Test name
Test status
Simulation time 142763682 ps
CPU time 1.07 seconds
Started Apr 15 12:32:57 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 195864 kb
Host smart-e42e4cf4-a765-4af5-8627-3a07e5cf5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893221669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.893221669
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2522940021
Short name T518
Test name
Test status
Simulation time 106782954 ps
CPU time 0.92 seconds
Started Apr 15 12:32:53 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 195948 kb
Host smart-566a04d5-335a-4cb4-9940-7fb767a80fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522940021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2522940021
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.821486185
Short name T76
Test name
Test status
Simulation time 8203344921 ps
CPU time 211.84 seconds
Started Apr 15 12:32:28 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 198144 kb
Host smart-9c43ee3a-1dfe-4998-8c92-59d8d737cff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821486185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.821486185
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2952669773
Short name T363
Test name
Test status
Simulation time 48964341455 ps
CPU time 591.76 seconds
Started Apr 15 12:32:58 PM PDT 24
Finished Apr 15 12:42:50 PM PDT 24
Peak memory 198300 kb
Host smart-98821988-4a86-4f7d-9f34-c07fac1ba35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2952669773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2952669773
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1408278056
Short name T409
Test name
Test status
Simulation time 36906707 ps
CPU time 0.55 seconds
Started Apr 15 12:32:29 PM PDT 24
Finished Apr 15 12:32:31 PM PDT 24
Peak memory 193884 kb
Host smart-c23419b0-78a7-4552-8469-b16c6661a43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408278056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1408278056
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.737686381
Short name T331
Test name
Test status
Simulation time 57560718 ps
CPU time 0.95 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196448 kb
Host smart-ae994a7e-b541-4486-8d53-17558debcb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737686381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.737686381
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1220885738
Short name T345
Test name
Test status
Simulation time 1682419445 ps
CPU time 23.97 seconds
Started Apr 15 12:32:10 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 195584 kb
Host smart-f1a82cec-c3df-44fc-8de2-37322c688438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220885738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1220885738
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.73246177
Short name T618
Test name
Test status
Simulation time 53966533 ps
CPU time 0.88 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 197824 kb
Host smart-b3007ba7-4af8-4151-9c6b-289971797ec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73246177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.73246177
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.886077508
Short name T133
Test name
Test status
Simulation time 84029823 ps
CPU time 1.26 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:16 PM PDT 24
Peak memory 198080 kb
Host smart-a61a4016-65e4-43f6-ad7d-073112b42f5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886077508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.886077508
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.724281297
Short name T184
Test name
Test status
Simulation time 104723835 ps
CPU time 2.21 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 197992 kb
Host smart-26e94743-4be4-447e-ae14-7c47aaaa9616
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724281297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.724281297
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2458806275
Short name T397
Test name
Test status
Simulation time 105828635 ps
CPU time 0.92 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 196156 kb
Host smart-20616975-5a62-4904-ba7c-d35b38f96f37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458806275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2458806275
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.486535474
Short name T563
Test name
Test status
Simulation time 26210905 ps
CPU time 0.71 seconds
Started Apr 15 12:32:23 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 195364 kb
Host smart-8bfb5948-1d10-423f-a995-7b8a46a322ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486535474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.486535474
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1430918302
Short name T380
Test name
Test status
Simulation time 114790323 ps
CPU time 1.16 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:15 PM PDT 24
Peak memory 195892 kb
Host smart-155d5d6a-6692-43b2-929b-5312d9fed500
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430918302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1430918302
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4281756646
Short name T481
Test name
Test status
Simulation time 394489368 ps
CPU time 4.49 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 198096 kb
Host smart-6bd2451e-b2c1-49a6-aa73-8333fb39411b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281756646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4281756646
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2830189668
Short name T53
Test name
Test status
Simulation time 36485757 ps
CPU time 0.8 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:17 PM PDT 24
Peak memory 213548 kb
Host smart-8f7b0416-6596-4585-8423-49129adf7637
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830189668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2830189668
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1212475844
Short name T697
Test name
Test status
Simulation time 51038006 ps
CPU time 1.06 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196644 kb
Host smart-be8f124e-70cb-46f9-aa20-762416b0dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212475844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1212475844
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3048153756
Short name T712
Test name
Test status
Simulation time 44943796 ps
CPU time 0.91 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 196416 kb
Host smart-7adc8b50-f3b4-4b92-93ed-7e03ae3f6871
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048153756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3048153756
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1874885519
Short name T513
Test name
Test status
Simulation time 10089568236 ps
CPU time 84.5 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:33:46 PM PDT 24
Peak memory 198176 kb
Host smart-8c47f2bf-d5e9-4720-9a4e-76320a629892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874885519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1874885519
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.587237402
Short name T67
Test name
Test status
Simulation time 205298058030 ps
CPU time 914.91 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:47:34 PM PDT 24
Peak memory 198188 kb
Host smart-89c62569-bc3b-40a0-8033-db3d8ffe55d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=587237402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.587237402
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3830642828
Short name T476
Test name
Test status
Simulation time 13911062 ps
CPU time 0.58 seconds
Started Apr 15 12:32:52 PM PDT 24
Finished Apr 15 12:32:53 PM PDT 24
Peak memory 194644 kb
Host smart-aeb38b54-e115-4aa8-b1f7-a4f179cae387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830642828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3830642828
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3292674188
Short name T136
Test name
Test status
Simulation time 80463895 ps
CPU time 0.72 seconds
Started Apr 15 12:32:31 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 194952 kb
Host smart-8bc7f76a-fdb3-4157-89db-9e207565eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292674188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3292674188
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2676633574
Short name T436
Test name
Test status
Simulation time 333708334 ps
CPU time 10.64 seconds
Started Apr 15 12:32:52 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 196252 kb
Host smart-4e4fee0e-ee54-48c1-98d9-16a4b2f2bc38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676633574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2676633574
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3864783649
Short name T324
Test name
Test status
Simulation time 579319932 ps
CPU time 0.96 seconds
Started Apr 15 12:32:46 PM PDT 24
Finished Apr 15 12:32:47 PM PDT 24
Peak memory 197332 kb
Host smart-03986f47-69b0-4b93-ae91-ffd7bce5a30d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864783649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3864783649
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3251927294
Short name T249
Test name
Test status
Simulation time 46474822 ps
CPU time 0.71 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 195612 kb
Host smart-d54dfe46-c4d6-4802-a113-38b17dd84547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251927294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3251927294
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3588131059
Short name T293
Test name
Test status
Simulation time 45089847 ps
CPU time 1.82 seconds
Started Apr 15 12:32:34 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 197456 kb
Host smart-1deefaa4-26c7-402b-8c02-6199a7645db3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588131059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3588131059
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2134443172
Short name T339
Test name
Test status
Simulation time 49423001 ps
CPU time 0.9 seconds
Started Apr 15 12:32:58 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 194480 kb
Host smart-0a082ff7-72a1-4f75-b4fe-6bf04db13213
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134443172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2134443172
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.105575765
Short name T439
Test name
Test status
Simulation time 204957539 ps
CPU time 0.81 seconds
Started Apr 15 12:32:30 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 195500 kb
Host smart-9a0426c1-752a-4b9e-a32f-2049a69a3bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105575765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.105575765
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2090476221
Short name T691
Test name
Test status
Simulation time 186843284 ps
CPU time 1.06 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:53 PM PDT 24
Peak memory 195848 kb
Host smart-8cf7a4b0-3a4b-4831-af4f-64278ec9d6ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090476221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2090476221
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.316819165
Short name T502
Test name
Test status
Simulation time 322515668 ps
CPU time 3.27 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:32:58 PM PDT 24
Peak memory 197996 kb
Host smart-7fb50741-9b5d-434d-b1df-d26a5846014b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316819165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.316819165
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3158253422
Short name T629
Test name
Test status
Simulation time 201212048 ps
CPU time 0.91 seconds
Started Apr 15 12:32:29 PM PDT 24
Finished Apr 15 12:32:30 PM PDT 24
Peak memory 195500 kb
Host smart-3d9c7b7f-fe48-42cd-8a53-f074d9c7aed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158253422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3158253422
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2276177992
Short name T493
Test name
Test status
Simulation time 35530613 ps
CPU time 0.7 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 195356 kb
Host smart-26ea4776-d576-4115-90f2-6fac4c0ca171
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276177992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2276177992
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.991068288
Short name T154
Test name
Test status
Simulation time 6944387709 ps
CPU time 169.57 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:35:45 PM PDT 24
Peak memory 198132 kb
Host smart-5d971b02-bca9-48ac-87ec-e4374ee85155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991068288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.991068288
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2383928777
Short name T423
Test name
Test status
Simulation time 42113339 ps
CPU time 0.57 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 193928 kb
Host smart-ce9c8118-d029-4e77-9c16-31c7b2774ecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383928777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2383928777
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.505783660
Short name T341
Test name
Test status
Simulation time 79878863 ps
CPU time 0.87 seconds
Started Apr 15 12:32:35 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 196508 kb
Host smart-7bda482a-d9cd-4a79-a3f9-c0f6c09e1551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505783660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.505783660
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3947675343
Short name T316
Test name
Test status
Simulation time 484525074 ps
CPU time 6.28 seconds
Started Apr 15 12:32:58 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 196756 kb
Host smart-996cf8bd-0a8b-49c9-987d-c3c98584c990
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947675343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3947675343
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4051333087
Short name T396
Test name
Test status
Simulation time 55998654 ps
CPU time 0.96 seconds
Started Apr 15 12:32:32 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 196768 kb
Host smart-8641a15f-d8cd-4997-9435-6835ac3ba3db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051333087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4051333087
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1447336026
Short name T155
Test name
Test status
Simulation time 324019556 ps
CPU time 1.25 seconds
Started Apr 15 12:33:05 PM PDT 24
Finished Apr 15 12:33:07 PM PDT 24
Peak memory 196252 kb
Host smart-82f621a7-da38-413c-8b70-bd35dbf4040f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447336026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1447336026
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1380202480
Short name T398
Test name
Test status
Simulation time 40191621 ps
CPU time 1.64 seconds
Started Apr 15 12:32:34 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 196940 kb
Host smart-29a6eb4d-b459-4b2a-92db-e8c3ba061ca1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380202480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1380202480
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.538662679
Short name T457
Test name
Test status
Simulation time 180757123 ps
CPU time 2.91 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:55 PM PDT 24
Peak memory 197448 kb
Host smart-5d7e1544-9113-46c5-9670-c5f72c5359a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538662679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
538662679
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2197400693
Short name T15
Test name
Test status
Simulation time 202137965 ps
CPU time 1.19 seconds
Started Apr 15 12:32:32 PM PDT 24
Finished Apr 15 12:32:33 PM PDT 24
Peak memory 195936 kb
Host smart-40436d16-ee3e-4d95-9fe6-3516df4e413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197400693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2197400693
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.148873231
Short name T713
Test name
Test status
Simulation time 86546919 ps
CPU time 1.16 seconds
Started Apr 15 12:32:33 PM PDT 24
Finished Apr 15 12:32:35 PM PDT 24
Peak memory 197016 kb
Host smart-154f5d54-d802-49d4-a9e3-ec8739a07ab8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148873231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.148873231
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2485924572
Short name T462
Test name
Test status
Simulation time 101862020 ps
CPU time 4.28 seconds
Started Apr 15 12:32:57 PM PDT 24
Finished Apr 15 12:33:02 PM PDT 24
Peak memory 197992 kb
Host smart-cfed5bef-020d-4ea8-94a2-312ea211c030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485924572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2485924572
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4253587272
Short name T430
Test name
Test status
Simulation time 606734513 ps
CPU time 1.01 seconds
Started Apr 15 12:32:37 PM PDT 24
Finished Apr 15 12:32:38 PM PDT 24
Peak memory 196528 kb
Host smart-433df0e8-2d7a-464d-9c4c-ab66b895c1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253587272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4253587272
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.4155033248
Short name T704
Test name
Test status
Simulation time 24369250 ps
CPU time 0.77 seconds
Started Apr 15 12:32:55 PM PDT 24
Finished Apr 15 12:32:56 PM PDT 24
Peak memory 195276 kb
Host smart-160a306c-7a3c-4894-a6f7-a7a9b2e4a379
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155033248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.4155033248
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1024592894
Short name T564
Test name
Test status
Simulation time 7625974069 ps
CPU time 95.97 seconds
Started Apr 15 12:33:01 PM PDT 24
Finished Apr 15 12:34:38 PM PDT 24
Peak memory 198120 kb
Host smart-42661d46-b9c0-406d-9f3f-dcb761a13bff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024592894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1024592894
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1833165396
Short name T138
Test name
Test status
Simulation time 98139430 ps
CPU time 0.64 seconds
Started Apr 15 12:32:44 PM PDT 24
Finished Apr 15 12:32:45 PM PDT 24
Peak memory 194832 kb
Host smart-68d79990-e5e4-4d69-b3cb-edae7a69a9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833165396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1833165396
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2128769120
Short name T239
Test name
Test status
Simulation time 31384769 ps
CPU time 0.86 seconds
Started Apr 15 12:32:46 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 195908 kb
Host smart-a87742c5-2643-4c63-847b-317e82915d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128769120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2128769120
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1645187879
Short name T186
Test name
Test status
Simulation time 851777828 ps
CPU time 16.59 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 197028 kb
Host smart-42c0a51f-2498-4d08-8418-d8c62813ef60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645187879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1645187879
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4080300387
Short name T579
Test name
Test status
Simulation time 42652270 ps
CPU time 0.76 seconds
Started Apr 15 12:32:49 PM PDT 24
Finished Apr 15 12:32:50 PM PDT 24
Peak memory 195784 kb
Host smart-1eb1d0e2-cfe8-4b82-86da-ba3a750ed8bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080300387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4080300387
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1071449307
Short name T334
Test name
Test status
Simulation time 371417191 ps
CPU time 1.37 seconds
Started Apr 15 12:32:50 PM PDT 24
Finished Apr 15 12:32:51 PM PDT 24
Peak memory 196812 kb
Host smart-fbc6bd70-32f4-4568-8b3d-1f27276b6c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071449307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1071449307
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.188502791
Short name T710
Test name
Test status
Simulation time 116977126 ps
CPU time 2.33 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 196544 kb
Host smart-8f5bff93-829b-4b51-a876-11ecf6e5938a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188502791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.188502791
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1097613896
Short name T246
Test name
Test status
Simulation time 426189957 ps
CPU time 2.07 seconds
Started Apr 15 12:33:02 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 198092 kb
Host smart-99c5bd88-0b77-4463-98d9-ab843129e994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097613896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1097613896
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.997662429
Short name T641
Test name
Test status
Simulation time 43203126 ps
CPU time 0.82 seconds
Started Apr 15 12:32:30 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 195876 kb
Host smart-fd65affd-742f-4349-a7c6-a1da1ff616b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997662429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.997662429
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2936907408
Short name T636
Test name
Test status
Simulation time 51531477 ps
CPU time 1.1 seconds
Started Apr 15 12:32:34 PM PDT 24
Finished Apr 15 12:32:36 PM PDT 24
Peak memory 195912 kb
Host smart-e3591bac-cf22-4de4-92a3-b41deeadf03e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936907408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2936907408
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_smoke.182828897
Short name T290
Test name
Test status
Simulation time 311849837 ps
CPU time 1.36 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:06 PM PDT 24
Peak memory 196960 kb
Host smart-e57f2628-1740-4885-b520-87a3fd8e348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182828897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.182828897
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1975734613
Short name T661
Test name
Test status
Simulation time 188592521 ps
CPU time 1.19 seconds
Started Apr 15 12:33:03 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 196820 kb
Host smart-3eeea3de-b875-47cc-b9ee-2209f48e0827
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975734613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1975734613
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3930975285
Short name T78
Test name
Test status
Simulation time 24772306518 ps
CPU time 49.64 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:50 PM PDT 24
Peak memory 198188 kb
Host smart-d5dfaa85-f77b-4737-b3b6-3ac8a461846b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930975285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3930975285
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.507575401
Short name T609
Test name
Test status
Simulation time 14280204 ps
CPU time 0.53 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 193928 kb
Host smart-69c2f33b-fa28-4e1f-8a6c-ba45a2ca463d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507575401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.507575401
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2780918338
Short name T631
Test name
Test status
Simulation time 271380158 ps
CPU time 0.92 seconds
Started Apr 15 12:32:52 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 195996 kb
Host smart-d949fbd7-3f78-4e53-9a94-6b54608068dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780918338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2780918338
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2630724925
Short name T639
Test name
Test status
Simulation time 589332465 ps
CPU time 20.09 seconds
Started Apr 15 12:32:43 PM PDT 24
Finished Apr 15 12:33:04 PM PDT 24
Peak memory 196680 kb
Host smart-b9872589-0644-46f1-aa34-d0496e4553ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630724925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2630724925
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.365024982
Short name T288
Test name
Test status
Simulation time 532626147 ps
CPU time 0.94 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 196536 kb
Host smart-d61a75ce-bbbc-4d5a-9d3c-0cf5a96d0786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365024982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.365024982
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.535544561
Short name T455
Test name
Test status
Simulation time 319207874 ps
CPU time 1.37 seconds
Started Apr 15 12:32:57 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 197092 kb
Host smart-6c9d255e-8054-4e17-b3aa-3c20ba3a2e38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535544561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.535544561
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3220848829
Short name T662
Test name
Test status
Simulation time 396310133 ps
CPU time 2.39 seconds
Started Apr 15 12:32:52 PM PDT 24
Finished Apr 15 12:32:55 PM PDT 24
Peak memory 198200 kb
Host smart-186f2624-6528-46ce-b467-8d2bf7ebae8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220848829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3220848829
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2014582073
Short name T484
Test name
Test status
Simulation time 434764357 ps
CPU time 2.51 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 198076 kb
Host smart-3a8104e1-df4c-4b22-a992-18145ddc0c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014582073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2014582073
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.287189312
Short name T676
Test name
Test status
Simulation time 33447157 ps
CPU time 1.18 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 198196 kb
Host smart-889e2c2a-8b55-48da-b797-19e58b2493d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287189312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.287189312
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1924558894
Short name T411
Test name
Test status
Simulation time 47155718 ps
CPU time 1.01 seconds
Started Apr 15 12:32:51 PM PDT 24
Finished Apr 15 12:32:53 PM PDT 24
Peak memory 195872 kb
Host smart-121dbf95-81ff-4f92-b167-6ae281637d60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924558894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1924558894
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1787752126
Short name T460
Test name
Test status
Simulation time 1511728772 ps
CPU time 4.86 seconds
Started Apr 15 12:32:58 PM PDT 24
Finished Apr 15 12:33:04 PM PDT 24
Peak memory 198108 kb
Host smart-654b1593-6c97-49ba-b733-1fa64471545b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787752126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1787752126
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1207066692
Short name T323
Test name
Test status
Simulation time 72176363 ps
CPU time 0.88 seconds
Started Apr 15 12:32:41 PM PDT 24
Finished Apr 15 12:32:42 PM PDT 24
Peak memory 195744 kb
Host smart-c1dd70bf-745a-43db-a628-13a6340bb3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207066692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1207066692
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2815709726
Short name T426
Test name
Test status
Simulation time 27780126 ps
CPU time 0.73 seconds
Started Apr 15 12:32:57 PM PDT 24
Finished Apr 15 12:32:58 PM PDT 24
Peak memory 195884 kb
Host smart-1ce4071f-3b05-46d1-bbe3-aed76d5c77ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815709726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2815709726
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3739583202
Short name T231
Test name
Test status
Simulation time 4643936290 ps
CPU time 104.96 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 198316 kb
Host smart-ff28e798-638c-4f5a-87b0-fd3f365b432a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739583202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3739583202
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2129404271
Short name T410
Test name
Test status
Simulation time 59756784 ps
CPU time 0.55 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 193928 kb
Host smart-0a0ce433-d19e-4406-960d-dd9d89897936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129404271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2129404271
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3506577450
Short name T370
Test name
Test status
Simulation time 21082306 ps
CPU time 0.63 seconds
Started Apr 15 12:32:59 PM PDT 24
Finished Apr 15 12:33:00 PM PDT 24
Peak memory 194076 kb
Host smart-68bb8782-7603-4859-a1cf-5d43bb65dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506577450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3506577450
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3439814123
Short name T378
Test name
Test status
Simulation time 99814595 ps
CPU time 4.87 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 197124 kb
Host smart-e57b5919-81b3-4118-ae22-bbdd99f523fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439814123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3439814123
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.866956300
Short name T707
Test name
Test status
Simulation time 63734183 ps
CPU time 0.73 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:32:58 PM PDT 24
Peak memory 194784 kb
Host smart-c48eeffc-58ad-4001-a7fa-b77f17e07559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866956300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.866956300
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.125306870
Short name T497
Test name
Test status
Simulation time 48650586 ps
CPU time 1.25 seconds
Started Apr 15 12:32:57 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 197044 kb
Host smart-ab66385a-eaa2-4a3b-9275-ef37990128a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125306870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.125306870
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3649254247
Short name T520
Test name
Test status
Simulation time 190141074 ps
CPU time 3.87 seconds
Started Apr 15 12:32:56 PM PDT 24
Finished Apr 15 12:33:00 PM PDT 24
Peak memory 198160 kb
Host smart-c9bd56b0-43e8-4738-90f4-1c168447d3b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649254247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3649254247
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.295852199
Short name T705
Test name
Test status
Simulation time 105720954 ps
CPU time 2.34 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 197168 kb
Host smart-3ebea56d-3d75-4259-98bf-63e653a12f30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295852199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
295852199
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1149384804
Short name T675
Test name
Test status
Simulation time 28255910 ps
CPU time 1.01 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 196056 kb
Host smart-4291b015-2f6b-405d-a1ac-0118b5619922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149384804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1149384804
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.328841411
Short name T160
Test name
Test status
Simulation time 20379646 ps
CPU time 0.67 seconds
Started Apr 15 12:32:46 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 195120 kb
Host smart-6ccadd6b-5bf0-433f-9f56-1f366ced7970
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328841411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.328841411
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3315302273
Short name T706
Test name
Test status
Simulation time 407329682 ps
CPU time 3.09 seconds
Started Apr 15 12:32:59 PM PDT 24
Finished Apr 15 12:33:02 PM PDT 24
Peak memory 198004 kb
Host smart-5f0c624c-db06-4a67-8875-c0cc09b95327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315302273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3315302273
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2440829375
Short name T384
Test name
Test status
Simulation time 550387693 ps
CPU time 0.87 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:06 PM PDT 24
Peak memory 195448 kb
Host smart-73ab516d-8232-4bc7-897f-5ac2ac7c492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440829375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2440829375
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2241163137
Short name T173
Test name
Test status
Simulation time 194169168 ps
CPU time 1.09 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196464 kb
Host smart-b2426689-c925-4560-8c24-7a0b92c3a1e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241163137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2241163137
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2435604678
Short name T622
Test name
Test status
Simulation time 3689846622 ps
CPU time 47.08 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:51 PM PDT 24
Peak memory 198224 kb
Host smart-28c2fca0-b77d-46d8-a9dc-ac9ae5924675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435604678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2435604678
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.929098134
Short name T653
Test name
Test status
Simulation time 40752000514 ps
CPU time 543.12 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:42:17 PM PDT 24
Peak memory 198324 kb
Host smart-72a94a11-5620-4dd8-bebe-4f17d35784b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=929098134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.929098134
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2118650054
Short name T414
Test name
Test status
Simulation time 35777899 ps
CPU time 0.61 seconds
Started Apr 15 12:32:47 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 193992 kb
Host smart-c9756a2b-c4b9-4588-bb8d-c18a49d180eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118650054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2118650054
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2990055969
Short name T187
Test name
Test status
Simulation time 35515587 ps
CPU time 0.82 seconds
Started Apr 15 12:32:44 PM PDT 24
Finished Apr 15 12:32:45 PM PDT 24
Peak memory 195984 kb
Host smart-d26540e0-83b8-493c-a208-9ced1e94fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990055969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2990055969
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3560615220
Short name T565
Test name
Test status
Simulation time 720744241 ps
CPU time 24.2 seconds
Started Apr 15 12:32:55 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 196984 kb
Host smart-438c4885-7786-4127-93e6-dcbfc00b0acb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560615220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3560615220
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2874146225
Short name T554
Test name
Test status
Simulation time 24511848 ps
CPU time 0.64 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 194636 kb
Host smart-42a58417-74fb-4f37-a4b2-692171434239
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874146225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2874146225
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2253780733
Short name T488
Test name
Test status
Simulation time 96219195 ps
CPU time 0.83 seconds
Started Apr 15 12:33:05 PM PDT 24
Finished Apr 15 12:33:07 PM PDT 24
Peak memory 196800 kb
Host smart-e951643e-a34f-4e29-847b-7b3d88f0a4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253780733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2253780733
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.398446847
Short name T144
Test name
Test status
Simulation time 31503710 ps
CPU time 1.31 seconds
Started Apr 15 12:32:44 PM PDT 24
Finished Apr 15 12:32:46 PM PDT 24
Peak memory 196920 kb
Host smart-fdca5bfa-0dbf-4735-b922-89567980d4dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398446847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.398446847
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3108210171
Short name T258
Test name
Test status
Simulation time 102099287 ps
CPU time 2.16 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 197328 kb
Host smart-c1976102-b96f-49cf-a453-ffb5dd92c913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108210171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3108210171
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3275160855
Short name T261
Test name
Test status
Simulation time 94389422 ps
CPU time 0.94 seconds
Started Apr 15 12:32:49 PM PDT 24
Finished Apr 15 12:32:51 PM PDT 24
Peak memory 196076 kb
Host smart-bee68477-5953-405d-af22-c7e2f03dd5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275160855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3275160855
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.587419174
Short name T392
Test name
Test status
Simulation time 92354063 ps
CPU time 0.87 seconds
Started Apr 15 12:32:59 PM PDT 24
Finished Apr 15 12:33:00 PM PDT 24
Peak memory 196104 kb
Host smart-33af64c1-1589-4cd0-824d-0040dd2285c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587419174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.587419174
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3136874482
Short name T587
Test name
Test status
Simulation time 1221688899 ps
CPU time 5.38 seconds
Started Apr 15 12:32:53 PM PDT 24
Finished Apr 15 12:33:04 PM PDT 24
Peak memory 198052 kb
Host smart-5e4f5553-6771-4449-93f7-64967f79683f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136874482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3136874482
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2907589671
Short name T522
Test name
Test status
Simulation time 119527493 ps
CPU time 0.75 seconds
Started Apr 15 12:32:50 PM PDT 24
Finished Apr 15 12:32:52 PM PDT 24
Peak memory 195220 kb
Host smart-4632a3b0-e034-441b-9f35-afe48821d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907589671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2907589671
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3245777188
Short name T548
Test name
Test status
Simulation time 41337272 ps
CPU time 0.83 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 196124 kb
Host smart-fa7c9229-7489-4509-b52f-3dc45250d90e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245777188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3245777188
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3643577219
Short name T251
Test name
Test status
Simulation time 5447982562 ps
CPU time 27.54 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:42 PM PDT 24
Peak memory 198300 kb
Host smart-c3bf515a-4677-4e38-a399-43d82eac688a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643577219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3643577219
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2466364944
Short name T501
Test name
Test status
Simulation time 37490644 ps
CPU time 0.55 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 194612 kb
Host smart-42d8659c-33b8-495f-b32a-b9f0a3ee8083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466364944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2466364944
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1910867630
Short name T431
Test name
Test status
Simulation time 78536976 ps
CPU time 0.95 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:09 PM PDT 24
Peak memory 196296 kb
Host smart-f6f91bde-be8f-4b7d-8948-3247d1ba3560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910867630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1910867630
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3777001969
Short name T351
Test name
Test status
Simulation time 279892170 ps
CPU time 6.79 seconds
Started Apr 15 12:33:05 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 196768 kb
Host smart-6dc7d412-80fa-4d78-a924-55574c7f3302
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777001969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3777001969
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3088743105
Short name T659
Test name
Test status
Simulation time 44993879 ps
CPU time 0.85 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:32:56 PM PDT 24
Peak memory 196112 kb
Host smart-702b0660-6bbd-496d-8b7c-0b9bb2222e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088743105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3088743105
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1466523065
Short name T59
Test name
Test status
Simulation time 1017238761 ps
CPU time 1.39 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196616 kb
Host smart-d09002fb-d03f-4cda-97c6-0b9c4e7cf122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466523065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1466523065
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3934219134
Short name T174
Test name
Test status
Simulation time 22819049 ps
CPU time 1.03 seconds
Started Apr 15 12:32:54 PM PDT 24
Finished Apr 15 12:32:56 PM PDT 24
Peak memory 196012 kb
Host smart-cf13f378-e12f-42a7-8e71-1f4eabe282b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934219134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3934219134
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3645791206
Short name T368
Test name
Test status
Simulation time 309313999 ps
CPU time 2.87 seconds
Started Apr 15 12:32:59 PM PDT 24
Finished Apr 15 12:33:02 PM PDT 24
Peak memory 197364 kb
Host smart-31641a95-b9f2-45ef-8b62-5ec550defde2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645791206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3645791206
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3184182288
Short name T250
Test name
Test status
Simulation time 25011243 ps
CPU time 0.88 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:33:08 PM PDT 24
Peak memory 195904 kb
Host smart-4618159b-2bbd-4f2a-8870-0294a5fb1530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184182288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3184182288
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3490121618
Short name T440
Test name
Test status
Simulation time 331158603 ps
CPU time 1.2 seconds
Started Apr 15 12:32:58 PM PDT 24
Finished Apr 15 12:33:00 PM PDT 24
Peak memory 196888 kb
Host smart-96afafae-a3fd-4a9c-8251-c49f812124c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490121618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3490121618
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2874922166
Short name T74
Test name
Test status
Simulation time 509462665 ps
CPU time 5.21 seconds
Started Apr 15 12:33:01 PM PDT 24
Finished Apr 15 12:33:07 PM PDT 24
Peak memory 198068 kb
Host smart-5cccf92f-39ef-4ada-959a-d12192302ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874922166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2874922166
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.868007654
Short name T452
Test name
Test status
Simulation time 297435139 ps
CPU time 1.13 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195712 kb
Host smart-044a63a5-f178-479c-b467-3e3d8fe20ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868007654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.868007654
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4239945066
Short name T60
Test name
Test status
Simulation time 288089267 ps
CPU time 1.1 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:33:08 PM PDT 24
Peak memory 195720 kb
Host smart-318781cd-5955-4545-9847-ebf52ec9700f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239945066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4239945066
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2000922635
Short name T598
Test name
Test status
Simulation time 17807410923 ps
CPU time 18.01 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:36 PM PDT 24
Peak memory 198344 kb
Host smart-e7dd8e4c-5bd7-400f-9405-79246f06ff39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000922635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2000922635
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2212318064
Short name T383
Test name
Test status
Simulation time 14505211 ps
CPU time 0.57 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:06 PM PDT 24
Peak memory 194220 kb
Host smart-173aeac3-c24c-4e56-a0bf-20b12e09c864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212318064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2212318064
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2678899485
Short name T147
Test name
Test status
Simulation time 35195381 ps
CPU time 0.58 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 193988 kb
Host smart-c9f3eaa4-b2dc-4389-b20f-b9e2de7e59bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678899485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2678899485
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2306271308
Short name T444
Test name
Test status
Simulation time 3343156938 ps
CPU time 24.2 seconds
Started Apr 15 12:32:59 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 197048 kb
Host smart-a90dc32a-9ff8-4437-89c7-543bf5078394
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306271308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2306271308
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.4003164700
Short name T241
Test name
Test status
Simulation time 519081516 ps
CPU time 0.96 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:06 PM PDT 24
Peak memory 197888 kb
Host smart-1fc9eda8-c5b8-48b5-8d3b-87c75f18739e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003164700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.4003164700
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2793790736
Short name T555
Test name
Test status
Simulation time 32635425 ps
CPU time 0.99 seconds
Started Apr 15 12:33:03 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 196204 kb
Host smart-71750f12-4a03-4d58-b7fc-0e4c83a601a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793790736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2793790736
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3275387222
Short name T673
Test name
Test status
Simulation time 456287236 ps
CPU time 3.21 seconds
Started Apr 15 12:32:49 PM PDT 24
Finished Apr 15 12:32:53 PM PDT 24
Peak memory 196408 kb
Host smart-e6bc76d4-0561-4c65-ab25-e519d91a8e8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275387222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3275387222
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2285682769
Short name T267
Test name
Test status
Simulation time 69099635 ps
CPU time 2 seconds
Started Apr 15 12:33:07 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 197020 kb
Host smart-b9879826-9ec3-472b-99fc-93f9bc9354da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285682769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2285682769
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.146940863
Short name T541
Test name
Test status
Simulation time 26989375 ps
CPU time 1.05 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:02 PM PDT 24
Peak memory 196768 kb
Host smart-3b2f4903-0fa2-45a0-a338-1650516b6c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146940863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.146940863
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.4203338790
Short name T454
Test name
Test status
Simulation time 26105374 ps
CPU time 0.93 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:01 PM PDT 24
Peak memory 196844 kb
Host smart-3100b571-dd33-43f3-afce-49d9682f259b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203338790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.4203338790
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1715265270
Short name T604
Test name
Test status
Simulation time 215966645 ps
CPU time 2.1 seconds
Started Apr 15 12:33:00 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 198036 kb
Host smart-4468ba91-ddbc-4d03-8146-bcffaeb30200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715265270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1715265270
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3789849562
Short name T606
Test name
Test status
Simulation time 133366552 ps
CPU time 1.13 seconds
Started Apr 15 12:33:01 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 196824 kb
Host smart-29dc55fd-e61e-4808-bdb5-242ede4ffddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789849562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3789849562
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3397592650
Short name T123
Test name
Test status
Simulation time 613207604 ps
CPU time 0.95 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:33:05 PM PDT 24
Peak memory 196556 kb
Host smart-27d2e43c-0bd7-4383-99a7-b78ca660ffab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397592650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3397592650
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3061248998
Short name T415
Test name
Test status
Simulation time 52116779866 ps
CPU time 177.93 seconds
Started Apr 15 12:33:02 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 198180 kb
Host smart-8be61f1f-ac8b-45c9-aa09-b7c93fc255d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061248998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3061248998
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2304535885
Short name T282
Test name
Test status
Simulation time 14299994 ps
CPU time 0.6 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 193924 kb
Host smart-c1d9048e-cfc5-4d47-af9c-64f301f1c1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304535885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2304535885
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2872289817
Short name T413
Test name
Test status
Simulation time 210910752 ps
CPU time 0.79 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195472 kb
Host smart-cd2e4664-d456-4dac-ac68-f2fe0158f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872289817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2872289817
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.935442943
Short name T503
Test name
Test status
Simulation time 373179370 ps
CPU time 10.39 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196900 kb
Host smart-466b01bf-94ae-4051-9329-4db6ef439dd5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935442943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.935442943
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2945092109
Short name T613
Test name
Test status
Simulation time 520416868 ps
CPU time 0.8 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 196016 kb
Host smart-27bbe349-7858-48a4-9e4d-0bd92580aec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945092109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2945092109
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.780138273
Short name T695
Test name
Test status
Simulation time 65344613 ps
CPU time 0.65 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 194320 kb
Host smart-9e90b679-7c20-48ac-9eed-77a26bb2b820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780138273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.780138273
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3960958342
Short name T451
Test name
Test status
Simulation time 190241885 ps
CPU time 3.49 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 198204 kb
Host smart-c3a500e9-29a8-430a-88bf-9e05eb7c0eec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960958342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3960958342
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3841905830
Short name T644
Test name
Test status
Simulation time 664356470 ps
CPU time 2.82 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 198204 kb
Host smart-9d69d292-611e-4a17-b1e3-dd0a5a8645e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841905830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3841905830
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2931705206
Short name T359
Test name
Test status
Simulation time 103615242 ps
CPU time 1.16 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196932 kb
Host smart-9f3de58c-7249-4efd-bcbd-f5dc49e9464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931705206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2931705206
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.845198469
Short name T168
Test name
Test status
Simulation time 34695640 ps
CPU time 0.67 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:09 PM PDT 24
Peak memory 194612 kb
Host smart-c54a212e-b3f9-490b-99b9-0aa7c675ecf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845198469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.845198469
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.983647058
Short name T218
Test name
Test status
Simulation time 262688341 ps
CPU time 2.7 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 198020 kb
Host smart-ddb9a69a-2d40-4ede-afa1-b24906e0f135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983647058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.983647058
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2949140911
Short name T602
Test name
Test status
Simulation time 119436352 ps
CPU time 1.08 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 195592 kb
Host smart-bf64c944-1fbb-4702-922c-d4c71b2de69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949140911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2949140911
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3383519089
Short name T467
Test name
Test status
Simulation time 127281299 ps
CPU time 0.84 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 195344 kb
Host smart-09228fb8-9957-45cf-ba0c-387b0d7a9513
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383519089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3383519089
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.201434274
Short name T566
Test name
Test status
Simulation time 18615395647 ps
CPU time 195.94 seconds
Started Apr 15 12:33:04 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 198208 kb
Host smart-4dd38ace-b3b2-495b-8c1d-de4ee7b5b244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201434274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.201434274
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.374954393
Short name T403
Test name
Test status
Simulation time 143638358576 ps
CPU time 890.68 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:48:04 PM PDT 24
Peak memory 198356 kb
Host smart-6431dc38-50b5-49ea-b1aa-3b5179c9a6c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=374954393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.374954393
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.282204758
Short name T299
Test name
Test status
Simulation time 31026480 ps
CPU time 0.59 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195516 kb
Host smart-810f9789-be05-4054-a171-cc5f3d710a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282204758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.282204758
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.133799419
Short name T496
Test name
Test status
Simulation time 30585295 ps
CPU time 0.71 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 194324 kb
Host smart-d32c74cb-16ae-4633-8d2c-28b306ceb859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133799419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.133799419
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3823006187
Short name T665
Test name
Test status
Simulation time 2321169441 ps
CPU time 22 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:35 PM PDT 24
Peak memory 197984 kb
Host smart-ef62a792-5d4a-46ad-92af-de5cf975717b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823006187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3823006187
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1955598028
Short name T230
Test name
Test status
Simulation time 42150486 ps
CPU time 0.75 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 194908 kb
Host smart-1b6f2164-172a-4ec4-af1e-108675c82f8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955598028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1955598028
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1172348087
Short name T263
Test name
Test status
Simulation time 122682080 ps
CPU time 0.68 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 195396 kb
Host smart-10eec088-a6fd-4c77-bb5f-f67172306fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172348087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1172348087
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2954456499
Short name T510
Test name
Test status
Simulation time 98185092 ps
CPU time 3.6 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 198140 kb
Host smart-fb235a91-40dd-4b74-a484-53109f19144e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954456499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2954456499
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1084647409
Short name T435
Test name
Test status
Simulation time 1543741925 ps
CPU time 3.32 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:33:09 PM PDT 24
Peak memory 196564 kb
Host smart-6c9a26b2-30a2-47e6-bd9d-e5d757c945df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084647409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1084647409
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3198739963
Short name T280
Test name
Test status
Simulation time 124265394 ps
CPU time 0.79 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196312 kb
Host smart-618e8d00-4b5f-4904-9980-01be17230c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198739963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3198739963
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1980678839
Short name T445
Test name
Test status
Simulation time 45965675 ps
CPU time 1.08 seconds
Started Apr 15 12:33:02 PM PDT 24
Finished Apr 15 12:33:04 PM PDT 24
Peak memory 196668 kb
Host smart-247be71e-58cb-4990-a909-dfb368f1fd63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980678839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1980678839
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3291695587
Short name T262
Test name
Test status
Simulation time 410673782 ps
CPU time 5.54 seconds
Started Apr 15 12:33:06 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 198104 kb
Host smart-dc7f5bdf-35d9-4007-962c-8cb6824457bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291695587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3291695587
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4272227162
Short name T57
Test name
Test status
Simulation time 41297140 ps
CPU time 1.08 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 195632 kb
Host smart-3f18cb3e-281e-422b-a006-eb00ae11bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272227162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4272227162
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4258188521
Short name T669
Test name
Test status
Simulation time 59110871 ps
CPU time 0.93 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196516 kb
Host smart-25605801-d0de-40bd-b506-df0f54257acb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258188521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4258188521
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3038525610
Short name T643
Test name
Test status
Simulation time 13456786858 ps
CPU time 144.45 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:35:39 PM PDT 24
Peak memory 198048 kb
Host smart-fdbaf667-2420-456d-8479-c2d418b3e60c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038525610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3038525610
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.226222675
Short name T274
Test name
Test status
Simulation time 223253099 ps
CPU time 0.59 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 194896 kb
Host smart-90b1a5a1-135e-4fd2-934c-de94929cf899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226222675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.226222675
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1915592259
Short name T690
Test name
Test status
Simulation time 85213194 ps
CPU time 0.82 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196164 kb
Host smart-a9c30560-a8e2-40dd-84c4-4b9b512be24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915592259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1915592259
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.909093848
Short name T124
Test name
Test status
Simulation time 3314283874 ps
CPU time 27.11 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:49 PM PDT 24
Peak memory 197180 kb
Host smart-84b77d05-e528-43f7-81f0-518ae1bbc19b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909093848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.909093848
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1602039655
Short name T195
Test name
Test status
Simulation time 261166876 ps
CPU time 0.92 seconds
Started Apr 15 12:32:09 PM PDT 24
Finished Apr 15 12:32:10 PM PDT 24
Peak memory 197708 kb
Host smart-af4a7092-6f4e-46cb-aa0c-b4af633957ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602039655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1602039655
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.910359965
Short name T667
Test name
Test status
Simulation time 48257240 ps
CPU time 1.25 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 197544 kb
Host smart-d4b83720-7fc6-45ec-ba30-1a8bb17a43e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910359965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.910359965
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2766066690
Short name T699
Test name
Test status
Simulation time 43224061 ps
CPU time 0.98 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 196440 kb
Host smart-befaeafa-2f88-4af2-bd22-293e71337857
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766066690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2766066690
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2490235236
Short name T373
Test name
Test status
Simulation time 171238525 ps
CPU time 2.39 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 197280 kb
Host smart-1a04605e-3a7e-4cbd-a781-61dab03c4e05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490235236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2490235236
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3116399833
Short name T244
Test name
Test status
Simulation time 89217116 ps
CPU time 0.92 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195840 kb
Host smart-13be7703-e8a1-495a-99ff-d3257f15caab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116399833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3116399833
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2682704888
Short name T209
Test name
Test status
Simulation time 211229660 ps
CPU time 1.25 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 198164 kb
Host smart-8f3b3bca-d65d-4240-93bd-52615d0673d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682704888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2682704888
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4027507258
Short name T535
Test name
Test status
Simulation time 52411646 ps
CPU time 1.83 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 198108 kb
Host smart-ec13385c-db9a-4aa3-9fa0-13f1da5b5ebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027507258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4027507258
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1673118092
Short name T44
Test name
Test status
Simulation time 131769908 ps
CPU time 0.85 seconds
Started Apr 15 12:32:11 PM PDT 24
Finished Apr 15 12:32:13 PM PDT 24
Peak memory 213584 kb
Host smart-197d3148-95ac-46f1-996c-7da2a8493c2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673118092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1673118092
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1951760101
Short name T422
Test name
Test status
Simulation time 88151495 ps
CPU time 0.92 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196356 kb
Host smart-39a3edf2-d218-4006-b389-d5e42a790715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951760101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1951760101
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.589816804
Short name T433
Test name
Test status
Simulation time 105944254 ps
CPU time 0.87 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196288 kb
Host smart-4627409b-ed56-49cd-800c-ee2749a4c401
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589816804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.589816804
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.47533613
Short name T584
Test name
Test status
Simulation time 287485358689 ps
CPU time 1712.67 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 01:00:49 PM PDT 24
Peak memory 198352 kb
Host smart-b8810ac0-155c-4d4e-8954-4e6e5254d345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=47533613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.47533613
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4247908749
Short name T33
Test name
Test status
Simulation time 33540681 ps
CPU time 0.59 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 194624 kb
Host smart-17c8bb0c-60e4-43c8-a8fb-ea67026825a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247908749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4247908749
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1825919283
Short name T219
Test name
Test status
Simulation time 23060131 ps
CPU time 0.68 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 194156 kb
Host smart-c51f6e22-84d0-4840-bb8e-4dd86cac88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825919283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1825919283
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1201203230
Short name T358
Test name
Test status
Simulation time 318188351 ps
CPU time 6.07 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 195576 kb
Host smart-5ccb0324-35d0-47ae-96a4-2b66defa2942
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201203230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1201203230
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2877107011
Short name T248
Test name
Test status
Simulation time 42552852 ps
CPU time 0.73 seconds
Started Apr 15 12:33:02 PM PDT 24
Finished Apr 15 12:33:03 PM PDT 24
Peak memory 195792 kb
Host smart-ba451390-769d-4f2c-aa17-4c2496bd854b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877107011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2877107011
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1664181064
Short name T343
Test name
Test status
Simulation time 79047176 ps
CPU time 1.45 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196764 kb
Host smart-e701ae0a-d26b-42cc-8224-8eb54bf9665b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664181064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1664181064
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.285853739
Short name T29
Test name
Test status
Simulation time 26639004 ps
CPU time 1.1 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 197476 kb
Host smart-9433809c-5e26-436c-9ec6-5da1719d92b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285853739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.285853739
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.466688036
Short name T614
Test name
Test status
Simulation time 156385625 ps
CPU time 3.18 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 195872 kb
Host smart-3a336054-c7ca-4166-b4e7-d014d81ecfb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466688036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
466688036
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3788580721
Short name T382
Test name
Test status
Simulation time 24632842 ps
CPU time 0.89 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195872 kb
Host smart-025b6656-0bb1-47f2-a0d3-a8ac86bb9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788580721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3788580721
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.580925236
Short name T137
Test name
Test status
Simulation time 67366602 ps
CPU time 1.2 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 197192 kb
Host smart-915eeb0c-f69c-42c9-a6af-37a5806d4b3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580925236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.580925236
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1768173911
Short name T582
Test name
Test status
Simulation time 26327720 ps
CPU time 1.14 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 197912 kb
Host smart-777f871f-8c72-42fb-bc28-205d08b66039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768173911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1768173911
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2224899332
Short name T207
Test name
Test status
Simulation time 217484794 ps
CPU time 1.01 seconds
Started Apr 15 12:33:07 PM PDT 24
Finished Apr 15 12:33:08 PM PDT 24
Peak memory 195952 kb
Host smart-92eeceb1-1bf3-44db-92f2-ae9f3f43fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224899332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2224899332
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1471570133
Short name T213
Test name
Test status
Simulation time 76196101 ps
CPU time 1.19 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195748 kb
Host smart-601e6ae3-6d79-4c83-abf4-28b788850055
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471570133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1471570133
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.991935481
Short name T3
Test name
Test status
Simulation time 28527582427 ps
CPU time 75.55 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:34:29 PM PDT 24
Peak memory 198112 kb
Host smart-0389cdb3-2a22-4972-9d8b-0b760fd7199b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991935481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.991935481
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2757931331
Short name T127
Test name
Test status
Simulation time 42410496 ps
CPU time 0.62 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 194692 kb
Host smart-4d88ff9b-956a-473e-a71d-791807f5800a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757931331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2757931331
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1489593463
Short name T483
Test name
Test status
Simulation time 18150129 ps
CPU time 0.64 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 194840 kb
Host smart-d7f834af-d87f-4afa-aa31-ffff135cc7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489593463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1489593463
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2425472708
Short name T306
Test name
Test status
Simulation time 1646400083 ps
CPU time 28.04 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:40 PM PDT 24
Peak memory 196312 kb
Host smart-76d93a96-faef-4873-9e98-886da7fea02b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425472708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2425472708
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1440428375
Short name T668
Test name
Test status
Simulation time 170289358 ps
CPU time 1.01 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 196680 kb
Host smart-08ca1074-ccd4-4516-9f0d-88749de66ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440428375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1440428375
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.152326310
Short name T268
Test name
Test status
Simulation time 72086237 ps
CPU time 0.79 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 196420 kb
Host smart-2e5bf284-8963-44cd-87fe-9d5a54417a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152326310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.152326310
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.647472102
Short name T538
Test name
Test status
Simulation time 171984989 ps
CPU time 1.82 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 196580 kb
Host smart-f73c26bc-0adb-4e02-aad9-c8b09e44d564
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647472102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.647472102
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1642416872
Short name T523
Test name
Test status
Simulation time 52157972 ps
CPU time 1.17 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 195604 kb
Host smart-a6531ac3-df8d-4f3e-8bf7-f230846ef0eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642416872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1642416872
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3532383102
Short name T79
Test name
Test status
Simulation time 46942377 ps
CPU time 1.19 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 196320 kb
Host smart-69b19d2b-7835-4450-912c-e3efbe9ad295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532383102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3532383102
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2035264
Short name T630
Test name
Test status
Simulation time 32047145 ps
CPU time 0.72 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195564 kb
Host smart-127b5847-6cef-4981-8c20-d1bad5d64f21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup_p
ulldown.2035264
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1420058924
Short name T405
Test name
Test status
Simulation time 4165831974 ps
CPU time 5.62 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 198168 kb
Host smart-fe0f3998-15db-4f9a-85bf-fbcdee17ff63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420058924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1420058924
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1675219738
Short name T511
Test name
Test status
Simulation time 116923390 ps
CPU time 1.32 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 197292 kb
Host smart-429f5192-5bd3-4174-8227-a23dac817572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675219738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1675219738
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2901329577
Short name T490
Test name
Test status
Simulation time 32123901 ps
CPU time 0.99 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 195556 kb
Host smart-d3f46363-82b0-4a21-8f58-5642e69a09cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901329577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2901329577
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.726422577
Short name T379
Test name
Test status
Simulation time 13756390269 ps
CPU time 185.13 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:36:24 PM PDT 24
Peak memory 198224 kb
Host smart-92439f97-507a-472e-ad56-017d9cfad2b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726422577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.726422577
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3080020218
Short name T70
Test name
Test status
Simulation time 208438712832 ps
CPU time 1120.49 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:51:57 PM PDT 24
Peak memory 198300 kb
Host smart-a6c13616-b01d-4d10-8a22-6d5ee5bacae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3080020218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3080020218
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3471258087
Short name T171
Test name
Test status
Simulation time 11083548 ps
CPU time 0.56 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 194032 kb
Host smart-bf242673-3c33-4541-bafa-9484e2587d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471258087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3471258087
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1621083847
Short name T703
Test name
Test status
Simulation time 111092126 ps
CPU time 0.88 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 195644 kb
Host smart-501ae11f-a4ed-4068-bad3-11fd64c387d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621083847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1621083847
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1538270675
Short name T495
Test name
Test status
Simulation time 508406279 ps
CPU time 13.1 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:33 PM PDT 24
Peak memory 198040 kb
Host smart-8771016d-cc02-4123-a782-711cb40f5562
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538270675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1538270675
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3217762828
Short name T198
Test name
Test status
Simulation time 1904820987 ps
CPU time 1.13 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196416 kb
Host smart-13f997ea-70d3-4d3a-8456-d6b9bc11757d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217762828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3217762828
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1061190065
Short name T291
Test name
Test status
Simulation time 24177398 ps
CPU time 0.71 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 194340 kb
Host smart-a72cc6e6-7408-41eb-a42d-5e68605d01b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061190065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1061190065
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.203566683
Short name T157
Test name
Test status
Simulation time 791294236 ps
CPU time 2.9 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 198132 kb
Host smart-e61d3e71-fb92-4703-b7ee-a96fdbed3974
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203566683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.203566683
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2274586521
Short name T487
Test name
Test status
Simulation time 600989670 ps
CPU time 2.99 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 197344 kb
Host smart-8a0afeb8-7f44-408e-875c-e57faf40c12b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274586521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2274586521
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3129599714
Short name T438
Test name
Test status
Simulation time 37303825 ps
CPU time 0.9 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 196712 kb
Host smart-043b2b0f-3fc8-47e0-b044-95a8a73c908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129599714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3129599714
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2268466707
Short name T419
Test name
Test status
Simulation time 28303500 ps
CPU time 1.1 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 196064 kb
Host smart-e32942da-ec58-4d0c-9638-bdf12b62ecd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268466707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2268466707
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3420827253
Short name T621
Test name
Test status
Simulation time 367648676 ps
CPU time 2.98 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 197996 kb
Host smart-26dba9a2-45cd-4abb-ae90-f918b2acab7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420827253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3420827253
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1472909463
Short name T315
Test name
Test status
Simulation time 376253575 ps
CPU time 1.39 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196640 kb
Host smart-014bb078-e5a1-4153-987c-276287022e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472909463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1472909463
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2777104188
Short name T151
Test name
Test status
Simulation time 1359405546 ps
CPU time 1.5 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 196832 kb
Host smart-b302b069-dd93-41a7-b647-99d893cfa7a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777104188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2777104188
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2533682956
Short name T281
Test name
Test status
Simulation time 183093162381 ps
CPU time 188.16 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:36:22 PM PDT 24
Peak memory 198132 kb
Host smart-dc679ef3-a0ce-4feb-87b7-c9580e37cbf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533682956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2533682956
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4671301
Short name T477
Test name
Test status
Simulation time 14189831 ps
CPU time 0.56 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 194596 kb
Host smart-887a7946-6531-477e-a747-267c63e96d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4671301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4671301
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3546634580
Short name T190
Test name
Test status
Simulation time 79391517 ps
CPU time 0.77 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195536 kb
Host smart-48e21d3d-732c-45a8-a6bd-a4cf24795cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546634580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3546634580
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3877099295
Short name T465
Test name
Test status
Simulation time 1647466731 ps
CPU time 13.57 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:35 PM PDT 24
Peak memory 196720 kb
Host smart-5a563bec-9253-4989-8f4d-a92160628e39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877099295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3877099295
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2575124606
Short name T20
Test name
Test status
Simulation time 74053594 ps
CPU time 0.9 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 197748 kb
Host smart-fbaba7a8-c56d-482b-9b96-2a12cd06d743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575124606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2575124606
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3203674242
Short name T701
Test name
Test status
Simulation time 79165891 ps
CPU time 0.86 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 195608 kb
Host smart-e662ceb9-ace1-479f-b7f5-662fcbf78f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203674242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3203674242
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.4261587620
Short name T182
Test name
Test status
Simulation time 70152906 ps
CPU time 1.67 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 196412 kb
Host smart-f156f14a-a3ff-4e36-a870-7d73f2a309b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261587620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.4261587620
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2485775471
Short name T349
Test name
Test status
Simulation time 511573993 ps
CPU time 2.52 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195628 kb
Host smart-b98039aa-956e-4e95-953a-154020865e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485775471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2485775471
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.816776140
Short name T260
Test name
Test status
Simulation time 36012002 ps
CPU time 1.22 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 196948 kb
Host smart-f924f248-f5d2-473e-b616-1a7924079544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816776140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.816776140
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.851831786
Short name T366
Test name
Test status
Simulation time 131741365 ps
CPU time 1.24 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 197220 kb
Host smart-951060fe-2644-4f7d-bc39-f5201fe6433a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851831786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.851831786
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3554251213
Short name T371
Test name
Test status
Simulation time 414624608 ps
CPU time 3.28 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 198040 kb
Host smart-8b828c1c-6398-40a4-8f9f-b89d7c39b3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554251213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3554251213
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.4054433619
Short name T556
Test name
Test status
Simulation time 68128479 ps
CPU time 1.26 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 197208 kb
Host smart-b43784ef-6d36-48a7-a371-c6b41bb66ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054433619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.4054433619
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2665810923
Short name T583
Test name
Test status
Simulation time 50579011 ps
CPU time 1.13 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 197048 kb
Host smart-27654cd7-ce23-46f1-81e9-c069ee61ea0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665810923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2665810923
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2916486114
Short name T479
Test name
Test status
Simulation time 15711642570 ps
CPU time 109.1 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:35:00 PM PDT 24
Peak memory 198128 kb
Host smart-b50a7f30-1189-4592-be04-18482683c8af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916486114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2916486114
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2547195129
Short name T658
Test name
Test status
Simulation time 15139947 ps
CPU time 0.55 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 193852 kb
Host smart-45b4b037-1a0c-47d1-ba34-22fcfebc35e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547195129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2547195129
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3867113785
Short name T73
Test name
Test status
Simulation time 46520467 ps
CPU time 0.62 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 194620 kb
Host smart-5b104024-e452-4afc-a365-8fc97e8de858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867113785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3867113785
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2688565069
Short name T283
Test name
Test status
Simulation time 921306594 ps
CPU time 21.7 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:41 PM PDT 24
Peak memory 196764 kb
Host smart-9f336a52-5470-46c1-a247-35d48f6a1527
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688565069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2688565069
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2582949949
Short name T300
Test name
Test status
Simulation time 44952681 ps
CPU time 0.77 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196712 kb
Host smart-3ce3bacc-4dc4-4bcb-8f70-ad2488d3564c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582949949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2582949949
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1110006709
Short name T229
Test name
Test status
Simulation time 234175291 ps
CPU time 1.05 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195916 kb
Host smart-9d73cfe5-7d53-4083-96b4-08cc8fd45356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110006709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1110006709
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2230028570
Short name T708
Test name
Test status
Simulation time 113939205 ps
CPU time 2.35 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 198096 kb
Host smart-1a6b6142-e899-4351-9089-23349267e777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230028570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2230028570
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1189178848
Short name T459
Test name
Test status
Simulation time 181426818 ps
CPU time 1.85 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 195868 kb
Host smart-f11e99ec-552c-49d0-a31a-ce410f4f9330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189178848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1189178848
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1675620779
Short name T590
Test name
Test status
Simulation time 37092658 ps
CPU time 1.3 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 198084 kb
Host smart-c86116d0-d1ad-4c4a-899c-9fa601ded75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675620779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1675620779
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2417541030
Short name T651
Test name
Test status
Simulation time 138500748 ps
CPU time 0.85 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196544 kb
Host smart-316325ed-6295-4b7e-80aa-23e38bad316e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417541030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2417541030
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2593424365
Short name T24
Test name
Test status
Simulation time 185092430 ps
CPU time 2.3 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196548 kb
Host smart-957394b2-c956-4723-95fc-4ae546db2d24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593424365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2593424365
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1110087217
Short name T461
Test name
Test status
Simulation time 40540082 ps
CPU time 1.11 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 195820 kb
Host smart-5c32ce93-c612-496b-91c8-8e39d0938f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110087217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1110087217
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.303951765
Short name T498
Test name
Test status
Simulation time 75565570 ps
CPU time 1.12 seconds
Started Apr 15 12:33:07 PM PDT 24
Finished Apr 15 12:33:08 PM PDT 24
Peak memory 197100 kb
Host smart-38a5ad5c-97c4-46cc-9a7f-f13036b0c1ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303951765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.303951765
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3300685797
Short name T9
Test name
Test status
Simulation time 38696796140 ps
CPU time 55.97 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:34:15 PM PDT 24
Peak memory 198164 kb
Host smart-62f5a2ad-bfd6-4e7a-b9a5-cd8a3eca7669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300685797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3300685797
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3217529106
Short name T152
Test name
Test status
Simulation time 22929948 ps
CPU time 0.54 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:13 PM PDT 24
Peak memory 194004 kb
Host smart-2da3f3c2-eb03-48af-bc31-5bd3c1e4403c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217529106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3217529106
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1244939103
Short name T104
Test name
Test status
Simulation time 43753634 ps
CPU time 0.94 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 195960 kb
Host smart-662391fa-4fbb-421b-bf93-c9c1d1c74789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244939103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1244939103
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1314387350
Short name T235
Test name
Test status
Simulation time 71680757 ps
CPU time 3.66 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195856 kb
Host smart-fb4f9395-1683-45db-b2e1-6ae4f3920ca5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314387350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1314387350
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3245643361
Short name T22
Test name
Test status
Simulation time 43976604 ps
CPU time 0.73 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 194792 kb
Host smart-72d4af07-481c-47bf-92ea-4a34681da3c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245643361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3245643361
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1353649986
Short name T117
Test name
Test status
Simulation time 460309807 ps
CPU time 0.86 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196812 kb
Host smart-c8fe9912-318f-44d4-8acc-87a437b3b79d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353649986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1353649986
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1090442839
Short name T553
Test name
Test status
Simulation time 94796130 ps
CPU time 1.98 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 198044 kb
Host smart-fe16ebe7-1162-4b5b-9445-225e1dd58dfd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090442839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1090442839
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2124372250
Short name T308
Test name
Test status
Simulation time 514820505 ps
CPU time 2.61 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 198000 kb
Host smart-f5a59ce4-821d-4480-b960-f6f326cd0b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124372250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2124372250
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1654630574
Short name T447
Test name
Test status
Simulation time 30185518 ps
CPU time 1.07 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196180 kb
Host smart-ced45fe2-f086-43ee-9280-bb9db14fac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654630574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1654630574
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1131328818
Short name T237
Test name
Test status
Simulation time 97420646 ps
CPU time 0.82 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 196468 kb
Host smart-06b458aa-686d-4737-b290-8c660947eecc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131328818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1131328818
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2209348235
Short name T449
Test name
Test status
Simulation time 195562827 ps
CPU time 1.32 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 197940 kb
Host smart-549f9c7a-7082-4d21-b1ac-339f45ecd544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209348235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2209348235
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.297444306
Short name T492
Test name
Test status
Simulation time 52358915 ps
CPU time 1.35 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196912 kb
Host smart-c12502bb-1eb0-4f0e-b26b-6282759a6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297444306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.297444306
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1772747857
Short name T509
Test name
Test status
Simulation time 252964330 ps
CPU time 1.1 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 195784 kb
Host smart-9c4767cf-5b60-4b0c-bf43-42e421df6c86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772747857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1772747857
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.969701225
Short name T8
Test name
Test status
Simulation time 29796474471 ps
CPU time 166.62 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 198280 kb
Host smart-12ae97a2-17b2-4fd7-ab11-7efbdfc2df78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969701225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.969701225
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2041403047
Short name T377
Test name
Test status
Simulation time 43072744 ps
CPU time 0.61 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 194036 kb
Host smart-3915395d-b4c3-41e4-9d8f-a965568652e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041403047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2041403047
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1945336049
Short name T202
Test name
Test status
Simulation time 247372744 ps
CPU time 6.36 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:27 PM PDT 24
Peak memory 196940 kb
Host smart-a964d38d-050a-4951-b2c6-74aa260e1229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945336049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1945336049
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.815309560
Short name T166
Test name
Test status
Simulation time 47390554 ps
CPU time 0.82 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196816 kb
Host smart-974da3c4-617a-45f2-9cab-45f6ec943116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815309560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.815309560
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1064278421
Short name T236
Test name
Test status
Simulation time 93246408 ps
CPU time 0.67 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 194164 kb
Host smart-701a71ac-1b2b-46e8-b133-4b36fa471f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064278421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1064278421
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3445400244
Short name T418
Test name
Test status
Simulation time 567680819 ps
CPU time 1.97 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 198180 kb
Host smart-76fc40f1-d2c5-441e-bb86-86435f89b49d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445400244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3445400244
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1754997185
Short name T591
Test name
Test status
Simulation time 51134093 ps
CPU time 1.09 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 195768 kb
Host smart-7c6c2db6-a52b-4fc1-8593-8cf0771c0e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754997185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1754997185
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2024959896
Short name T516
Test name
Test status
Simulation time 239288127 ps
CPU time 1.13 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 196088 kb
Host smart-888be9af-50c4-4d33-a6dc-60c549073b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024959896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2024959896
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1394603377
Short name T655
Test name
Test status
Simulation time 61257020 ps
CPU time 0.75 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 195664 kb
Host smart-b14af5ca-0187-4114-8748-f69799a112c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394603377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1394603377
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.293823586
Short name T228
Test name
Test status
Simulation time 192593511 ps
CPU time 3.33 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 198020 kb
Host smart-cd59a48b-0b7a-4a04-9d55-160ec26246f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293823586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.293823586
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3656542871
Short name T489
Test name
Test status
Simulation time 203470356 ps
CPU time 1.02 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196580 kb
Host smart-5ceb261b-9a3d-4df4-a78a-3f76fb26b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656542871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3656542871
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.584276015
Short name T616
Test name
Test status
Simulation time 1151114841 ps
CPU time 1.11 seconds
Started Apr 15 12:33:08 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 196260 kb
Host smart-4c5636f8-4f64-4436-80dd-0877523d1185
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584276015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.584276015
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.907050823
Short name T485
Test name
Test status
Simulation time 35580456710 ps
CPU time 87.48 seconds
Started Apr 15 12:33:07 PM PDT 24
Finished Apr 15 12:34:35 PM PDT 24
Peak memory 198132 kb
Host smart-800c9947-564f-4cc5-b3a4-3ca86cb87f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907050823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.907050823
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3259313238
Short name T385
Test name
Test status
Simulation time 25336604 ps
CPU time 0.57 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 194056 kb
Host smart-dd7ad773-2ba7-49bc-bb2f-1c3994bd6bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259313238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3259313238
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3687285809
Short name T469
Test name
Test status
Simulation time 42377035 ps
CPU time 0.88 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:11 PM PDT 24
Peak memory 197260 kb
Host smart-83aa8855-8c86-4d3e-92ec-38293fc2d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687285809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3687285809
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2628709249
Short name T539
Test name
Test status
Simulation time 1195099614 ps
CPU time 10.81 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:36 PM PDT 24
Peak memory 196884 kb
Host smart-3dfb1c3d-41cf-407e-aafc-fa58c7a27767
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628709249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2628709249
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3075333588
Short name T472
Test name
Test status
Simulation time 80128377 ps
CPU time 0.81 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195932 kb
Host smart-34c500c1-f723-4e85-bf77-ff8339a9612f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075333588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3075333588
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.518594267
Short name T181
Test name
Test status
Simulation time 35969389 ps
CPU time 1.01 seconds
Started Apr 15 12:33:09 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 196556 kb
Host smart-3112ce37-689a-4f9d-8cfd-a010eb13fbae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518594267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.518594267
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1588066028
Short name T169
Test name
Test status
Simulation time 171298705 ps
CPU time 3.21 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 198192 kb
Host smart-eb526d97-3eb6-4981-8686-c1092e2a4aef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588066028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1588066028
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.2482261397
Short name T135
Test name
Test status
Simulation time 327685395 ps
CPU time 2.44 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195868 kb
Host smart-8ce7dba5-eb71-4af7-9127-73d22ddc0026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482261397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.2482261397
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2755380447
Short name T347
Test name
Test status
Simulation time 23200600 ps
CPU time 0.7 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 195356 kb
Host smart-03ff4085-5865-4cac-9bf0-40f47020256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755380447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2755380447
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.996236703
Short name T623
Test name
Test status
Simulation time 141823388 ps
CPU time 0.8 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 196480 kb
Host smart-1fd19a81-8c1c-4fec-b8ca-1fb1e8e1edb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996236703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.996236703
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1417186507
Short name T434
Test name
Test status
Simulation time 1188788490 ps
CPU time 4.23 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 198016 kb
Host smart-3db8df8c-b2f5-4b7f-8949-b2db73797fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417186507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1417186507
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.53684947
Short name T252
Test name
Test status
Simulation time 23895503 ps
CPU time 0.68 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 194928 kb
Host smart-2d8a36f6-11e8-47a1-bbf7-be0a3536fdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53684947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.53684947
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2203265959
Short name T189
Test name
Test status
Simulation time 47036108 ps
CPU time 1 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195780 kb
Host smart-5adb2559-5ae7-4f4c-8980-478bea654518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203265959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2203265959
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.776143597
Short name T478
Test name
Test status
Simulation time 35732238983 ps
CPU time 95.76 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:34:59 PM PDT 24
Peak memory 198160 kb
Host smart-a4c08b0e-f162-4773-92e6-ef47b591710a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776143597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.776143597
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1542433638
Short name T530
Test name
Test status
Simulation time 53739726 ps
CPU time 0.55 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:33:46 PM PDT 24
Peak memory 194016 kb
Host smart-5dac7ea3-9065-4dac-9873-4f3eb05307a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542433638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1542433638
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1404803718
Short name T360
Test name
Test status
Simulation time 149438785 ps
CPU time 0.88 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195180 kb
Host smart-9e077db5-1b91-4bdd-b997-bd3cf5389947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404803718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1404803718
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.635655548
Short name T596
Test name
Test status
Simulation time 158365766 ps
CPU time 5.51 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 196792 kb
Host smart-7c4b3cea-d8bc-4228-bf9d-bd7fad4a1735
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635655548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.635655548
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1214078087
Short name T346
Test name
Test status
Simulation time 374100849 ps
CPU time 1.05 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196812 kb
Host smart-efdae49e-2669-4410-9c98-b13019facf92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214078087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1214078087
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2868932411
Short name T214
Test name
Test status
Simulation time 70249497 ps
CPU time 0.74 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195592 kb
Host smart-e9ce050a-e9cb-4eff-bd29-69226cad3458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868932411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2868932411
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.285055151
Short name T242
Test name
Test status
Simulation time 177301535 ps
CPU time 1.45 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 198040 kb
Host smart-b8078c6b-988e-4c25-826e-77736d4b00c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285055151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.285055151
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1119519012
Short name T77
Test name
Test status
Simulation time 560163387 ps
CPU time 2.43 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 197120 kb
Host smart-d9022b28-590e-4f00-8880-919c4eeeaf68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119519012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1119519012
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1555322345
Short name T693
Test name
Test status
Simulation time 19469267 ps
CPU time 0.73 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 196228 kb
Host smart-c61ab2ca-bf10-4a7a-b1bc-c06ffa942b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555322345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1555322345
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1863612121
Short name T374
Test name
Test status
Simulation time 86807683 ps
CPU time 0.89 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 195800 kb
Host smart-3208b564-1334-4e0d-b87d-61b761604333
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863612121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1863612121
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2980596991
Short name T19
Test name
Test status
Simulation time 530376328 ps
CPU time 4.48 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 198156 kb
Host smart-5a223336-4248-4fba-a4c0-23c4a1783fe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980596991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2980596991
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.29218014
Short name T417
Test name
Test status
Simulation time 53867241 ps
CPU time 1.03 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196392 kb
Host smart-d85f07fa-6b30-417f-b27c-d445021c1386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29218014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.29218014
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1524965863
Short name T27
Test name
Test status
Simulation time 625920939 ps
CPU time 1.23 seconds
Started Apr 15 12:33:44 PM PDT 24
Finished Apr 15 12:33:46 PM PDT 24
Peak memory 196672 kb
Host smart-d8da6c13-c168-4c59-ae46-570384ef6dcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524965863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1524965863
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3395214935
Short name T247
Test name
Test status
Simulation time 40037969324 ps
CPU time 144.72 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:35:42 PM PDT 24
Peak memory 198072 kb
Host smart-a15a6904-16c5-4701-a47a-d8dd51fc71f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395214935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3395214935
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3689210700
Short name T38
Test name
Test status
Simulation time 35877769457 ps
CPU time 822.87 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:47:00 PM PDT 24
Peak memory 198192 kb
Host smart-6e6e846d-4103-44b1-9db1-e3c541696dc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3689210700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3689210700
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2111213733
Short name T220
Test name
Test status
Simulation time 44099297 ps
CPU time 0.59 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 194652 kb
Host smart-e9d216e1-f282-4951-a61f-248346213a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111213733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2111213733
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.396932063
Short name T350
Test name
Test status
Simulation time 35428854 ps
CPU time 0.85 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 195260 kb
Host smart-9933d1f9-6c08-4950-860f-082726ba7bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396932063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.396932063
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1900621381
Short name T532
Test name
Test status
Simulation time 219572562 ps
CPU time 10.66 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 196976 kb
Host smart-8a1e7f08-566d-4d4d-a2cb-086b9363dd16
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900621381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1900621381
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1417416655
Short name T376
Test name
Test status
Simulation time 310288898 ps
CPU time 0.94 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 197272 kb
Host smart-15ce60bd-b8de-476a-b0d2-449c0276ec89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417416655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1417416655
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2131362054
Short name T285
Test name
Test status
Simulation time 95736601 ps
CPU time 1.13 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 196172 kb
Host smart-66bffed1-8f33-4b6e-875f-f041fcf30951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131362054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2131362054
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1287021442
Short name T329
Test name
Test status
Simulation time 32695209 ps
CPU time 1.26 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 196468 kb
Host smart-97554ba2-6c28-45eb-baab-e5385638af85
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287021442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1287021442
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2005150651
Short name T217
Test name
Test status
Simulation time 30532880 ps
CPU time 0.96 seconds
Started Apr 15 12:33:28 PM PDT 24
Finished Apr 15 12:33:30 PM PDT 24
Peak memory 195712 kb
Host smart-78a1f1c8-a4b7-4181-8024-82585d87371c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005150651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2005150651
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1892075456
Short name T330
Test name
Test status
Simulation time 24342729 ps
CPU time 0.92 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 196032 kb
Host smart-71caea14-f8f8-4ea6-9787-4cce088a3f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892075456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1892075456
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1656777948
Short name T357
Test name
Test status
Simulation time 22020563 ps
CPU time 0.68 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 195092 kb
Host smart-3cb8402d-005a-42a4-aa5e-3d072ed348b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656777948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1656777948
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4252542053
Short name T2
Test name
Test status
Simulation time 1300614783 ps
CPU time 4.36 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 197988 kb
Host smart-f5e9894b-ec05-44a3-896b-82b4c07bae8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252542053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4252542053
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1898095836
Short name T525
Test name
Test status
Simulation time 126855770 ps
CPU time 1.32 seconds
Started Apr 15 12:33:05 PM PDT 24
Finished Apr 15 12:33:07 PM PDT 24
Peak memory 196784 kb
Host smart-be7915ba-2e7b-4049-a3a9-518d6239f9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898095836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1898095836
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1906059360
Short name T594
Test name
Test status
Simulation time 203521987 ps
CPU time 0.96 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 195700 kb
Host smart-ddb9f281-e141-47d0-8b43-5888823f0584
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906059360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1906059360
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.251877757
Short name T529
Test name
Test status
Simulation time 27434560787 ps
CPU time 152.42 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 198148 kb
Host smart-19b802ec-c747-4a73-a013-0867415b1e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251877757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.251877757
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.936698266
Short name T223
Test name
Test status
Simulation time 43405482 ps
CPU time 0.61 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 191608 kb
Host smart-41189a33-7f98-46a9-9bc3-f5f127927114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936698266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.936698266
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1078197156
Short name T362
Test name
Test status
Simulation time 171744673 ps
CPU time 0.89 seconds
Started Apr 15 12:32:27 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 196680 kb
Host smart-6a481aa3-8ff3-420e-b7df-ea526595d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078197156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1078197156
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2096777463
Short name T589
Test name
Test status
Simulation time 1793392827 ps
CPU time 23.4 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:48 PM PDT 24
Peak memory 196216 kb
Host smart-74670f98-58da-4bdc-b433-a1636f2fe2ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096777463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2096777463
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.150767235
Short name T420
Test name
Test status
Simulation time 39648274 ps
CPU time 0.73 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 195960 kb
Host smart-cefc7fba-8327-4b7b-9685-4c5a5e7ec757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150767235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.150767235
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3981691009
Short name T34
Test name
Test status
Simulation time 34015327 ps
CPU time 0.81 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 195584 kb
Host smart-f429c57d-3d6b-4a4c-b5a8-12f4b43abe3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981691009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3981691009
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1072976500
Short name T352
Test name
Test status
Simulation time 62337205 ps
CPU time 1.52 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 198048 kb
Host smart-f46415f1-6e2b-4d8c-9d00-aa308cc7fd3e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072976500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1072976500
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.321601990
Short name T486
Test name
Test status
Simulation time 107231581 ps
CPU time 1.38 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 195888 kb
Host smart-97340bda-564b-4113-8f5b-73e224bfe27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321601990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.321601990
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1772202816
Short name T272
Test name
Test status
Simulation time 34551004 ps
CPU time 1.07 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 197400 kb
Host smart-24e5db54-83a1-43aa-9477-e3f7742fd075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772202816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1772202816
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.813688193
Short name T356
Test name
Test status
Simulation time 27277741 ps
CPU time 0.99 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 196704 kb
Host smart-28310218-6692-46f7-845c-b8e09325d7dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813688193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.813688193
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.54696785
Short name T678
Test name
Test status
Simulation time 42358678 ps
CPU time 1.02 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 196392 kb
Host smart-2b875b18-3b31-4170-9b6c-d872a052cb2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54696785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rando
m_long_reg_writes_reg_reads.54696785
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2189100563
Short name T42
Test name
Test status
Simulation time 228056589 ps
CPU time 0.82 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 213712 kb
Host smart-a3b84eed-577e-4885-a5aa-7a684df9be41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189100563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2189100563
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1034303619
Short name T381
Test name
Test status
Simulation time 83288093 ps
CPU time 1.3 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 196800 kb
Host smart-8967b554-ffb4-4924-8fea-b324ca65ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034303619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1034303619
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.722228174
Short name T63
Test name
Test status
Simulation time 178251666 ps
CPU time 0.95 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 196292 kb
Host smart-fb154f5f-d252-4887-83ea-b9ec98b190d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722228174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.722228174
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3989135751
Short name T199
Test name
Test status
Simulation time 12703134695 ps
CPU time 36.98 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:57 PM PDT 24
Peak memory 198220 kb
Host smart-3a346495-8ff5-4510-bd1a-54a2036704d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989135751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3989135751
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1391580648
Short name T635
Test name
Test status
Simulation time 24494787 ps
CPU time 0.57 seconds
Started Apr 15 12:33:10 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 193916 kb
Host smart-95867e73-9451-43aa-a7ab-f06e45563e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391580648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1391580648
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3014796625
Short name T404
Test name
Test status
Simulation time 56564201 ps
CPU time 0.67 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 194156 kb
Host smart-c89019d7-7856-47e4-8677-b2b5fada33ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014796625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3014796625
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.943190279
Short name T549
Test name
Test status
Simulation time 304331408 ps
CPU time 7.78 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196912 kb
Host smart-126d4dac-26f2-428f-bb19-d9fff8c80c99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943190279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.943190279
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3576923983
Short name T524
Test name
Test status
Simulation time 348517225 ps
CPU time 1.12 seconds
Started Apr 15 12:33:12 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 196760 kb
Host smart-35d15ee1-bc2c-491a-b088-29fc6218d2df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576923983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3576923983
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.229838714
Short name T463
Test name
Test status
Simulation time 108812118 ps
CPU time 0.79 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 195616 kb
Host smart-fa53eb89-3d18-4efc-af8c-d9c22d35e21f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229838714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.229838714
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3053236405
Short name T542
Test name
Test status
Simulation time 80986791 ps
CPU time 3.28 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 198084 kb
Host smart-1d7d4b3a-08c5-456e-b59e-f10e77bda44a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053236405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3053236405
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3957154384
Short name T312
Test name
Test status
Simulation time 33415011 ps
CPU time 0.93 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195736 kb
Host smart-8d9ed188-6c54-47e5-b2be-6811b832d072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957154384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3957154384
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3443744069
Short name T573
Test name
Test status
Simulation time 126719880 ps
CPU time 1.21 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 197140 kb
Host smart-95ad0959-fb4c-4400-b7d0-e2f2d682ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443744069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3443744069
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.650850794
Short name T574
Test name
Test status
Simulation time 67034107 ps
CPU time 0.86 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195524 kb
Host smart-9d3ee9ed-a906-42e5-8fcc-42a717ce899c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650850794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullup
_pulldown.650850794
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2590028217
Short name T480
Test name
Test status
Simulation time 114302696 ps
CPU time 2.06 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 198012 kb
Host smart-aa52a23b-a806-4aa5-ad2c-5d70ae2848c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590028217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2590028217
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3463450975
Short name T165
Test name
Test status
Simulation time 132070119 ps
CPU time 0.75 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 195292 kb
Host smart-64222a89-265a-4ed4-9d07-1acf08a267b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463450975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3463450975
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.58015611
Short name T232
Test name
Test status
Simulation time 27878648 ps
CPU time 0.82 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 196092 kb
Host smart-daeb7263-0c42-4ab3-8abe-b51a7f6b74fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58015611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.58015611
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.4254385986
Short name T311
Test name
Test status
Simulation time 19468888912 ps
CPU time 51.07 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:34:14 PM PDT 24
Peak memory 198128 kb
Host smart-2e0bc624-0a8c-4a8f-98ed-63210a9005d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254385986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.4254385986
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.863135245
Short name T65
Test name
Test status
Simulation time 34162927435 ps
CPU time 373.01 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 198188 kb
Host smart-7211bc5a-f6f7-4139-a07e-0e6a7a9307c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=863135245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.863135245
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.784415997
Short name T500
Test name
Test status
Simulation time 13443300 ps
CPU time 0.56 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 193944 kb
Host smart-218e6a8c-ddc2-48ce-9fcf-e41ab34f6dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784415997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.784415997
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.354431436
Short name T253
Test name
Test status
Simulation time 29056508 ps
CPU time 0.62 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 194068 kb
Host smart-66e2a921-9021-4c0f-b32a-c4b28acf24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354431436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.354431436
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1149004162
Short name T307
Test name
Test status
Simulation time 535109069 ps
CPU time 28.03 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:42 PM PDT 24
Peak memory 198108 kb
Host smart-9bb14077-9ef0-4674-8003-ecbc6229f471
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149004162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1149004162
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2991275960
Short name T140
Test name
Test status
Simulation time 40875154 ps
CPU time 0.78 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195932 kb
Host smart-3bfc31c8-4f16-4959-bd51-d5d328f5db46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991275960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2991275960
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3567565767
Short name T176
Test name
Test status
Simulation time 310566708 ps
CPU time 1.21 seconds
Started Apr 15 12:33:23 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 196124 kb
Host smart-40a36447-c2d2-449c-a964-53c8a3544406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567565767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3567565767
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.804560426
Short name T255
Test name
Test status
Simulation time 306001517 ps
CPU time 2.95 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 198132 kb
Host smart-9b2d34a7-c0b0-4663-8bc7-fa0796956b5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804560426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.804560426
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3663811137
Short name T394
Test name
Test status
Simulation time 373766371 ps
CPU time 1.96 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 195828 kb
Host smart-7ea6551e-81a9-44e3-a17f-22f2e9187b86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663811137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3663811137
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1381975631
Short name T72
Test name
Test status
Simulation time 1151574679 ps
CPU time 1.17 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 198060 kb
Host smart-1c7a3323-54dc-434a-ade4-f90aa6a80c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381975631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1381975631
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1816189184
Short name T233
Test name
Test status
Simulation time 58685416 ps
CPU time 0.63 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 194328 kb
Host smart-95e49804-793f-4dc1-a6fc-242658a2ea63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816189184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1816189184
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1833756840
Short name T666
Test name
Test status
Simulation time 60080001 ps
CPU time 1.28 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 198012 kb
Host smart-c6e2e3a8-7381-49dd-b0ed-a6843dd27010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833756840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1833756840
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.977572005
Short name T75
Test name
Test status
Simulation time 41931982 ps
CPU time 0.86 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195240 kb
Host smart-cf7495f3-8fbe-4a4d-8056-c9fa4febcd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977572005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.977572005
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1923560289
Short name T645
Test name
Test status
Simulation time 282005677 ps
CPU time 0.95 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 195560 kb
Host smart-ceb8def4-42a5-4ac8-9caa-348ca5f99875
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923560289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1923560289
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1119667768
Short name T619
Test name
Test status
Simulation time 48797249147 ps
CPU time 175.86 seconds
Started Apr 15 12:33:33 PM PDT 24
Finished Apr 15 12:36:29 PM PDT 24
Peak memory 198176 kb
Host smart-954b630e-edfd-4161-9e4e-64d690905eb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119667768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1119667768
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.340630254
Short name T557
Test name
Test status
Simulation time 187322338119 ps
CPU time 1290.96 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:54:48 PM PDT 24
Peak memory 198296 kb
Host smart-0cfa994b-8d2e-4111-8e63-3e1d13ef1500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=340630254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.340630254
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3956426730
Short name T119
Test name
Test status
Simulation time 28261103 ps
CPU time 0.57 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 194816 kb
Host smart-80ab82b6-80ca-42b3-bef9-d2f75b1722b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956426730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3956426730
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.409438119
Short name T348
Test name
Test status
Simulation time 32620086 ps
CPU time 0.73 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:14 PM PDT 24
Peak memory 195360 kb
Host smart-cdb1b82f-9c07-4e7b-b572-a11e6301abd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409438119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.409438119
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2473223738
Short name T450
Test name
Test status
Simulation time 265303944 ps
CPU time 13.35 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:32 PM PDT 24
Peak memory 196652 kb
Host smart-77231eef-300b-4baf-bade-0efcb20b6d5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473223738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2473223738
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2107037561
Short name T180
Test name
Test status
Simulation time 133741494 ps
CPU time 1.01 seconds
Started Apr 15 12:33:42 PM PDT 24
Finished Apr 15 12:33:44 PM PDT 24
Peak memory 196432 kb
Host smart-e4105cf0-9eba-4f55-9c54-ce07273889f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107037561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2107037561
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3945453909
Short name T11
Test name
Test status
Simulation time 26973538 ps
CPU time 0.74 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 194492 kb
Host smart-42528904-e6ca-473f-ac35-080dec96f7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945453909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3945453909
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3582610672
Short name T266
Test name
Test status
Simulation time 95545580 ps
CPU time 3.14 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 196388 kb
Host smart-c563cb85-7035-47f1-b58c-031dec703e24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582610672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3582610672
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.304191295
Short name T648
Test name
Test status
Simulation time 120986644 ps
CPU time 2.02 seconds
Started Apr 15 12:33:11 PM PDT 24
Finished Apr 15 12:33:15 PM PDT 24
Peak memory 198040 kb
Host smart-a46ab1eb-230d-4eba-b5b5-ac233016cf3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304191295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
304191295
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2700080154
Short name T521
Test name
Test status
Simulation time 32442146 ps
CPU time 1.15 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 197124 kb
Host smart-a22b8b38-6162-47e6-9bf8-0a0c042b8c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700080154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2700080154
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3447666445
Short name T679
Test name
Test status
Simulation time 51184333 ps
CPU time 1.09 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196196 kb
Host smart-2821170d-5656-41f7-97c0-f6555ffaa578
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447666445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3447666445
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2646420065
Short name T512
Test name
Test status
Simulation time 978212697 ps
CPU time 6.42 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 198052 kb
Host smart-df712400-70d1-40e0-85d1-e7619b23c4d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646420065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2646420065
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2149929303
Short name T647
Test name
Test status
Simulation time 76395635 ps
CPU time 1.04 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:17 PM PDT 24
Peak memory 195740 kb
Host smart-1af5d8ba-dc8b-42a9-bc54-73aa746ad2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149929303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2149929303
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2290398414
Short name T287
Test name
Test status
Simulation time 47781684 ps
CPU time 1.22 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 196812 kb
Host smart-58f7ecb8-b085-4f6c-ab02-eeed7595ef9a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290398414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2290398414
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.881576264
Short name T167
Test name
Test status
Simulation time 36244875577 ps
CPU time 192.89 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:36:34 PM PDT 24
Peak memory 198148 kb
Host smart-a9080c37-c5d1-4ffe-a929-fd83d8b5d2d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881576264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.881576264
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2273963874
Short name T314
Test name
Test status
Simulation time 10651732 ps
CPU time 0.6 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 194740 kb
Host smart-4d7c35e8-65de-4314-8cb6-7e27a1838505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273963874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2273963874
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1826892205
Short name T148
Test name
Test status
Simulation time 89138597 ps
CPU time 0.82 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 195304 kb
Host smart-cc4b5f78-d410-4e93-979f-db002075c88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826892205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1826892205
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.274352631
Short name T116
Test name
Test status
Simulation time 864652502 ps
CPU time 12.42 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:34 PM PDT 24
Peak memory 196440 kb
Host smart-603a6523-513f-425f-9945-8eb789618daf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274352631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.274352631
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1141392239
Short name T304
Test name
Test status
Simulation time 96813296 ps
CPU time 0.81 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 196880 kb
Host smart-d3ff6081-fef1-48e8-b84b-0d9dc32f70ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141392239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1141392239
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3181659449
Short name T633
Test name
Test status
Simulation time 132668489 ps
CPU time 1 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 196032 kb
Host smart-c30a4b50-6cb2-427d-8183-cf7485f68b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181659449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3181659449
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.623330070
Short name T149
Test name
Test status
Simulation time 79258417 ps
CPU time 2.2 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 198120 kb
Host smart-2997f4f3-68ac-4c18-a43f-bb11e895dbe8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623330070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.623330070
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3009832082
Short name T650
Test name
Test status
Simulation time 66980295 ps
CPU time 1.91 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:27 PM PDT 24
Peak memory 197188 kb
Host smart-01a7f6be-265b-4275-8770-f268dae43117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009832082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3009832082
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3945036404
Short name T270
Test name
Test status
Simulation time 266703203 ps
CPU time 0.7 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195592 kb
Host smart-8cae16df-2899-4ad9-9a1c-f8895e65aa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945036404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3945036404
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.243728109
Short name T559
Test name
Test status
Simulation time 44426973 ps
CPU time 1.06 seconds
Started Apr 15 12:33:40 PM PDT 24
Finished Apr 15 12:33:42 PM PDT 24
Peak memory 196136 kb
Host smart-4df55513-8e8b-4617-8450-0bdc2c91e510
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243728109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.243728109
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2294600553
Short name T504
Test name
Test status
Simulation time 772163619 ps
CPU time 3.91 seconds
Started Apr 15 12:33:21 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 198032 kb
Host smart-60186f03-4552-408a-964e-85e8c50b71d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294600553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2294600553
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1585951387
Short name T577
Test name
Test status
Simulation time 50988345 ps
CPU time 1.35 seconds
Started Apr 15 12:33:41 PM PDT 24
Finished Apr 15 12:33:43 PM PDT 24
Peak memory 195612 kb
Host smart-490fe00a-ba8c-4c0e-80cf-11c75961528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585951387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1585951387
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3328832856
Short name T698
Test name
Test status
Simulation time 38432090 ps
CPU time 0.82 seconds
Started Apr 15 12:33:15 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 195428 kb
Host smart-67fd8ec8-aa42-42ab-b1ca-029401e7fdf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328832856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3328832856
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.370290751
Short name T4
Test name
Test status
Simulation time 13783825918 ps
CPU time 163.75 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:36:29 PM PDT 24
Peak memory 198140 kb
Host smart-c7bb824e-772b-4155-ae04-1adf17c13102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370290751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.370290751
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3191519285
Short name T581
Test name
Test status
Simulation time 19122242737 ps
CPU time 502.68 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:41:42 PM PDT 24
Peak memory 198348 kb
Host smart-c05fe1dd-0a2e-4625-9f2f-d8d35f283e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3191519285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3191519285
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3876390109
Short name T120
Test name
Test status
Simulation time 21507841 ps
CPU time 0.57 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 194160 kb
Host smart-efb1098a-fdd3-491f-b936-2349ea79b85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876390109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3876390109
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1828987904
Short name T31
Test name
Test status
Simulation time 37297219 ps
CPU time 0.69 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 194240 kb
Host smart-75e8eff1-9219-4396-85c3-38c8ed20cb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828987904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1828987904
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.679763638
Short name T164
Test name
Test status
Simulation time 94304661 ps
CPU time 3.16 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 195508 kb
Host smart-7ef68eda-858e-4d50-94d8-f739eaa939ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679763638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.679763638
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2600610494
Short name T637
Test name
Test status
Simulation time 136798693 ps
CPU time 0.68 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195468 kb
Host smart-11721c57-8c71-4b67-8f5c-df3dff1cc9c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600610494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2600610494
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.38225268
Short name T586
Test name
Test status
Simulation time 197071294 ps
CPU time 0.86 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 196768 kb
Host smart-e1aab78d-47af-4c9d-b22f-9d5d58d4b47e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38225268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.38225268
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1082336306
Short name T562
Test name
Test status
Simulation time 47624878 ps
CPU time 1.85 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:19 PM PDT 24
Peak memory 196592 kb
Host smart-5d67650c-c732-488c-8836-0828c48ab9e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082336306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1082336306
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3758013390
Short name T320
Test name
Test status
Simulation time 182244672 ps
CPU time 3.34 seconds
Started Apr 15 12:33:42 PM PDT 24
Finished Apr 15 12:33:46 PM PDT 24
Peak memory 198084 kb
Host smart-f3d98c27-9f14-45e7-9ed4-41c4c99e3d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758013390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3758013390
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1468875686
Short name T212
Test name
Test status
Simulation time 64795969 ps
CPU time 0.78 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195556 kb
Host smart-6ffe3451-4b76-493b-b727-0831273c5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468875686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1468875686
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1569245995
Short name T364
Test name
Test status
Simulation time 182459435 ps
CPU time 0.99 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 196064 kb
Host smart-93ef99e9-d12c-4dfc-a546-7ed5d2113b08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569245995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1569245995
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2860386440
Short name T470
Test name
Test status
Simulation time 393730083 ps
CPU time 2.03 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 198044 kb
Host smart-3b6c173b-7a15-482f-88e9-c5b27735158a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860386440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2860386440
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1161436781
Short name T183
Test name
Test status
Simulation time 25830005 ps
CPU time 0.79 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 195996 kb
Host smart-39e886db-768b-4f60-afd8-ca2387a73909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161436781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1161436781
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1106019146
Short name T130
Test name
Test status
Simulation time 56375194 ps
CPU time 1.14 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195704 kb
Host smart-43069423-daa3-4817-9afb-0401f004381e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106019146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1106019146
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2478161118
Short name T570
Test name
Test status
Simulation time 2399794318 ps
CPU time 57.4 seconds
Started Apr 15 12:33:22 PM PDT 24
Finished Apr 15 12:34:20 PM PDT 24
Peak memory 198216 kb
Host smart-a5359890-36b6-46d6-9fb8-5a498e9a0421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478161118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2478161118
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1225395193
Short name T240
Test name
Test status
Simulation time 26209497 ps
CPU time 0.59 seconds
Started Apr 15 12:33:13 PM PDT 24
Finished Apr 15 12:33:16 PM PDT 24
Peak memory 193968 kb
Host smart-6d3a2cb8-55de-4f34-b6b4-b8ddcd33b706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225395193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1225395193
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3208928136
Short name T179
Test name
Test status
Simulation time 138411626 ps
CPU time 0.89 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 196276 kb
Host smart-e4f4131d-b94c-435c-8c45-88105e8090e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208928136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3208928136
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2912247839
Short name T575
Test name
Test status
Simulation time 271710908 ps
CPU time 3.79 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:24 PM PDT 24
Peak memory 195752 kb
Host smart-82951bf9-9998-4b3e-9986-6c0fe4a4fc45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912247839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2912247839
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1452461889
Short name T332
Test name
Test status
Simulation time 78257015 ps
CPU time 1.06 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 197980 kb
Host smart-a490ac46-1c90-481e-a545-b283218eeb18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452461889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1452461889
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1977911263
Short name T624
Test name
Test status
Simulation time 263323614 ps
CPU time 1.18 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196360 kb
Host smart-f1da0c17-8735-45be-ae08-067853fb3ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977911263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1977911263
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3406664221
Short name T305
Test name
Test status
Simulation time 125624182 ps
CPU time 2.45 seconds
Started Apr 15 12:33:44 PM PDT 24
Finished Apr 15 12:33:52 PM PDT 24
Peak memory 196676 kb
Host smart-cc3d93cd-6e7a-45e6-9bdf-d069a5067332
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406664221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3406664221
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1305441557
Short name T139
Test name
Test status
Simulation time 110403821 ps
CPU time 2.15 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 196752 kb
Host smart-4993d307-3f0c-4c7b-bb3e-fb8c43d0ea30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305441557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1305441557
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3788521392
Short name T640
Test name
Test status
Simulation time 46326145 ps
CPU time 1.09 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 196100 kb
Host smart-451afa67-936d-4771-8e64-66ff51f1df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788521392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3788521392
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.519085469
Short name T686
Test name
Test status
Simulation time 41727931 ps
CPU time 0.85 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 196716 kb
Host smart-967bbbfa-d276-4e28-bc39-8607838798ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519085469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.519085469
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.753573260
Short name T540
Test name
Test status
Simulation time 66762888 ps
CPU time 2.49 seconds
Started Apr 15 12:33:23 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 198044 kb
Host smart-096d2b0b-e210-4dff-9fe0-fe49f1fa79ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753573260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.753573260
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.862070825
Short name T269
Test name
Test status
Simulation time 39407274 ps
CPU time 1.14 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 195548 kb
Host smart-c442ab49-d6e7-4152-bf80-4c77c674ffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862070825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.862070825
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2416718817
Short name T572
Test name
Test status
Simulation time 31004551 ps
CPU time 0.75 seconds
Started Apr 15 12:33:17 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 195428 kb
Host smart-492b3b58-a51f-4fc8-a658-6b812ffa1276
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416718817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2416718817
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2677254480
Short name T628
Test name
Test status
Simulation time 23195664582 ps
CPU time 135.48 seconds
Started Apr 15 12:33:37 PM PDT 24
Finished Apr 15 12:35:53 PM PDT 24
Peak memory 198328 kb
Host smart-fb90a679-a354-4469-a127-e71908c45a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677254480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2677254480
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1631970484
Short name T163
Test name
Test status
Simulation time 34787635 ps
CPU time 0.54 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 193900 kb
Host smart-d3810374-046f-4868-984d-6cd366be8907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631970484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1631970484
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.235281581
Short name T677
Test name
Test status
Simulation time 81397890 ps
CPU time 0.66 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:33:46 PM PDT 24
Peak memory 194128 kb
Host smart-6bb461e1-f4d7-4dbe-a6df-5bc632aa79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235281581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.235281581
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2188140257
Short name T254
Test name
Test status
Simulation time 1121090144 ps
CPU time 25.21 seconds
Started Apr 15 12:33:42 PM PDT 24
Finished Apr 15 12:34:08 PM PDT 24
Peak memory 196728 kb
Host smart-9bca3aff-fdf2-42b7-bff8-c0d62407be80
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188140257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2188140257
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.551719921
Short name T150
Test name
Test status
Simulation time 87992823 ps
CPU time 0.82 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 195908 kb
Host smart-96f0c95c-c128-49df-9273-15a4d97a314b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551719921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.551719921
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1959343056
Short name T194
Test name
Test status
Simulation time 85924446 ps
CPU time 1.35 seconds
Started Apr 15 12:33:18 PM PDT 24
Finished Apr 15 12:33:21 PM PDT 24
Peak memory 196032 kb
Host smart-2bce624b-c92d-4b2a-8b14-5ed773b34f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959343056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1959343056
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.4153073448
Short name T537
Test name
Test status
Simulation time 80416482 ps
CPU time 2.92 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:33 PM PDT 24
Peak memory 198128 kb
Host smart-99c43120-9bf5-47e9-9d5b-c53ad88c4892
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153073448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.4153073448
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3305938731
Short name T161
Test name
Test status
Simulation time 32527454 ps
CPU time 0.94 seconds
Started Apr 15 12:33:29 PM PDT 24
Finished Apr 15 12:33:31 PM PDT 24
Peak memory 196312 kb
Host smart-97764474-c1d3-47f0-884b-ac240a9dbdb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305938731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3305938731
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1232686964
Short name T670
Test name
Test status
Simulation time 70476794 ps
CPU time 0.81 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:33:47 PM PDT 24
Peak memory 196504 kb
Host smart-9f0b793a-64f5-4acd-9b47-6fbe0b03921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232686964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1232686964
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2563783339
Short name T162
Test name
Test status
Simulation time 78361232 ps
CPU time 1.36 seconds
Started Apr 15 12:33:29 PM PDT 24
Finished Apr 15 12:33:31 PM PDT 24
Peak memory 198128 kb
Host smart-4d58063a-8e8b-4dcc-893d-e7bb99f046b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563783339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2563783339
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3926470971
Short name T159
Test name
Test status
Simulation time 1006851410 ps
CPU time 4.33 seconds
Started Apr 15 12:33:50 PM PDT 24
Finished Apr 15 12:33:55 PM PDT 24
Peak memory 198012 kb
Host smart-5f40ecc0-3c8d-4ed2-9955-e10cbab3c0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926470971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3926470971
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2761254915
Short name T634
Test name
Test status
Simulation time 730333002 ps
CPU time 1.07 seconds
Started Apr 15 12:33:14 PM PDT 24
Finished Apr 15 12:33:18 PM PDT 24
Peak memory 195784 kb
Host smart-9d7414a0-1811-4604-8077-43deb06ccd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761254915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2761254915
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.984663561
Short name T128
Test name
Test status
Simulation time 110179816 ps
CPU time 0.93 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:33:20 PM PDT 24
Peak memory 196576 kb
Host smart-7f640f85-c514-4769-a033-8246459e06ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984663561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.984663561
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2017343892
Short name T319
Test name
Test status
Simulation time 12278135679 ps
CPU time 171.83 seconds
Started Apr 15 12:33:42 PM PDT 24
Finished Apr 15 12:36:35 PM PDT 24
Peak memory 198136 kb
Host smart-7942cba6-ac3e-48b5-8580-de0b42377985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017343892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2017343892
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.4158133367
Short name T617
Test name
Test status
Simulation time 29874426405 ps
CPU time 388.27 seconds
Started Apr 15 12:33:16 PM PDT 24
Finished Apr 15 12:39:47 PM PDT 24
Peak memory 198240 kb
Host smart-59164e88-82f5-49b0-b613-6a80319f7fcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4158133367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.4158133367
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.12468246
Short name T216
Test name
Test status
Simulation time 15785113 ps
CPU time 0.6 seconds
Started Apr 15 12:33:51 PM PDT 24
Finished Apr 15 12:33:52 PM PDT 24
Peak memory 192712 kb
Host smart-fbdeb700-0cf9-4ff0-be76-f4ad6c9f9fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.12468246
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3769744879
Short name T663
Test name
Test status
Simulation time 20768309 ps
CPU time 0.62 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 193976 kb
Host smart-a24ed539-117d-4738-ab7b-4f8821b0b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769744879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3769744879
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3783974383
Short name T593
Test name
Test status
Simulation time 827923954 ps
CPU time 12.48 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:38 PM PDT 24
Peak memory 195552 kb
Host smart-4a2f10ae-48d5-4874-9da6-a8e6dc073992
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783974383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3783974383
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1142053691
Short name T328
Test name
Test status
Simulation time 248379111 ps
CPU time 0.93 seconds
Started Apr 15 12:33:52 PM PDT 24
Finished Apr 15 12:33:54 PM PDT 24
Peak memory 197088 kb
Host smart-03600e6b-43bf-4944-bfd8-d694d730289c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142053691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1142053691
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1095361463
Short name T321
Test name
Test status
Simulation time 86124869 ps
CPU time 1.23 seconds
Started Apr 15 12:33:37 PM PDT 24
Finished Apr 15 12:33:39 PM PDT 24
Peak memory 195936 kb
Host smart-7b9e056c-f55a-4d40-aed7-479d62a935b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095361463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1095361463
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.879252324
Short name T215
Test name
Test status
Simulation time 128351567 ps
CPU time 1.5 seconds
Started Apr 15 12:33:23 PM PDT 24
Finished Apr 15 12:33:25 PM PDT 24
Peak memory 198100 kb
Host smart-0376c97e-e162-4391-9cd9-a23015819c98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879252324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.879252324
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3518251217
Short name T468
Test name
Test status
Simulation time 75793459 ps
CPU time 2.17 seconds
Started Apr 15 12:33:29 PM PDT 24
Finished Apr 15 12:33:31 PM PDT 24
Peak memory 197188 kb
Host smart-25554611-aff1-4f00-9b13-b2e06f1d9d63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518251217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3518251217
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3929694550
Short name T599
Test name
Test status
Simulation time 337359339 ps
CPU time 0.96 seconds
Started Apr 15 12:33:20 PM PDT 24
Finished Apr 15 12:33:23 PM PDT 24
Peak memory 196556 kb
Host smart-3a4e492c-f331-4feb-9155-6a698932b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929694550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3929694550
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.582876301
Short name T592
Test name
Test status
Simulation time 150635000 ps
CPU time 0.89 seconds
Started Apr 15 12:33:46 PM PDT 24
Finished Apr 15 12:33:48 PM PDT 24
Peak memory 196100 kb
Host smart-82965dd0-53fc-4fa0-aced-83c57bce179c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582876301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.582876301
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2809754743
Short name T354
Test name
Test status
Simulation time 149884343 ps
CPU time 1.81 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:33:48 PM PDT 24
Peak memory 198072 kb
Host smart-3ff79474-b54e-4e81-b4cd-544c74f0311c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809754743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2809754743
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1367694699
Short name T700
Test name
Test status
Simulation time 92141539 ps
CPU time 0.77 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 195188 kb
Host smart-c6fe2e20-e3f1-463d-b42b-5a28179621f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367694699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1367694699
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1992470453
Short name T56
Test name
Test status
Simulation time 51100768 ps
CPU time 0.93 seconds
Started Apr 15 12:33:19 PM PDT 24
Finished Apr 15 12:33:22 PM PDT 24
Peak memory 196568 kb
Host smart-f4124552-554b-41d9-a6ae-8d92223e37fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992470453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1992470453
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3704064178
Short name T273
Test name
Test status
Simulation time 2155345678 ps
CPU time 68.38 seconds
Started Apr 15 12:33:23 PM PDT 24
Finished Apr 15 12:34:32 PM PDT 24
Peak memory 198212 kb
Host smart-a650ba14-2f9a-4193-a1d8-11583cff2cc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704064178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3704064178
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1489189254
Short name T578
Test name
Test status
Simulation time 47458962706 ps
CPU time 518.83 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:42:05 PM PDT 24
Peak memory 198300 kb
Host smart-9d012c40-d6d6-478a-b775-ee594e2c7b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1489189254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1489189254
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.974537941
Short name T424
Test name
Test status
Simulation time 13117993 ps
CPU time 0.58 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 193952 kb
Host smart-ce49bb1a-d800-4883-bc63-e3346f488f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974537941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.974537941
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.611137820
Short name T505
Test name
Test status
Simulation time 94319282 ps
CPU time 0.83 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 196608 kb
Host smart-98205c15-a272-4de6-9fc9-a9790d56e049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611137820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.611137820
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1037409102
Short name T13
Test name
Test status
Simulation time 602098535 ps
CPU time 5.81 seconds
Started Apr 15 12:33:34 PM PDT 24
Finished Apr 15 12:33:40 PM PDT 24
Peak memory 196980 kb
Host smart-c9134153-43d1-4895-b361-b45e2371df89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037409102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1037409102
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.41939145
Short name T355
Test name
Test status
Simulation time 180380581 ps
CPU time 0.85 seconds
Started Apr 15 12:33:39 PM PDT 24
Finished Apr 15 12:33:40 PM PDT 24
Peak memory 196228 kb
Host smart-3457c7c8-32a4-4e5c-a716-f5a1e043cdf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41939145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.41939145
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1110243412
Short name T387
Test name
Test status
Simulation time 45519592 ps
CPU time 1.23 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:33:27 PM PDT 24
Peak memory 198084 kb
Host smart-38e1a002-020f-44f8-9207-be64adca4795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110243412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1110243412
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2342984077
Short name T340
Test name
Test status
Simulation time 277697175 ps
CPU time 3.01 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:30 PM PDT 24
Peak memory 198268 kb
Host smart-907a4cdf-d26f-47c5-8c5c-6971e9911930
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342984077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2342984077
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.4030228569
Short name T508
Test name
Test status
Simulation time 356919683 ps
CPU time 1.74 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 196212 kb
Host smart-7356cc5a-f9a5-4678-aaff-77fd1042f9d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030228569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.4030228569
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2456595984
Short name T108
Test name
Test status
Simulation time 141314130 ps
CPU time 1.19 seconds
Started Apr 15 12:33:42 PM PDT 24
Finished Apr 15 12:33:44 PM PDT 24
Peak memory 196040 kb
Host smart-dd52bcb9-c306-4dad-bb9e-feba02b22839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456595984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2456595984
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2837836775
Short name T642
Test name
Test status
Simulation time 90331931 ps
CPU time 0.79 seconds
Started Apr 15 12:33:47 PM PDT 24
Finished Apr 15 12:33:49 PM PDT 24
Peak memory 196488 kb
Host smart-1dc7a4d1-c26a-45d5-94fa-c709f3875810
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837836775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2837836775
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.287031776
Short name T23
Test name
Test status
Simulation time 1166332309 ps
CPU time 3.73 seconds
Started Apr 15 12:33:49 PM PDT 24
Finished Apr 15 12:33:54 PM PDT 24
Peak memory 198040 kb
Host smart-e79b0fd9-beb5-4a66-9afe-9cfdd7dbbc20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287031776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.287031776
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2714559814
Short name T437
Test name
Test status
Simulation time 203606924 ps
CPU time 1.13 seconds
Started Apr 15 12:33:24 PM PDT 24
Finished Apr 15 12:33:26 PM PDT 24
Peak memory 195616 kb
Host smart-7e36b873-678d-40bb-bae4-4bc3ed033e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714559814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2714559814
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1545703152
Short name T134
Test name
Test status
Simulation time 145934716 ps
CPU time 0.99 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 196388 kb
Host smart-04b1d949-2b6d-4ced-b816-f3932cf7cc0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545703152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1545703152
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.85592441
Short name T177
Test name
Test status
Simulation time 94806959887 ps
CPU time 231.31 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:37:17 PM PDT 24
Peak memory 198160 kb
Host smart-b5777f27-2aff-4b04-9926-12f34924944e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85592441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gp
io_stress_all.85592441
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.798428613
Short name T64
Test name
Test status
Simulation time 90497275865 ps
CPU time 933.77 seconds
Started Apr 15 12:33:23 PM PDT 24
Finished Apr 15 12:48:58 PM PDT 24
Peak memory 198220 kb
Host smart-0ec665f1-4d33-439a-89a3-8546b584d78d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=798428613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.798428613
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1629865440
Short name T141
Test name
Test status
Simulation time 12818573 ps
CPU time 0.58 seconds
Started Apr 15 12:33:47 PM PDT 24
Finished Apr 15 12:33:49 PM PDT 24
Peak memory 194592 kb
Host smart-9d050f73-c1f3-4855-9451-0cf2033d8b4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629865440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1629865440
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1343838520
Short name T12
Test name
Test status
Simulation time 21327101 ps
CPU time 0.71 seconds
Started Apr 15 12:33:47 PM PDT 24
Finished Apr 15 12:33:49 PM PDT 24
Peak memory 194252 kb
Host smart-cb284a9e-ca60-47a1-91a6-5be353e15466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343838520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1343838520
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1357536215
Short name T295
Test name
Test status
Simulation time 4165198094 ps
CPU time 15.76 seconds
Started Apr 15 12:33:46 PM PDT 24
Finished Apr 15 12:34:03 PM PDT 24
Peak memory 197064 kb
Host smart-09a13f72-0c85-4305-8617-1c620f110484
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357536215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1357536215
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2096221570
Short name T276
Test name
Test status
Simulation time 278114898 ps
CPU time 0.88 seconds
Started Apr 15 12:33:52 PM PDT 24
Finished Apr 15 12:33:54 PM PDT 24
Peak memory 196596 kb
Host smart-58a813f3-ccf2-450a-9281-e546f4318068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096221570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2096221570
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1896929840
Short name T318
Test name
Test status
Simulation time 46673020 ps
CPU time 1.26 seconds
Started Apr 15 12:33:43 PM PDT 24
Finished Apr 15 12:33:45 PM PDT 24
Peak memory 197204 kb
Host smart-539da36a-1816-4bee-aa10-26cf4d15a22c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896929840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1896929840
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3574164806
Short name T26
Test name
Test status
Simulation time 181047065 ps
CPU time 2.49 seconds
Started Apr 15 12:33:45 PM PDT 24
Finished Apr 15 12:33:48 PM PDT 24
Peak memory 198144 kb
Host smart-d87c36d1-f2d8-40e1-8069-7560f17305b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574164806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3574164806
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2004013547
Short name T421
Test name
Test status
Simulation time 1502366319 ps
CPU time 2.82 seconds
Started Apr 15 12:33:28 PM PDT 24
Finished Apr 15 12:33:31 PM PDT 24
Peak memory 198068 kb
Host smart-b65a0a66-823f-443e-bffb-fdbe9cae4066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004013547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2004013547
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1771375603
Short name T625
Test name
Test status
Simulation time 240496300 ps
CPU time 1.19 seconds
Started Apr 15 12:33:29 PM PDT 24
Finished Apr 15 12:33:31 PM PDT 24
Peak memory 196588 kb
Host smart-edde370e-89d1-415d-877e-a8f882a4b375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771375603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1771375603
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3602853867
Short name T265
Test name
Test status
Simulation time 60795488 ps
CPU time 0.82 seconds
Started Apr 15 12:33:47 PM PDT 24
Finished Apr 15 12:33:49 PM PDT 24
Peak memory 196424 kb
Host smart-5fb5ee8f-7f4e-4d8b-a416-ced19af1cd59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602853867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3602853867
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1174478340
Short name T458
Test name
Test status
Simulation time 83730927 ps
CPU time 2.3 seconds
Started Apr 15 12:33:34 PM PDT 24
Finished Apr 15 12:33:37 PM PDT 24
Peak memory 198032 kb
Host smart-07710339-88bf-4379-befb-26c0dd155f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174478340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1174478340
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4161713527
Short name T196
Test name
Test status
Simulation time 39087386 ps
CPU time 1.13 seconds
Started Apr 15 12:33:48 PM PDT 24
Finished Apr 15 12:33:50 PM PDT 24
Peak memory 195812 kb
Host smart-b8038bfe-b803-470a-9f69-42642055efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161713527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4161713527
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1816319609
Short name T580
Test name
Test status
Simulation time 96269703 ps
CPU time 1.42 seconds
Started Apr 15 12:33:53 PM PDT 24
Finished Apr 15 12:33:56 PM PDT 24
Peak memory 196956 kb
Host smart-94d2845e-bbe0-4e16-933e-4281ba23e57a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816319609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1816319609
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1177142086
Short name T507
Test name
Test status
Simulation time 7240711564 ps
CPU time 180.6 seconds
Started Apr 15 12:33:38 PM PDT 24
Finished Apr 15 12:36:39 PM PDT 24
Peak memory 198236 kb
Host smart-f697cc0f-f3a8-4d7e-880c-e03c404d6d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177142086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1177142086
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2677948004
Short name T568
Test name
Test status
Simulation time 257006646234 ps
CPU time 1952.23 seconds
Started Apr 15 12:33:48 PM PDT 24
Finished Apr 15 01:06:26 PM PDT 24
Peak memory 198252 kb
Host smart-a6104f5e-dcbd-40d9-8aaa-4f7da95fd33b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2677948004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2677948004
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.613704161
Short name T401
Test name
Test status
Simulation time 100014802 ps
CPU time 0.58 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 194580 kb
Host smart-391cbf20-5a54-4d3e-9514-a9836b5b222c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613704161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.613704161
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3588612619
Short name T427
Test name
Test status
Simulation time 45552396 ps
CPU time 0.57 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:28 PM PDT 24
Peak memory 191896 kb
Host smart-8379b14c-ec89-4c18-89da-b52d4a39b744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588612619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3588612619
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3075194419
Short name T682
Test name
Test status
Simulation time 283088475 ps
CPU time 4.79 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 196208 kb
Host smart-55ac28a5-98fb-44de-bf8e-001f2e6269a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075194419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3075194419
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1886742013
Short name T466
Test name
Test status
Simulation time 43257132 ps
CPU time 0.74 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 195756 kb
Host smart-756faf64-1a1a-47c4-a2fa-f8f362eea02c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886742013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1886742013
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1609814327
Short name T536
Test name
Test status
Simulation time 28467851 ps
CPU time 0.77 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 196128 kb
Host smart-8e6380aa-937d-4e1f-8469-285ebe99f703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609814327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1609814327
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.958847567
Short name T600
Test name
Test status
Simulation time 194391196 ps
CPU time 2.96 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 198168 kb
Host smart-3736f55d-a83f-4009-9681-824077ac7e6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958847567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.958847567
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.592128043
Short name T197
Test name
Test status
Simulation time 379377897 ps
CPU time 2.17 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 197192 kb
Host smart-27a63933-4a73-440f-ab4a-c6bf2f9608a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592128043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.592128043
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3719993256
Short name T208
Test name
Test status
Simulation time 28287446 ps
CPU time 0.64 seconds
Started Apr 15 12:32:10 PM PDT 24
Finished Apr 15 12:32:11 PM PDT 24
Peak memory 194296 kb
Host smart-46d7826a-7d74-477a-ad1b-e9176eb3268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719993256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3719993256
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3168337699
Short name T646
Test name
Test status
Simulation time 234195295 ps
CPU time 1.21 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196964 kb
Host smart-da895f4c-a49d-494c-9679-7bdcbc75dd7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168337699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3168337699
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3952144566
Short name T547
Test name
Test status
Simulation time 99958615 ps
CPU time 1.85 seconds
Started Apr 15 12:32:39 PM PDT 24
Finished Apr 15 12:32:41 PM PDT 24
Peak memory 198128 kb
Host smart-abf6b12e-9651-4427-be65-c06fd3c2c03d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952144566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3952144566
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.328602944
Short name T681
Test name
Test status
Simulation time 131577804 ps
CPU time 0.92 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196320 kb
Host smart-5bf1d8f4-2aac-4080-86fc-14d0b28e4e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328602944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.328602944
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2959950276
Short name T638
Test name
Test status
Simulation time 330484144 ps
CPU time 1.08 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 195704 kb
Host smart-8e152b2b-55d7-4a0b-9101-ab5060e06fb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959950276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2959950276
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.104622067
Short name T338
Test name
Test status
Simulation time 10689354187 ps
CPU time 26.49 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:47 PM PDT 24
Peak memory 198268 kb
Host smart-87891c2f-9c0a-4505-90af-fa89c0362a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104622067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.104622067
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.57472952
Short name T353
Test name
Test status
Simulation time 12515600 ps
CPU time 0.65 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 194580 kb
Host smart-c21a3227-7ff5-4071-baaa-d64ab788ef83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57472952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.57472952
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2635443859
Short name T569
Test name
Test status
Simulation time 28256555 ps
CPU time 0.85 seconds
Started Apr 15 12:32:14 PM PDT 24
Finished Apr 15 12:32:15 PM PDT 24
Peak memory 197160 kb
Host smart-4df2fd15-d339-469a-a199-c0ecbc76c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635443859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2635443859
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1681393209
Short name T620
Test name
Test status
Simulation time 1644733075 ps
CPU time 20.16 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:38 PM PDT 24
Peak memory 196900 kb
Host smart-90458465-542d-4b48-81de-062e7badb513
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681393209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1681393209
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.905184835
Short name T264
Test name
Test status
Simulation time 62746294 ps
CPU time 0.88 seconds
Started Apr 15 12:33:27 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 196852 kb
Host smart-fe958cb1-9b75-40cd-ae3e-acf35fe055b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905184835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.905184835
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2229069429
Short name T601
Test name
Test status
Simulation time 357044813 ps
CPU time 1.3 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 197060 kb
Host smart-2af1e12c-9467-48a2-b806-3d554cb33763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229069429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2229069429
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3930646525
Short name T178
Test name
Test status
Simulation time 853419251 ps
CPU time 2.92 seconds
Started Apr 15 12:33:26 PM PDT 24
Finished Apr 15 12:33:30 PM PDT 24
Peak memory 196684 kb
Host smart-efff7e65-52ac-492a-bc53-0366f0a3b046
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930646525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3930646525
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1829224075
Short name T221
Test name
Test status
Simulation time 470607657 ps
CPU time 2.55 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 197296 kb
Host smart-d3c34ad4-bc72-4597-bb6a-bfb42b308122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829224075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1829224075
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1078594084
Short name T407
Test name
Test status
Simulation time 79726600 ps
CPU time 0.73 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:29 PM PDT 24
Peak memory 195384 kb
Host smart-a31fceeb-9b4f-4dd2-9581-2be5f962c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078594084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1078594084
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3052820468
Short name T517
Test name
Test status
Simulation time 18091937 ps
CPU time 0.79 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 196432 kb
Host smart-5c1a7214-e5da-4890-8c54-7cae2d7d0814
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052820468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3052820468
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1073688091
Short name T425
Test name
Test status
Simulation time 277793640 ps
CPU time 3.49 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 198096 kb
Host smart-c5bfce1b-d7de-42ef-823c-eb6724f4b125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073688091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1073688091
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.394301039
Short name T129
Test name
Test status
Simulation time 216641833 ps
CPU time 1.38 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 196820 kb
Host smart-eebf1df2-dd3b-4109-a33f-1dfd5358c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394301039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.394301039
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1006479226
Short name T702
Test name
Test status
Simulation time 161053891 ps
CPU time 0.99 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 196644 kb
Host smart-8a697fdd-e58e-4ece-b492-04fcca87746c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006479226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1006479226
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1161534924
Short name T684
Test name
Test status
Simulation time 40124884208 ps
CPU time 89.12 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:33:53 PM PDT 24
Peak memory 198188 kb
Host smart-bd1e3d1c-03b4-4f44-bc6e-dfbc87be551c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161534924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1161534924
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2577429597
Short name T278
Test name
Test status
Simulation time 31723489 ps
CPU time 0.56 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 193924 kb
Host smart-fd2a33b8-9dc8-43fe-8a64-f6b912c93071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577429597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2577429597
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3981878764
Short name T203
Test name
Test status
Simulation time 18425099 ps
CPU time 0.76 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 194764 kb
Host smart-b80bbda9-1ea7-4a3d-a9f5-95af41beba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981878764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3981878764
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.4286170801
Short name T297
Test name
Test status
Simulation time 225937378 ps
CPU time 11.94 seconds
Started Apr 15 12:32:13 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 198040 kb
Host smart-e42c4070-170c-40bc-a416-af026b3a0dbf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286170801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.4286170801
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1201130383
Short name T544
Test name
Test status
Simulation time 104147258 ps
CPU time 0.63 seconds
Started Apr 15 12:33:27 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 194384 kb
Host smart-63baa679-b982-4786-adaf-913691ca8dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201130383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1201130383
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.696913736
Short name T546
Test name
Test status
Simulation time 33948403 ps
CPU time 0.81 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195348 kb
Host smart-54b4b188-1d25-493a-b805-739d9d2ca3c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696913736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.696913736
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3148385916
Short name T482
Test name
Test status
Simulation time 126191501 ps
CPU time 2.84 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 198176 kb
Host smart-0c17915d-154a-4582-b44d-71d61857ab5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148385916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3148385916
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1933055793
Short name T464
Test name
Test status
Simulation time 61412873 ps
CPU time 1.41 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 196596 kb
Host smart-aa27a917-f161-4bc2-9a54-3a11190d7926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933055793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1933055793
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2589360801
Short name T443
Test name
Test status
Simulation time 225276268 ps
CPU time 1.25 seconds
Started Apr 15 12:32:26 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 196904 kb
Host smart-450768a8-d494-4ebb-be3b-5bb25da5d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589360801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2589360801
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3564081142
Short name T222
Test name
Test status
Simulation time 95002784 ps
CPU time 0.92 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 196144 kb
Host smart-73033ee0-00c4-4405-9d36-c5f42d8e8bbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564081142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3564081142
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.944604690
Short name T558
Test name
Test status
Simulation time 1101813134 ps
CPU time 3.08 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 198160 kb
Host smart-0f770afd-c6a0-4925-87d4-0e0cbf71e518
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944604690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.944604690
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1336740921
Short name T122
Test name
Test status
Simulation time 194536069 ps
CPU time 1.1 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 195884 kb
Host smart-554c60e0-0d07-4c30-90fd-dbbed59a8e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336740921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1336740921
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3030243677
Short name T474
Test name
Test status
Simulation time 170853812 ps
CPU time 0.88 seconds
Started Apr 15 12:32:23 PM PDT 24
Finished Apr 15 12:32:25 PM PDT 24
Peak memory 195232 kb
Host smart-6a881b8a-05de-4eb8-8394-cfb71e9a2b33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030243677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3030243677
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1389191509
Short name T335
Test name
Test status
Simulation time 12199802709 ps
CPU time 105.43 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:34:08 PM PDT 24
Peak memory 197996 kb
Host smart-e51f01d8-ddaf-4abf-a656-d18053be8c6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389191509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1389191509
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3812040345
Short name T429
Test name
Test status
Simulation time 13142059 ps
CPU time 0.58 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 193888 kb
Host smart-6f5bbbb6-bd42-4f35-8d2b-2605333f43be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812040345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3812040345
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1669599833
Short name T286
Test name
Test status
Simulation time 149899317 ps
CPU time 0.82 seconds
Started Apr 15 12:32:20 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195504 kb
Host smart-d852b1e9-b9e6-44e0-96e2-d6aacc20dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669599833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1669599833
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.779697177
Short name T14
Test name
Test status
Simulation time 1843831799 ps
CPU time 24.59 seconds
Started Apr 15 12:32:47 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 197988 kb
Host smart-379183dc-41b0-4ca4-b362-93bca58aa1d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779697177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.779697177
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1655582901
Short name T21
Test name
Test status
Simulation time 463659060 ps
CPU time 1.05 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 196452 kb
Host smart-9fbbc1d1-753f-45df-bd0a-042ff2570df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655582901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1655582901
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.803734578
Short name T105
Test name
Test status
Simulation time 128490086 ps
CPU time 1.33 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 197196 kb
Host smart-aa8eab0c-eb8e-4213-bef4-090b93cf1aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803734578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.803734578
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1047826817
Short name T170
Test name
Test status
Simulation time 236226299 ps
CPU time 2.81 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 198132 kb
Host smart-ad41c24c-fbf2-4a04-a0e8-74337ee86af2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047826817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1047826817
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2805086726
Short name T298
Test name
Test status
Simulation time 262424522 ps
CPU time 3.45 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:32:19 PM PDT 24
Peak memory 195864 kb
Host smart-5ff8be00-be44-4f73-8fa3-26820cc322d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805086726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2805086726
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.391396827
Short name T109
Test name
Test status
Simulation time 121475723 ps
CPU time 0.76 seconds
Started Apr 15 12:32:31 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 195584 kb
Host smart-a8e4380e-2815-413e-b32d-13ef7388880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391396827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.391396827
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.214503275
Short name T649
Test name
Test status
Simulation time 53337578 ps
CPU time 1.17 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:20 PM PDT 24
Peak memory 196980 kb
Host smart-f51b0459-ca60-4607-be0a-a1f942d4cbd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214503275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.214503275
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3702932819
Short name T674
Test name
Test status
Simulation time 373580704 ps
CPU time 4.57 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 198028 kb
Host smart-1b6c813e-2ebe-437d-ace3-4b7c2523c15c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702932819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3702932819
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3101862299
Short name T585
Test name
Test status
Simulation time 213749122 ps
CPU time 1.03 seconds
Started Apr 15 12:32:32 PM PDT 24
Finished Apr 15 12:32:33 PM PDT 24
Peak memory 195796 kb
Host smart-ad91409e-ae1c-415f-b502-56b6c421b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101862299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3101862299
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.902264551
Short name T692
Test name
Test status
Simulation time 610801470 ps
CPU time 0.93 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196516 kb
Host smart-9d5eda44-3c17-4ef5-8151-2b896ea6e454
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902264551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.902264551
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2108198498
Short name T5
Test name
Test status
Simulation time 21972494903 ps
CPU time 226.8 seconds
Started Apr 15 12:32:16 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 198188 kb
Host smart-f3c76c88-9e83-41ee-9a41-132bd942eec5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108198498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2108198498
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1661002072
Short name T66
Test name
Test status
Simulation time 88354737677 ps
CPU time 1416.87 seconds
Started Apr 15 12:32:15 PM PDT 24
Finished Apr 15 12:55:53 PM PDT 24
Peak memory 198240 kb
Host smart-0c8c1505-7b74-4831-add3-988dc99928f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1661002072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1661002072
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1793283503
Short name T106
Test name
Test status
Simulation time 12434207 ps
CPU time 0.58 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:26 PM PDT 24
Peak memory 194728 kb
Host smart-681a4452-5810-492c-9522-7f79e0c0a467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793283503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1793283503
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1063926569
Short name T688
Test name
Test status
Simulation time 16162691 ps
CPU time 0.64 seconds
Started Apr 15 12:32:17 PM PDT 24
Finished Apr 15 12:32:18 PM PDT 24
Peak memory 194148 kb
Host smart-fac685ea-2524-4aec-a028-47d408d3dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063926569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1063926569
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.4018661830
Short name T672
Test name
Test status
Simulation time 574899850 ps
CPU time 7.68 seconds
Started Apr 15 12:32:22 PM PDT 24
Finished Apr 15 12:32:32 PM PDT 24
Peak memory 195544 kb
Host smart-c99c3390-ebac-4c9c-bb83-080d8bbadc9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018661830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.4018661830
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2027063053
Short name T432
Test name
Test status
Simulation time 278712775 ps
CPU time 0.96 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:22 PM PDT 24
Peak memory 196712 kb
Host smart-52a27535-2375-42b2-8458-48e90ffab9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027063053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2027063053
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1977123766
Short name T441
Test name
Test status
Simulation time 179111988 ps
CPU time 1.46 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 198060 kb
Host smart-d6459bc6-3c1f-4191-a76c-a60e846e98a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977123766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1977123766
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4122903571
Short name T193
Test name
Test status
Simulation time 83123243 ps
CPU time 3.1 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 198300 kb
Host smart-f4cb85a0-5417-4a8f-8704-f592bc57f246
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122903571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4122903571
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.46365120
Short name T561
Test name
Test status
Simulation time 79942259 ps
CPU time 1.68 seconds
Started Apr 15 12:32:19 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 196000 kb
Host smart-4e6714fb-0c11-439b-b762-5665eebebb7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46365120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.46365120
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3821105538
Short name T326
Test name
Test status
Simulation time 31808163 ps
CPU time 0.74 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195444 kb
Host smart-3ebdcd7e-f772-4498-90f0-4b8875912e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821105538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3821105538
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.672251729
Short name T408
Test name
Test status
Simulation time 71965181 ps
CPU time 0.96 seconds
Started Apr 15 12:32:24 PM PDT 24
Finished Apr 15 12:32:27 PM PDT 24
Peak memory 196056 kb
Host smart-8e6e02e8-fc03-4e22-95f5-ee1cfc88430f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672251729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.672251729
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2789933360
Short name T687
Test name
Test status
Simulation time 787645998 ps
CPU time 4.41 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:28 PM PDT 24
Peak memory 198052 kb
Host smart-1ed5fcc1-4dac-47d7-8b81-abf608e9dfb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789933360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2789933360
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4082746992
Short name T607
Test name
Test status
Simulation time 212963891 ps
CPU time 1.17 seconds
Started Apr 15 12:32:21 PM PDT 24
Finished Apr 15 12:32:24 PM PDT 24
Peak memory 195716 kb
Host smart-9b9eb18e-3c15-4714-8abe-7b858ec2dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082746992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4082746992
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.561550905
Short name T125
Test name
Test status
Simulation time 205970036 ps
CPU time 0.93 seconds
Started Apr 15 12:32:18 PM PDT 24
Finished Apr 15 12:32:21 PM PDT 24
Peak memory 196504 kb
Host smart-38edd634-41a7-494d-b666-92013505c66d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561550905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.561550905
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.574924300
Short name T52
Test name
Test status
Simulation time 9852732796 ps
CPU time 132.84 seconds
Started Apr 15 12:33:25 PM PDT 24
Finished Apr 15 12:35:44 PM PDT 24
Peak memory 197396 kb
Host smart-61c6e9c9-0cf8-427c-b5be-0765178f4507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574924300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.574924300
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3379563372
Short name T871
Test name
Test status
Simulation time 278429402 ps
CPU time 1.16 seconds
Started Apr 15 12:18:57 PM PDT 24
Finished Apr 15 12:18:59 PM PDT 24
Peak memory 190032 kb
Host smart-a9fdbfc1-a8e0-4d5f-98bd-6c9192183c31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3379563372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3379563372
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3399305035
Short name T937
Test name
Test status
Simulation time 42422695 ps
CPU time 1.22 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:10 PM PDT 24
Peak memory 191124 kb
Host smart-377dc008-5823-4788-a67c-94ac9203ae36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399305035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3399305035
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2624625776
Short name T861
Test name
Test status
Simulation time 342337716 ps
CPU time 1.3 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 191328 kb
Host smart-22585a62-ee16-4383-ab1d-8b2bfc07e7ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2624625776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2624625776
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1953389420
Short name T926
Test name
Test status
Simulation time 22862218 ps
CPU time 0.79 seconds
Started Apr 15 12:19:08 PM PDT 24
Finished Apr 15 12:19:10 PM PDT 24
Peak memory 194776 kb
Host smart-a216bc01-10ce-4705-996e-41e7324d1e37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953389420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1953389420
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1959735614
Short name T932
Test name
Test status
Simulation time 234866396 ps
CPU time 1.12 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 191136 kb
Host smart-c78a601f-6d87-466c-a669-789c144c18fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1959735614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1959735614
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3622772287
Short name T900
Test name
Test status
Simulation time 35385547 ps
CPU time 0.84 seconds
Started Apr 15 12:18:58 PM PDT 24
Finished Apr 15 12:19:00 PM PDT 24
Peak memory 195712 kb
Host smart-69be87a0-3689-4933-83ac-23b74d3a63ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622772287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3622772287
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.338736815
Short name T868
Test name
Test status
Simulation time 113933200 ps
CPU time 1.17 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 191384 kb
Host smart-7b2b0c93-ac30-4ddc-8833-50eba1d8bd3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=338736815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.338736815
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2548300728
Short name T919
Test name
Test status
Simulation time 664144680 ps
CPU time 0.99 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 191372 kb
Host smart-aca242c1-5dcb-435b-93e7-e8c0fe8664ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548300728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2548300728
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2659217112
Short name T854
Test name
Test status
Simulation time 699054748 ps
CPU time 1.18 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 197496 kb
Host smart-1b1f0c4e-1427-4e08-9402-568431d3cbd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2659217112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2659217112
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2577430017
Short name T894
Test name
Test status
Simulation time 90846718 ps
CPU time 1.25 seconds
Started Apr 15 12:18:12 PM PDT 24
Finished Apr 15 12:18:14 PM PDT 24
Peak memory 197388 kb
Host smart-6f8ca1cf-a634-4946-8faa-1adbb69f0c94
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577430017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2577430017
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3763713665
Short name T892
Test name
Test status
Simulation time 444298600 ps
CPU time 1.21 seconds
Started Apr 15 12:19:08 PM PDT 24
Finished Apr 15 12:19:10 PM PDT 24
Peak memory 191060 kb
Host smart-af6d98e2-3ffa-429d-b96e-3ea4d9d88e81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3763713665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3763713665
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.89371335
Short name T897
Test name
Test status
Simulation time 138389489 ps
CPU time 1.19 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 197652 kb
Host smart-07928fb9-f847-490a-8a1d-99a83372028a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89371335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.89371335
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2300548021
Short name T843
Test name
Test status
Simulation time 150601240 ps
CPU time 1.13 seconds
Started Apr 15 12:18:48 PM PDT 24
Finished Apr 15 12:18:50 PM PDT 24
Peak memory 190984 kb
Host smart-f4376783-2f54-427a-9cfb-52cada919874
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2300548021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2300548021
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680566294
Short name T917
Test name
Test status
Simulation time 56148984 ps
CPU time 0.98 seconds
Started Apr 15 12:18:59 PM PDT 24
Finished Apr 15 12:19:00 PM PDT 24
Peak memory 197396 kb
Host smart-83fe17b2-08eb-42ba-ae59-c90ff156e764
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680566294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3680566294
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3435210443
Short name T935
Test name
Test status
Simulation time 519534110 ps
CPU time 0.84 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 195900 kb
Host smart-82bcceb7-229c-46e1-b899-8f1aff0219d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3435210443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3435210443
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587843553
Short name T921
Test name
Test status
Simulation time 94893404 ps
CPU time 1.42 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 190028 kb
Host smart-64c2f356-a60d-4bc7-b37a-31a5b4eeee03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587843553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3587843553
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1638111422
Short name T886
Test name
Test status
Simulation time 86929448 ps
CPU time 1.37 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 191356 kb
Host smart-a187d38e-df20-40b9-99df-cac2c2283c28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1638111422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1638111422
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2616966828
Short name T925
Test name
Test status
Simulation time 43301277 ps
CPU time 0.93 seconds
Started Apr 15 12:17:03 PM PDT 24
Finished Apr 15 12:17:04 PM PDT 24
Peak memory 195680 kb
Host smart-7d726742-0ccc-4f8a-80bc-8d4a7ecfe1d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616966828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2616966828
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.971451734
Short name T901
Test name
Test status
Simulation time 114382971 ps
CPU time 1.19 seconds
Started Apr 15 12:18:48 PM PDT 24
Finished Apr 15 12:18:50 PM PDT 24
Peak memory 190152 kb
Host smart-83769e0c-9700-4163-8fc6-19feff0afb85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=971451734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.971451734
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.486274389
Short name T875
Test name
Test status
Simulation time 25435040 ps
CPU time 0.87 seconds
Started Apr 15 12:18:58 PM PDT 24
Finished Apr 15 12:18:59 PM PDT 24
Peak memory 191072 kb
Host smart-f4a1c4b3-f30d-4524-990f-2bd0f37be893
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486274389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.486274389
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2350032705
Short name T878
Test name
Test status
Simulation time 465748047 ps
CPU time 1.25 seconds
Started Apr 15 12:19:08 PM PDT 24
Finished Apr 15 12:19:10 PM PDT 24
Peak memory 196792 kb
Host smart-a785c451-ec66-4ac2-8c4a-0e20b0228c1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2350032705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2350032705
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2044839338
Short name T939
Test name
Test status
Simulation time 22199785 ps
CPU time 0.66 seconds
Started Apr 15 12:18:49 PM PDT 24
Finished Apr 15 12:18:50 PM PDT 24
Peak memory 190936 kb
Host smart-a3f5f27f-bbd7-4d69-981c-be6b5e4f0b4e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044839338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2044839338
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3728991575
Short name T920
Test name
Test status
Simulation time 44226396 ps
CPU time 0.98 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 195940 kb
Host smart-9ee0fc0b-010d-4653-8f55-41390428a65e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3728991575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3728991575
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463169252
Short name T857
Test name
Test status
Simulation time 78929184 ps
CPU time 1.12 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:10 PM PDT 24
Peak memory 197636 kb
Host smart-29763300-9508-4df5-836c-096cf1f1142e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463169252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3463169252
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3574710327
Short name T905
Test name
Test status
Simulation time 308289149 ps
CPU time 1.29 seconds
Started Apr 15 12:19:07 PM PDT 24
Finished Apr 15 12:19:09 PM PDT 24
Peak memory 190244 kb
Host smart-fb71df65-2273-47d5-8270-76f7cab7402c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3574710327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3574710327
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2502966933
Short name T881
Test name
Test status
Simulation time 89233576 ps
CPU time 1.04 seconds
Started Apr 15 12:17:11 PM PDT 24
Finished Apr 15 12:17:12 PM PDT 24
Peak memory 191388 kb
Host smart-baa7c069-4169-469c-85b0-b04fc2b45107
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502966933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2502966933
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1699634139
Short name T872
Test name
Test status
Simulation time 301600562 ps
CPU time 1.49 seconds
Started Apr 15 12:17:22 PM PDT 24
Finished Apr 15 12:17:24 PM PDT 24
Peak memory 191368 kb
Host smart-4969c46b-e0fd-490d-bbd0-f1b4b111e181
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1699634139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1699634139
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2903646207
Short name T927
Test name
Test status
Simulation time 53795951 ps
CPU time 0.91 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 189932 kb
Host smart-0394f59a-a976-43ac-a5e8-f1176c3a173c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903646207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2903646207
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4185102883
Short name T914
Test name
Test status
Simulation time 77738301 ps
CPU time 1.16 seconds
Started Apr 15 12:19:07 PM PDT 24
Finished Apr 15 12:19:09 PM PDT 24
Peak memory 190596 kb
Host smart-c1e6de84-f852-415f-a224-cc8aa14cac53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185102883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4185102883
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.924776563
Short name T907
Test name
Test status
Simulation time 34003539 ps
CPU time 0.81 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 191044 kb
Host smart-29be81b5-ff04-450a-8e61-a4c42e4198bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924776563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.924776563
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1579082762
Short name T866
Test name
Test status
Simulation time 49455253 ps
CPU time 0.87 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 191308 kb
Host smart-a5e4f9ae-8f97-418e-91a0-795e0dd09ec9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1579082762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1579082762
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1946235679
Short name T847
Test name
Test status
Simulation time 84904586 ps
CPU time 1.34 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 197580 kb
Host smart-adabff6d-202c-4cea-ab7d-47a198d542eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946235679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1946235679
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1475265622
Short name T938
Test name
Test status
Simulation time 51022085 ps
CPU time 0.78 seconds
Started Apr 15 12:19:19 PM PDT 24
Finished Apr 15 12:19:21 PM PDT 24
Peak memory 190312 kb
Host smart-f48bd3d0-4d29-4747-aa15-8b1bd49c57f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1475265622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1475265622
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3665503242
Short name T898
Test name
Test status
Simulation time 45497349 ps
CPU time 0.97 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 189896 kb
Host smart-7e722758-38ab-4c42-973c-5f2fc891442c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665503242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3665503242
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1692637799
Short name T934
Test name
Test status
Simulation time 40485685 ps
CPU time 1.07 seconds
Started Apr 15 12:19:13 PM PDT 24
Finished Apr 15 12:19:15 PM PDT 24
Peak memory 197472 kb
Host smart-320d450b-13a8-4a7f-b746-c12326b69ff5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1692637799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1692637799
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3147484125
Short name T877
Test name
Test status
Simulation time 130440451 ps
CPU time 0.79 seconds
Started Apr 15 12:18:25 PM PDT 24
Finished Apr 15 12:18:27 PM PDT 24
Peak memory 191208 kb
Host smart-14b9437a-807c-425e-915f-e6be05d3cee5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147484125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3147484125
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1294110982
Short name T889
Test name
Test status
Simulation time 37414684 ps
CPU time 1.11 seconds
Started Apr 15 12:18:48 PM PDT 24
Finished Apr 15 12:18:50 PM PDT 24
Peak memory 196432 kb
Host smart-bdcd6732-1cfa-4b4e-9d62-0543ac2dfad1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1294110982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1294110982
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2263591181
Short name T874
Test name
Test status
Simulation time 169648950 ps
CPU time 1.28 seconds
Started Apr 15 12:18:57 PM PDT 24
Finished Apr 15 12:18:59 PM PDT 24
Peak memory 190244 kb
Host smart-991c371e-4e61-414e-885c-e2321c63822b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263591181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2263591181
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1169433021
Short name T873
Test name
Test status
Simulation time 237054865 ps
CPU time 1.13 seconds
Started Apr 15 12:19:07 PM PDT 24
Finished Apr 15 12:19:09 PM PDT 24
Peak memory 195676 kb
Host smart-a2cbc737-df81-495d-8348-6a674f02ab23
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1169433021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1169433021
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.188077038
Short name T909
Test name
Test status
Simulation time 40660150 ps
CPU time 0.9 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 189860 kb
Host smart-18d61ff6-a69a-4bfe-8b1e-d41806f30194
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188077038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.188077038
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.4154869488
Short name T876
Test name
Test status
Simulation time 218296248 ps
CPU time 1.24 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 191244 kb
Host smart-8f86b8ca-10c0-46eb-a286-048788b75ea9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4154869488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.4154869488
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232240542
Short name T859
Test name
Test status
Simulation time 133887972 ps
CPU time 1.15 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:12 PM PDT 24
Peak memory 191404 kb
Host smart-d9a211ee-23b2-4296-b04c-ad70dde5904e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232240542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4232240542
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3901180020
Short name T899
Test name
Test status
Simulation time 43511483 ps
CPU time 0.89 seconds
Started Apr 15 12:19:31 PM PDT 24
Finished Apr 15 12:19:32 PM PDT 24
Peak memory 190364 kb
Host smart-a4c6129d-d584-4906-8e71-25658391f403
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3901180020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3901180020
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243738869
Short name T865
Test name
Test status
Simulation time 76352305 ps
CPU time 1.01 seconds
Started Apr 15 12:19:08 PM PDT 24
Finished Apr 15 12:19:09 PM PDT 24
Peak memory 196828 kb
Host smart-357403ab-9c47-4696-a46b-8a02301f9944
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243738869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1243738869
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4284218935
Short name T890
Test name
Test status
Simulation time 78247244 ps
CPU time 1.12 seconds
Started Apr 15 12:17:41 PM PDT 24
Finished Apr 15 12:17:42 PM PDT 24
Peak memory 191392 kb
Host smart-733bcad5-4d87-422f-baa6-c2de7deb8508
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4284218935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4284218935
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3098835413
Short name T862
Test name
Test status
Simulation time 118089700 ps
CPU time 0.84 seconds
Started Apr 15 12:19:30 PM PDT 24
Finished Apr 15 12:19:32 PM PDT 24
Peak memory 189900 kb
Host smart-47154208-ef4d-43d1-b773-8c534be41f96
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098835413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3098835413
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2923150280
Short name T842
Test name
Test status
Simulation time 265653304 ps
CPU time 1.06 seconds
Started Apr 15 12:19:06 PM PDT 24
Finished Apr 15 12:19:08 PM PDT 24
Peak memory 191116 kb
Host smart-610cafb3-a096-4ded-a0e0-e27e30cc5dae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2923150280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2923150280
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3048953344
Short name T906
Test name
Test status
Simulation time 104145998 ps
CPU time 1.51 seconds
Started Apr 15 12:19:09 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 191068 kb
Host smart-62917d4d-f194-4d04-93e7-7281bb2185b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048953344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3048953344
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1561814010
Short name T860
Test name
Test status
Simulation time 146533013 ps
CPU time 0.93 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 191168 kb
Host smart-76f8605a-b026-43f1-96f0-f52b6450716f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1561814010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1561814010
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.213491574
Short name T908
Test name
Test status
Simulation time 100812787 ps
CPU time 0.75 seconds
Started Apr 15 12:18:57 PM PDT 24
Finished Apr 15 12:18:59 PM PDT 24
Peak memory 190012 kb
Host smart-7ed2c438-7314-4690-96f9-c9bf70d8a061
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213491574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.213491574
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1326682584
Short name T867
Test name
Test status
Simulation time 344313555 ps
CPU time 1.37 seconds
Started Apr 15 12:18:59 PM PDT 24
Finished Apr 15 12:19:01 PM PDT 24
Peak memory 197496 kb
Host smart-d9f06f44-84d6-4ab2-90d8-c3217f2ca685
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1326682584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1326682584
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1515341522
Short name T856
Test name
Test status
Simulation time 93418400 ps
CPU time 1.2 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191032 kb
Host smart-ee8ca164-42ea-4578-b148-8a23942c27fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515341522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1515341522
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2509724637
Short name T863
Test name
Test status
Simulation time 95444307 ps
CPU time 1.05 seconds
Started Apr 15 12:18:51 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 190604 kb
Host smart-ec14b1db-bca3-4439-bdb8-f66afb2d73b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2509724637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2509724637
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.660558385
Short name T869
Test name
Test status
Simulation time 31503248 ps
CPU time 0.79 seconds
Started Apr 15 12:19:44 PM PDT 24
Finished Apr 15 12:19:47 PM PDT 24
Peak memory 191104 kb
Host smart-05f80fb7-dff4-4ec0-a4fa-d60015390e1f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660558385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.660558385
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2491656180
Short name T888
Test name
Test status
Simulation time 198867749 ps
CPU time 1.5 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 189876 kb
Host smart-e0b94223-0365-4eb6-964d-16047d3a4b2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2491656180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2491656180
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2783749458
Short name T885
Test name
Test status
Simulation time 174722573 ps
CPU time 0.75 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:11 PM PDT 24
Peak memory 191280 kb
Host smart-219afe45-f50e-4976-9d11-4d751f07cfa2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783749458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2783749458
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.600382159
Short name T887
Test name
Test status
Simulation time 147426759 ps
CPU time 0.92 seconds
Started Apr 15 12:19:43 PM PDT 24
Finished Apr 15 12:19:45 PM PDT 24
Peak memory 196764 kb
Host smart-2f6c3882-9dfc-44fa-aae1-a51ffb64102c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=600382159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.600382159
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1812209196
Short name T940
Test name
Test status
Simulation time 67457664 ps
CPU time 1.12 seconds
Started Apr 15 12:17:03 PM PDT 24
Finished Apr 15 12:17:04 PM PDT 24
Peak memory 191312 kb
Host smart-c0a407a3-95b8-4cd2-bc8b-83f963db4823
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812209196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1812209196
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1299657181
Short name T884
Test name
Test status
Simulation time 53656301 ps
CPU time 1.01 seconds
Started Apr 15 12:19:43 PM PDT 24
Finished Apr 15 12:19:45 PM PDT 24
Peak memory 191088 kb
Host smart-54fdec1e-a48a-42ff-9e5c-9aa112fbe7d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1299657181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1299657181
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.393017082
Short name T913
Test name
Test status
Simulation time 127643597 ps
CPU time 0.91 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:14 PM PDT 24
Peak memory 191028 kb
Host smart-c0fd6593-6f2a-4d55-ae5f-07ea19fd5f53
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393017082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.393017082
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1452925510
Short name T895
Test name
Test status
Simulation time 59820469 ps
CPU time 1.11 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:14 PM PDT 24
Peak memory 197432 kb
Host smart-2d47e180-8341-4592-9440-1e5e96dd422c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1452925510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1452925510
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3632993065
Short name T846
Test name
Test status
Simulation time 20934872 ps
CPU time 0.8 seconds
Started Apr 15 12:19:44 PM PDT 24
Finished Apr 15 12:19:47 PM PDT 24
Peak memory 195772 kb
Host smart-7fc0dc6b-4057-4474-b2fb-66703e397458
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632993065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3632993065
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2297036786
Short name T879
Test name
Test status
Simulation time 106381809 ps
CPU time 0.99 seconds
Started Apr 15 12:18:50 PM PDT 24
Finished Apr 15 12:18:52 PM PDT 24
Peak memory 194896 kb
Host smart-226e8c27-6357-4ced-a450-8899a86c5652
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2297036786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2297036786
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605370635
Short name T915
Test name
Test status
Simulation time 83623866 ps
CPU time 0.9 seconds
Started Apr 15 12:19:44 PM PDT 24
Finished Apr 15 12:19:46 PM PDT 24
Peak memory 191100 kb
Host smart-6f96a027-bc6d-4193-b7a8-385badf841c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605370635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3605370635
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2885370616
Short name T933
Test name
Test status
Simulation time 209502564 ps
CPU time 1.16 seconds
Started Apr 15 12:18:51 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 195816 kb
Host smart-5b3abe2a-2790-4ee3-a956-2e60c1071aed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2885370616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2885370616
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.509792144
Short name T852
Test name
Test status
Simulation time 149974059 ps
CPU time 1.28 seconds
Started Apr 15 12:18:50 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 190216 kb
Host smart-b96ab0f6-2815-4deb-9541-cdcdffe8d759
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509792144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.509792144
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2471587362
Short name T922
Test name
Test status
Simulation time 399568186 ps
CPU time 1.21 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191364 kb
Host smart-44c531bd-de6d-45ff-85c5-85e60ac86f80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2471587362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2471587362
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430478366
Short name T848
Test name
Test status
Simulation time 259430800 ps
CPU time 1.07 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191360 kb
Host smart-471a8f43-2762-4af4-a9ee-9426d32f1cfa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430478366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3430478366
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.215252620
Short name T904
Test name
Test status
Simulation time 63150803 ps
CPU time 1.34 seconds
Started Apr 15 12:19:32 PM PDT 24
Finished Apr 15 12:19:34 PM PDT 24
Peak memory 191176 kb
Host smart-41c206ff-67f1-4465-bdae-99297d144143
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=215252620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.215252620
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037500581
Short name T923
Test name
Test status
Simulation time 51926376 ps
CPU time 1.08 seconds
Started Apr 15 12:19:30 PM PDT 24
Finished Apr 15 12:19:32 PM PDT 24
Peak memory 196372 kb
Host smart-07228828-8078-45ff-84f1-3df79e8129a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037500581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3037500581
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.146092049
Short name T910
Test name
Test status
Simulation time 101214223 ps
CPU time 0.98 seconds
Started Apr 15 12:19:10 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 189676 kb
Host smart-e5b80bfd-a87b-423d-9ad5-b8504ad39f60
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=146092049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.146092049
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1967279432
Short name T845
Test name
Test status
Simulation time 136904695 ps
CPU time 0.99 seconds
Started Apr 15 12:18:51 PM PDT 24
Finished Apr 15 12:18:53 PM PDT 24
Peak memory 191104 kb
Host smart-d86a7b0a-0def-44c0-8e95-82d410e51ec4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967279432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1967279432
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.505553983
Short name T912
Test name
Test status
Simulation time 62045190 ps
CPU time 0.91 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191312 kb
Host smart-15a96c66-7c7e-453a-821b-2fd6cdc05da5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=505553983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.505553983
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1426243435
Short name T864
Test name
Test status
Simulation time 136309558 ps
CPU time 0.96 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191308 kb
Host smart-4b0f6eff-7945-4bc5-83c6-efa737abca5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426243435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1426243435
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3495828021
Short name T893
Test name
Test status
Simulation time 215646961 ps
CPU time 0.99 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 191368 kb
Host smart-e30ef23e-2cea-4215-9804-d87b27729dbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3495828021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3495828021
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2292177286
Short name T924
Test name
Test status
Simulation time 46752312 ps
CPU time 1.16 seconds
Started Apr 15 12:18:55 PM PDT 24
Finished Apr 15 12:18:57 PM PDT 24
Peak memory 190872 kb
Host smart-c05c231c-79d2-40da-854b-5398ea3a24ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292177286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2292177286
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1949873756
Short name T916
Test name
Test status
Simulation time 44851466 ps
CPU time 1.16 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 196288 kb
Host smart-4e9cf2df-18a4-4f67-a99f-3831e953c0e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1949873756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1949873756
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744512061
Short name T883
Test name
Test status
Simulation time 78624906 ps
CPU time 0.87 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 194796 kb
Host smart-1d8fd599-9a98-407f-9a93-1a7f41fe87f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744512061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2744512061
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.158207448
Short name T931
Test name
Test status
Simulation time 93762700 ps
CPU time 1.1 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 189816 kb
Host smart-35b9f033-e3da-4c41-84a1-373154d14bfb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=158207448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.158207448
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983297759
Short name T936
Test name
Test status
Simulation time 188469181 ps
CPU time 1.16 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 190248 kb
Host smart-ad2ab02d-f24f-413d-a1cd-0cf74dd5b9a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983297759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.983297759
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2364656921
Short name T918
Test name
Test status
Simulation time 439274546 ps
CPU time 1.18 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:07 PM PDT 24
Peak memory 190936 kb
Host smart-4184bf64-6e6b-4cbe-b358-460722114a0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2364656921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2364656921
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466046610
Short name T858
Test name
Test status
Simulation time 108611813 ps
CPU time 0.77 seconds
Started Apr 15 12:19:11 PM PDT 24
Finished Apr 15 12:19:13 PM PDT 24
Peak memory 195640 kb
Host smart-65599caf-24ba-462d-8a12-b7d1f0a0f3f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466046610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2466046610
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.674898908
Short name T870
Test name
Test status
Simulation time 145670620 ps
CPU time 1.21 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:08 PM PDT 24
Peak memory 190924 kb
Host smart-8119d71d-d361-49b5-9fde-c84499263e50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=674898908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.674898908
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3966908724
Short name T855
Test name
Test status
Simulation time 72892606 ps
CPU time 1.16 seconds
Started Apr 15 12:19:05 PM PDT 24
Finished Apr 15 12:19:08 PM PDT 24
Peak memory 191128 kb
Host smart-0afae849-c8f4-4eaa-8942-365b30047027
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966908724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3966908724
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2042398736
Short name T880
Test name
Test status
Simulation time 319353567 ps
CPU time 1.08 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 191020 kb
Host smart-96327b16-50a8-4ba4-9b16-295051834c4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2042398736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2042398736
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2581083686
Short name T930
Test name
Test status
Simulation time 913389861 ps
CPU time 1.33 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 196064 kb
Host smart-d8f82009-d9b8-4606-a7f0-90738bcb3d21
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581083686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2581083686
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4182319779
Short name T841
Test name
Test status
Simulation time 31106504 ps
CPU time 0.82 seconds
Started Apr 15 12:17:02 PM PDT 24
Finished Apr 15 12:17:03 PM PDT 24
Peak memory 190996 kb
Host smart-c7fa0803-8cc7-47fc-bfe3-14a8891ac7a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4182319779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4182319779
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4087197554
Short name T853
Test name
Test status
Simulation time 71576067 ps
CPU time 1.19 seconds
Started Apr 15 12:19:04 PM PDT 24
Finished Apr 15 12:19:06 PM PDT 24
Peak memory 197340 kb
Host smart-cb3bc45d-6973-40e3-941b-a6c107e4e620
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087197554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4087197554
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1042794162
Short name T844
Test name
Test status
Simulation time 44946357 ps
CPU time 0.98 seconds
Started Apr 15 12:19:31 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 191120 kb
Host smart-297852f5-8467-4796-9e94-43ff391e06b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1042794162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1042794162
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223932561
Short name T928
Test name
Test status
Simulation time 49451132 ps
CPU time 1 seconds
Started Apr 15 12:19:45 PM PDT 24
Finished Apr 15 12:19:47 PM PDT 24
Peak memory 195840 kb
Host smart-fabad533-1480-46f2-9c08-8da4a8fa8f93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223932561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2223932561
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3203714979
Short name T882
Test name
Test status
Simulation time 157910195 ps
CPU time 1.36 seconds
Started Apr 15 12:19:44 PM PDT 24
Finished Apr 15 12:19:46 PM PDT 24
Peak memory 197560 kb
Host smart-c9cd4c32-5b30-44f4-a8e3-1f39985b3458
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3203714979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3203714979
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1779715340
Short name T896
Test name
Test status
Simulation time 158922188 ps
CPU time 0.84 seconds
Started Apr 15 12:19:12 PM PDT 24
Finished Apr 15 12:19:14 PM PDT 24
Peak memory 196792 kb
Host smart-2be01717-975c-4a93-b91c-7ec33eebb727
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779715340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1779715340
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1197086093
Short name T903
Test name
Test status
Simulation time 212401778 ps
CPU time 1.04 seconds
Started Apr 15 12:18:53 PM PDT 24
Finished Apr 15 12:18:55 PM PDT 24
Peak memory 190592 kb
Host smart-7dd77089-bb43-49e1-882b-4ce951d14b65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1197086093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1197086093
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1874852940
Short name T929
Test name
Test status
Simulation time 93074671 ps
CPU time 1.34 seconds
Started Apr 15 12:19:31 PM PDT 24
Finished Apr 15 12:19:33 PM PDT 24
Peak memory 191128 kb
Host smart-9f5369d2-35f8-49ff-923e-bdd721d17905
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874852940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1874852940
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3433090172
Short name T902
Test name
Test status
Simulation time 23638660 ps
CPU time 0.66 seconds
Started Apr 15 12:19:12 PM PDT 24
Finished Apr 15 12:19:14 PM PDT 24
Peak memory 191236 kb
Host smart-d60691a9-5327-4532-894d-2d403b804ac8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3433090172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3433090172
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.944596223
Short name T850
Test name
Test status
Simulation time 67968869 ps
CPU time 1.18 seconds
Started Apr 15 12:18:57 PM PDT 24
Finished Apr 15 12:18:59 PM PDT 24
Peak memory 190184 kb
Host smart-5a8efe03-025d-4a02-a839-b17be10fa919
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944596223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.944596223
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3525173245
Short name T891
Test name
Test status
Simulation time 29977776 ps
CPU time 1 seconds
Started Apr 15 12:19:01 PM PDT 24
Finished Apr 15 12:19:03 PM PDT 24
Peak memory 191272 kb
Host smart-affec65d-b924-4340-87c7-23cebd5e5604
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3525173245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3525173245
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.124035449
Short name T849
Test name
Test status
Simulation time 83238870 ps
CPU time 1.34 seconds
Started Apr 15 12:19:19 PM PDT 24
Finished Apr 15 12:19:21 PM PDT 24
Peak memory 197636 kb
Host smart-29f93421-be5f-4103-80e3-0367f2d98a1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124035449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.124035449
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2088508286
Short name T851
Test name
Test status
Simulation time 86945057 ps
CPU time 0.66 seconds
Started Apr 15 12:19:12 PM PDT 24
Finished Apr 15 12:19:14 PM PDT 24
Peak memory 191264 kb
Host smart-ec84bf74-e1fa-4c5e-9cc6-bfd1d1386b3f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088508286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2088508286
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833645593
Short name T911
Test name
Test status
Simulation time 68738406 ps
CPU time 1.1 seconds
Started Apr 15 12:19:15 PM PDT 24
Finished Apr 15 12:19:16 PM PDT 24
Peak memory 191140 kb
Host smart-dde6076e-a910-41ed-8e7e-14cac050595d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833645593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2833645593
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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