Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3352790	1			T23	10		T24	1		T25	1
all_pins[1]	3352790	1			T23	10		T24	1		T25	1
all_pins[2]	3352790	1			T23	10		T24	1		T25	1
all_pins[3]	3352790	1			T23	10		T24	1		T25	1
all_pins[4]	3352790	1			T23	10		T24	1		T25	1
all_pins[5]	3352790	1			T23	10		T24	1		T25	1
all_pins[6]	3352790	1			T23	10		T24	1		T25	1
all_pins[7]	3352790	1			T23	10		T24	1		T25	1
all_pins[8]	3352790	1			T23	10		T24	1		T25	1
all_pins[9]	3352790	1			T23	10		T24	1		T25	1
all_pins[10]	3352790	1			T23	10		T24	1		T25	1
all_pins[11]	3352790	1			T23	10		T24	1		T25	1
all_pins[12]	3352790	1			T23	10		T24	1		T25	1
all_pins[13]	3352790	1			T23	10		T24	1		T25	1
all_pins[14]	3352790	1			T23	10		T24	1		T25	1
all_pins[15]	3352790	1			T23	10		T24	1		T25	1
all_pins[16]	3352790	1			T23	10		T24	1		T25	1
all_pins[17]	3352790	1			T23	10		T24	1		T25	1
all_pins[18]	3352790	1			T23	10		T24	1		T25	1
all_pins[19]	3352790	1			T23	10		T24	1		T25	1
all_pins[20]	3352790	1			T23	10		T24	1		T25	1
all_pins[21]	3352790	1			T23	10		T24	1		T25	1
all_pins[22]	3352790	1			T23	10		T24	1		T25	1
all_pins[23]	3352790	1			T23	10		T24	1		T25	1
all_pins[24]	3352790	1			T23	10		T24	1		T25	1
all_pins[25]	3352790	1			T23	10		T24	1		T25	1
all_pins[26]	3352790	1			T23	10		T24	1		T25	1
all_pins[27]	3352790	1			T23	10		T24	1		T25	1
all_pins[28]	3352790	1			T23	10		T24	1		T25	1
all_pins[29]	3352790	1			T23	10		T24	1		T25	1
all_pins[30]	3352790	1			T23	10		T24	1		T25	1
all_pins[31]	3352790	1			T23	10		T24	1		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	66652675	1			T23	181		T24	32		T25	32
values[0x1]	40636605	1			T23	139		T29	274		T30	1000
transitions[0x0=>0x1]	24336814	1			T23	77		T29	164		T30	495
transitions[0x1=>0x0]	24336676	1			T23	76		T29	164		T30	495

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2080941	1			T23	7		T24	1		T25	1
all_pins[0]	values[0x1]	1271849	1			T23	3		T29	5		T30	26
all_pins[0]	transitions[0x0=>0x1]	787666	1			T23	2		T29	4		T30	10
all_pins[0]	transitions[0x1=>0x0]	780332	1			T23	3		T29	4		T30	22
all_pins[1]	values[0x0]	2077905	1			T23	5		T24	1		T25	1
all_pins[1]	values[0x1]	1274885	1			T23	5		T29	11		T30	29
all_pins[1]	transitions[0x0=>0x1]	762425	1			T23	4		T29	8		T30	14
all_pins[1]	transitions[0x1=>0x0]	759389	1			T23	2		T29	2		T30	11
all_pins[2]	values[0x0]	2077608	1			T23	7		T24	1		T25	1
all_pins[2]	values[0x1]	1275182	1			T23	3		T29	6		T30	36
all_pins[2]	transitions[0x0=>0x1]	761387	1			T23	3		T29	1		T30	22
all_pins[2]	transitions[0x1=>0x0]	761090	1			T23	5		T29	6		T30	15
all_pins[3]	values[0x0]	2076308	1			T23	3		T24	1		T25	1
all_pins[3]	values[0x1]	1276482	1			T23	7		T29	6		T30	31
all_pins[3]	transitions[0x0=>0x1]	761523	1			T23	6		T29	4		T30	13
all_pins[3]	transitions[0x1=>0x0]	760223	1			T23	2		T29	4		T30	18
all_pins[4]	values[0x0]	2081207	1			T23	6		T24	1		T25	1
all_pins[4]	values[0x1]	1271583	1			T23	4		T29	14		T30	32
all_pins[4]	transitions[0x0=>0x1]	756599	1			T23	1		T29	9		T30	15
all_pins[4]	transitions[0x1=>0x0]	761498	1			T23	4		T29	1		T30	14
all_pins[5]	values[0x0]	2083654	1			T23	7		T24	1		T25	1
all_pins[5]	values[0x1]	1269136	1			T23	3		T29	13		T30	35
all_pins[5]	transitions[0x0=>0x1]	759218	1			T23	2		T29	4		T30	17
all_pins[5]	transitions[0x1=>0x0]	761665	1			T23	3		T29	5		T30	14
all_pins[6]	values[0x0]	2084580	1			T23	6		T24	1		T25	1
all_pins[6]	values[0x1]	1268210	1			T23	4		T30	27		T44	2
all_pins[6]	transitions[0x0=>0x1]	760697	1			T23	2		T30	12		T44	2
all_pins[6]	transitions[0x1=>0x0]	761623	1			T23	1		T29	13		T30	20
all_pins[7]	values[0x0]	2079662	1			T23	9		T24	1		T25	1
all_pins[7]	values[0x1]	1273128	1			T23	1		T29	5		T30	29
all_pins[7]	transitions[0x0=>0x1]	764738	1			T23	1		T29	5		T30	17
all_pins[7]	transitions[0x1=>0x0]	759820	1			T23	4		T30	15		T44	2
all_pins[8]	values[0x0]	2084769	1			T23	4		T24	1		T25	1
all_pins[8]	values[0x1]	1268021	1			T23	6		T29	5		T30	33
all_pins[8]	transitions[0x0=>0x1]	756496	1			T23	5		T29	4		T30	16
all_pins[8]	transitions[0x1=>0x0]	761603	1			T29	4		T30	12		T44	1
all_pins[9]	values[0x0]	2085667	1			T23	4		T24	1		T25	1
all_pins[9]	values[0x1]	1267123	1			T23	6		T29	7		T30	28
all_pins[9]	transitions[0x0=>0x1]	760149	1			T23	2		T29	5		T30	9
all_pins[9]	transitions[0x1=>0x0]	761047	1			T23	2		T29	3		T30	14
all_pins[10]	values[0x0]	2082998	1			T23	6		T24	1		T25	1
all_pins[10]	values[0x1]	1269792	1			T23	4		T29	12		T30	33
all_pins[10]	transitions[0x0=>0x1]	759993	1			T23	1		T29	9		T30	22
all_pins[10]	transitions[0x1=>0x0]	757324	1			T23	3		T29	4		T30	17
all_pins[11]	values[0x0]	2088620	1			T23	6		T24	1		T25	1
all_pins[11]	values[0x1]	1264170	1			T23	4		T29	10		T30	42
all_pins[11]	transitions[0x0=>0x1]	756057	1			T29	3		T30	18		T44	8
all_pins[11]	transitions[0x1=>0x0]	761679	1			T29	5		T30	9		T45	135
all_pins[12]	values[0x0]	2086089	1			T23	4		T24	1		T25	1
all_pins[12]	values[0x1]	1266701	1			T23	6		T29	4		T30	32
all_pins[12]	transitions[0x0=>0x1]	761157	1			T23	2		T29	3		T30	13
all_pins[12]	transitions[0x1=>0x0]	758626	1			T29	9		T30	23		T44	7
all_pins[13]	values[0x0]	2084951	1			T23	5		T24	1		T25	1
all_pins[13]	values[0x1]	1267839	1			T23	5		T30	31		T45	315
all_pins[13]	transitions[0x0=>0x1]	759674	1			T23	3		T30	9		T45	139
all_pins[13]	transitions[0x1=>0x0]	758536	1			T23	4		T29	4		T30	10
all_pins[14]	values[0x0]	2082768	1			T23	7		T24	1		T25	1
all_pins[14]	values[0x1]	1270022	1			T23	3		T29	6		T30	39
all_pins[14]	transitions[0x0=>0x1]	761163	1			T23	2		T29	6		T30	19
all_pins[14]	transitions[0x1=>0x0]	758980	1			T23	4		T30	11		T45	168
all_pins[15]	values[0x0]	2083289	1			T23	4		T24	1		T25	1
all_pins[15]	values[0x1]	1269501	1			T23	6		T29	13		T30	36
all_pins[15]	transitions[0x0=>0x1]	759057	1			T23	3		T29	8		T30	15
all_pins[15]	transitions[0x1=>0x0]	759578	1			T29	1		T30	18		T45	150
all_pins[16]	values[0x0]	2088089	1			T23	6		T24	1		T25	1
all_pins[16]	values[0x1]	1264701	1			T23	4		T29	7		T30	32
all_pins[16]	transitions[0x0=>0x1]	756457	1			T23	1		T29	6		T30	11
all_pins[16]	transitions[0x1=>0x0]	761257	1			T23	3		T29	12		T30	15
all_pins[17]	values[0x0]	2081203	1			T23	3		T24	1		T25	1
all_pins[17]	values[0x1]	1271587	1			T23	7		T29	7		T30	32
all_pins[17]	transitions[0x0=>0x1]	763607	1			T23	4		T29	7		T30	15
all_pins[17]	transitions[0x1=>0x0]	756721	1			T23	1		T29	7		T30	15
all_pins[18]	values[0x0]	2079655	1			T23	6		T24	1		T25	1
all_pins[18]	values[0x1]	1273135	1			T23	4		T29	9		T30	31
all_pins[18]	transitions[0x0=>0x1]	761926	1			T23	2		T29	6		T30	16
all_pins[18]	transitions[0x1=>0x0]	760378	1			T23	5		T29	4		T30	17
all_pins[19]	values[0x0]	2079920	1			T23	7		T24	1		T25	1
all_pins[19]	values[0x1]	1272870	1			T23	3		T29	7		T30	31
all_pins[19]	transitions[0x0=>0x1]	757377	1			T23	3		T29	3		T30	15
all_pins[19]	transitions[0x1=>0x0]	757642	1			T23	4		T29	5		T30	15
all_pins[20]	values[0x0]	2084253	1			T23	6		T24	1		T25	1
all_pins[20]	values[0x1]	1268537	1			T23	4		T29	6		T30	21
all_pins[20]	transitions[0x0=>0x1]	756980	1			T23	2		T29	5		T30	8
all_pins[20]	transitions[0x1=>0x0]	761313	1			T23	1		T29	6		T30	18
all_pins[21]	values[0x0]	2082315	1			T23	6		T24	1		T25	1
all_pins[21]	values[0x1]	1270475	1			T23	4		T29	20		T30	26
all_pins[21]	transitions[0x0=>0x1]	759503	1			T23	1		T29	16		T30	18
all_pins[21]	transitions[0x1=>0x0]	757565	1			T23	1		T29	2		T30	13
all_pins[22]	values[0x0]	2085527	1			T23	5		T24	1		T25	1
all_pins[22]	values[0x1]	1267263	1			T23	5		T29	15		T30	34
all_pins[22]	transitions[0x0=>0x1]	757095	1			T23	3		T29	1		T30	19
all_pins[22]	transitions[0x1=>0x0]	760307	1			T23	2		T29	6		T30	11
all_pins[23]	values[0x0]	2085199	1			T23	5		T24	1		T25	1
all_pins[23]	values[0x1]	1267591	1			T23	5		T29	14		T30	31
all_pins[23]	transitions[0x0=>0x1]	760213	1			T23	3		T29	6		T30	15
all_pins[23]	transitions[0x1=>0x0]	759885	1			T23	3		T29	7		T30	18
all_pins[24]	values[0x0]	2083668	1			T23	7		T24	1		T25	1
all_pins[24]	values[0x1]	1269122	1			T23	3		T29	7		T30	31
all_pins[24]	transitions[0x0=>0x1]	760558	1			T23	3		T29	5		T30	19
all_pins[24]	transitions[0x1=>0x0]	759027	1			T23	5		T29	12		T30	19
all_pins[25]	values[0x0]	2079628	1			T23	6		T24	1		T25	1
all_pins[25]	values[0x1]	1273162	1			T23	4		T29	11		T30	25
all_pins[25]	transitions[0x0=>0x1]	761486	1			T23	2		T29	8		T30	14
all_pins[25]	transitions[0x1=>0x0]	757446	1			T23	1		T29	4		T30	20
all_pins[26]	values[0x0]	2082082	1			T23	6		T24	1		T25	1
all_pins[26]	values[0x1]	1270708	1			T23	4		T29	16		T30	24
all_pins[26]	transitions[0x0=>0x1]	759800	1			T23	2		T29	7		T30	10
all_pins[26]	transitions[0x1=>0x0]	762254	1			T23	2		T29	2		T30	11
all_pins[27]	values[0x0]	2088777	1			T23	6		T24	1		T25	1
all_pins[27]	values[0x1]	1264013	1			T23	4		T29	4		T30	31
all_pins[27]	transitions[0x0=>0x1]	754637	1			T23	3		T30	16		T44	1
all_pins[27]	transitions[0x1=>0x0]	761332	1			T23	3		T29	12		T30	9
all_pins[28]	values[0x0]	2078145	1			T23	6		T24	1		T25	1
all_pins[28]	values[0x1]	1274645	1			T23	4		T29	6		T30	36
all_pins[28]	transitions[0x0=>0x1]	764632	1			T23	3		T29	2		T30	21
all_pins[28]	transitions[0x1=>0x0]	754000	1			T23	3		T30	16		T44	1
all_pins[29]	values[0x0]	2085489	1			T23	6		T24	1		T25	1
all_pins[29]	values[0x1]	1267301	1			T23	4		T29	5		T30	33
all_pins[29]	transitions[0x0=>0x1]	756526	1			T23	2		T29	2		T30	16
all_pins[29]	transitions[0x1=>0x0]	763870	1			T23	2		T29	3		T30	19
all_pins[30]	values[0x0]	2079572	1			T23	5		T24	1		T25	1
all_pins[30]	values[0x1]	1273218	1			T23	5		T29	18		T30	25
all_pins[30]	transitions[0x0=>0x1]	762177	1			T23	2		T29	14		T30	15
all_pins[30]	transitions[0x1=>0x0]	756260	1			T23	1		T29	1		T30	23
all_pins[31]	values[0x0]	2088137	1			T23	5		T24	1		T25	1
all_pins[31]	values[0x1]	1264653	1			T23	5		T29	5		T30	38
all_pins[31]	transitions[0x0=>0x1]	755841	1			T23	2		T29	3		T30	26
all_pins[31]	transitions[0x1=>0x0]	764406	1			T23	2		T29	16		T30	13