Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[1]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[2]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[3]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[4]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[5]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[6]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[7]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[8]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[9]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[10]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[11]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[12]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[13]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[14]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[15]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[16]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[17]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[18]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[19]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[20]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[21]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[22]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[23]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[24]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[25]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[26]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[27]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[28]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[29]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[30]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[31]	11298567	1			T23	254		T24	1		T25	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212263653

1

T23

4236

T24

32

T25

32

auto[1]

149290491

1

T23

3892

T26

4011

T27

3174

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289985083

1

T23

8128

T24

32

T25

32

auto[1]

71569061

1

T26

4952

T27

1832

T29

278

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269306205

1

T23

8128

T24

32

T25

32

auto[1]

92247939

1

T26

9732

T27

1895

T29

907

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4142530	1			T23	111		T24	1		T25	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3146075	1			T23	143		T26	33		T27	68
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1123029	1			T26	87		T27	30		T29	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1369402	1			T26	149		T27	22		T29	7
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	402059	1			T26	8		T29	12		T32	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1115472	1			T26	67		T27	42		T29	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4134183	1			T23	115		T24	1		T25	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3158358	1			T23	139		T26	21		T27	63
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1123081	1			T26	101		T27	28		T29	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1363664	1			T26	209		T27	26		T29	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	403951	1			T26	32		T29	17		T32	11
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1115330	1			T26	64		T27	37		T29	22
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4144919	1			T23	139		T24	1		T25	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3145794	1			T23	115		T26	27		T27	63
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1123322	1			T26	91		T27	17		T29	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1365069	1			T26	212		T27	28		T29	12
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	399988	1			T26	27		T29	5		T32	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1119475	1			T26	63		T27	36		T29	3
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4146861	1			T23	84		T24	1		T25	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3145555	1			T23	170		T26	37		T27	71
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1126092	1			T26	73		T27	35		T29	9
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1364273	1			T26	160		T27	26		T29	34
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	403487	1			T26	25		T29	3		T32	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1112299	1			T26	59		T27	26		T29	3
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4137287	1			T23	114		T24	1		T25	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3149420	1			T23	140		T26	30		T27	64
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1128307	1			T26	81		T27	42		T31	76
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1363285	1			T26	209		T27	14		T29	7
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	404896	1			T26	34		T29	11		T32	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1115372	1			T26	69		T27	26		T29	9
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4137362	1			T23	112		T24	1		T25	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3152064	1			T23	142		T26	27		T27	74
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1130564	1			T26	80		T27	22		T29	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1364351	1			T26	198		T27	28		T29	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	402841	1			T26	31		T29	18		T32	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1111385	1			T26	86		T27	23		T29	19
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4141321	1			T23	137		T24	1		T25	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3152717	1			T23	117		T26	34		T27	66
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1126532	1			T26	82		T27	32		T29	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1364145	1			T26	216		T27	39		T29	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	401539	1			T26	30		T29	10		T32	28
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1112313	1			T26	63		T27	24		T29	20
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4149332	1			T23	130		T24	1		T25	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3142244	1			T23	124		T26	16		T27	69
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1126943	1			T26	84		T27	13		T31	84
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1362695	1			T26	225		T27	44		T29	32
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	404058	1			T26	35		T29	10		T32	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1113295	1			T26	73		T27	20		T31	80
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4129256	1			T23	119		T24	1		T25	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3164530	1			T23	135		T26	34		T27	65
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1123126	1			T26	81		T27	27		T31	83
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1367940	1			T26	212		T27	26		T29	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	403598	1			T26	25		T29	8		T32	19
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1110117	1			T26	51		T27	38		T29	9
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4141531	1			T23	143		T24	1		T25	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3148662	1			T23	111		T26	21		T27	85
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1123710	1			T26	65		T27	20		T29	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1364901	1			T26	232		T27	26		T29	17
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	401749	1			T26	34		T32	13		T101	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1118014	1			T26	69		T27	49		T31	67
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4145017	1			T23	138		T24	1		T25	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3149792	1			T23	116		T26	23		T27	66
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1124447	1			T26	110		T27	28		T29	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1364569	1			T26	202		T27	28		T29	22
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	403234	1			T26	29		T29	5		T32	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1111508	1			T26	75		T27	20		T29	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4146461	1			T23	141		T24	1		T25	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3142196	1			T23	113		T26	30		T27	72
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1125086	1			T26	97		T27	40		T29	11
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1363815	1			T26	244		T27	19		T29	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	402609	1			T26	23		T32	20		T101	7
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1118400	1			T26	36		T27	28		T31	96
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4139564	1			T23	116		T24	1		T25	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3148723	1			T23	138		T26	35		T27	68
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1125548	1			T26	69		T27	34		T31	68
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1367305	1			T26	176		T27	26		T29	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	403481	1			T26	15		T29	10		T32	12
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1113946	1			T26	74		T27	26		T29	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4129486	1			T23	127		T24	1		T25	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3158155	1			T23	127		T26	28		T27	69
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1123616	1			T26	75		T27	14		T29	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1364503	1			T26	207		T27	37		T29	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	404290	1			T26	23		T29	4		T32	21
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1118517	1			T26	90		T27	30		T29	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4142629	1			T23	190		T24	1		T25	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3147993	1			T23	64		T26	16		T27	75
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1128494	1			T26	92		T27	20		T29	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1361880	1			T26	229		T27	36		T29	23
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	401104	1			T26	32		T29	11		T32	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1116467	1			T26	106		T27	24		T29	9
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4139454	1			T23	164		T24	1		T25	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3149667	1			T23	90		T26	34		T27	67
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1119175	1			T26	48		T27	48		T31	96
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1372144	1			T26	240		T27	22		T29	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	404595	1			T26	27		T29	13		T32	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1113532	1			T26	68		T27	29		T29	9
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4148799	1			T23	158		T24	1		T25	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3148969	1			T23	96		T26	31		T27	67
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1121660	1			T26	120		T27	20		T29	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1366241	1			T26	191		T27	34		T29	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	403207	1			T26	17		T29	7		T32	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1109691	1			T26	66		T27	29		T31	91
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4138438	1			T23	153		T24	1		T25	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3154134	1			T23	101		T26	24		T27	54
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1126352	1			T26	67		T27	20		T31	67
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1365076	1			T26	229		T27	35		T29	10
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	403885	1			T26	30		T29	11		T32	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1110682	1			T26	63		T27	36		T29	2
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4145486	1			T23	112		T24	1		T25	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3147263	1			T23	142		T26	36		T27	72
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1118672	1			T26	126		T27	16		T29	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1373191	1			T26	167		T27	18		T29	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	402487	1			T26	22		T29	17		T32	14
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1111468	1			T26	58		T27	37		T29	3
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4143652	1			T23	78		T24	1		T25	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3149689	1			T23	176		T26	28		T27	74
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1116258	1			T26	61		T27	19		T29	7
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1374421	1			T26	200		T27	42		T29	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	402774	1			T26	32		T29	4		T32	28
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1111773	1			T26	61		T27	22		T31	114
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4145715	1			T23	131		T24	1		T25	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3148962	1			T23	123		T26	16		T27	64
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1117947	1			T26	63		T27	40		T29	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1370864	1			T26	260		T27	24		T29	7
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	403717	1			T26	35		T29	12		T32	18
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1111362	1			T26	48		T27	24		T29	5
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4151241	1			T23	150		T24	1		T25	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3138594	1			T23	104		T26	34		T27	62
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1120473	1			T26	61		T27	13		T29	6
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1368567	1			T26	225		T27	32		T29	15
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	403713	1			T26	24		T32	13		T101	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1115979	1			T26	89		T27	48		T31	84
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4142589	1			T23	136		T24	1		T25	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3152827	1			T23	118		T26	11		T27	69
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1122200	1			T26	92		T27	22		T29	15
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1371145	1			T26	268		T27	25		T29	23
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	401112	1			T26	39		T32	17		T101	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1108694	1			T26	89		T27	38		T31	77
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4138642	1			T23	114		T24	1		T25	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3158228	1			T23	140		T26	32		T27	72
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1130306	1			T26	124		T27	38		T29	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1360825	1			T26	138		T27	22		T29	18
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	400623	1			T26	30		T29	6		T32	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1109943	1			T26	79		T27	30		T31	68
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4143575	1			T23	135		T24	1		T25	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3151525	1			T23	119		T26	41		T27	75
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1122658	1			T26	65		T27	20		T29	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1368357	1			T26	158		T27	35		T29	14
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	404661	1			T26	17		T29	4		T32	14
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1107791	1			T26	68		T27	24		T31	68
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4156724	1			T23	162		T24	1		T25	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3137410	1			T23	92		T26	44		T27	65
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1120140	1			T26	69		T27	52		T29	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1370901	1			T26	218		T27	19		T29	28
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	403105	1			T26	19		T29	6		T32	17
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1110287	1			T26	77		T27	20		T31	76
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4137597	1			T23	141		T24	1		T25	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3155751	1			T23	113		T26	24		T27	73
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1120967	1			T26	62		T27	19		T29	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1367289	1			T26	258		T27	38		T29	17
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	402160	1			T26	35		T29	19		T32	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1114803	1			T26	55		T27	34		T29	3
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4143930	1			T23	121		T24	1		T25	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3147692	1			T23	133		T26	39		T27	60
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1120819	1			T26	122		T27	27		T29	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1373367	1			T26	138		T27	34		T29	11
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	401797	1			T26	13		T29	4		T32	21
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1110962	1			T26	68		T27	22		T31	84
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4148966	1			T23	131		T24	1		T25	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3142502	1			T23	123		T26	30		T27	72
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1121563	1			T26	79		T27	21		T29	6
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1369076	1			T26	209		T27	32		T29	17
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	404119	1			T26	28		T29	2		T32	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1112341	1			T26	57		T27	52		T31	106
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4149109	1			T23	130		T24	1		T25	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3151513	1			T23	124		T26	40		T27	66
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1125498	1			T26	160		T27	22		T29	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1362920	1			T26	151		T27	34		T31	79
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	400684	1			T26	17		T29	21		T32	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1108843	1			T26	63		T27	18		T29	4
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4140874	1			T23	124		T24	1		T25	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3153189	1			T23	130		T26	15		T27	78
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1123820	1			T26	57		T27	27		T31	74
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1365895	1			T26	262		T27	38		T29	16
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	403249	1			T26	43		T29	8		T32	16
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1111540	1			T26	110		T27	30		T29	4
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4149919	1			T23	180		T24	1		T25	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3141375	1			T23	74		T26	18		T27	80
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1121783	1			T26	77		T27	40		T29	7
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1366940	1			T26	238		T27	20		T29	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	403278	1			T26	40		T29	23		T32	18
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1115272	1			T26	67		T27	24		T29	10

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal