Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[1]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[2]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[3]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[4]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[5]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[6]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[7]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[8]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[9]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[10]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[11]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[12]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[13]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[14]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[15]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[16]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[17]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[18]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[19]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[20]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[21]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[22]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[23]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[24]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[25]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[26]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[27]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[28]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[29]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[30]	11298567	1			T23	254		T24	1		T25	1
bins_for_gpio_bits[31]	11298567	1			T23	254		T24	1		T25	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212263653

1

T23

4236

T24

32

T25

32

auto[1]

149290491

1

T23

3892

T26

4011

T27

3174

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212255502

1

T23

4236

T24

32

T25

32

auto[1]

149298642

1

T23

3892

T26

4020

T27

3180

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6435285	1			T23	111		T24	1		T25	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	199436	1			T26	14		T27	9		T31	24
bins_for_gpio_bits[0]	auto[1]	auto[0]	199676	1			T26	14		T27	9		T31	24
bins_for_gpio_bits[0]	auto[1]	auto[1]	4464170	1			T23	143		T26	94		T27	101
bins_for_gpio_bits[1]	auto[0]	auto[0]	6421279	1			T23	115		T24	1		T25	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	199373	1			T26	17		T27	9		T31	22
bins_for_gpio_bits[1]	auto[1]	auto[0]	199649	1			T26	17		T27	10		T31	22
bins_for_gpio_bits[1]	auto[1]	auto[1]	4478266	1			T23	139		T26	100		T27	91
bins_for_gpio_bits[2]	auto[0]	auto[0]	6433833	1			T23	139		T24	1		T25	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	199221	1			T26	12		T27	8		T31	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	199477	1			T26	12		T27	8		T31	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	4466036	1			T23	115		T26	105		T27	91
bins_for_gpio_bits[3]	auto[0]	auto[0]	6438469	1			T23	84		T24	1		T25	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	198487	1			T26	9		T27	7		T31	22
bins_for_gpio_bits[3]	auto[1]	auto[0]	198757	1			T26	10		T27	7		T31	22
bins_for_gpio_bits[3]	auto[1]	auto[1]	4462854	1			T23	170		T26	112		T27	90
bins_for_gpio_bits[4]	auto[0]	auto[0]	6429596	1			T23	114		T24	1		T25	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	199022	1			T26	16		T27	5		T31	23
bins_for_gpio_bits[4]	auto[1]	auto[0]	199283	1			T26	16		T27	5		T31	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	4470666	1			T23	140		T26	117		T27	85
bins_for_gpio_bits[5]	auto[0]	auto[0]	6433051	1			T23	112		T24	1		T25	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	198980	1			T26	15		T27	7		T31	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	199226	1			T26	15		T27	8		T31	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	4467310	1			T23	142		T26	129		T27	90
bins_for_gpio_bits[6]	auto[0]	auto[0]	6432904	1			T23	137		T24	1		T25	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	198812	1			T26	12		T27	8		T31	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	199094	1			T26	12		T27	8		T31	18
bins_for_gpio_bits[6]	auto[1]	auto[1]	4467757	1			T23	117		T26	115		T27	82
bins_for_gpio_bits[7]	auto[0]	auto[0]	6439902	1			T23	130		T24	1		T25	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	198840	1			T26	16		T27	5		T31	19
bins_for_gpio_bits[7]	auto[1]	auto[0]	199068	1			T26	17		T27	5		T31	19
bins_for_gpio_bits[7]	auto[1]	auto[1]	4460757	1			T23	124		T26	108		T27	84
bins_for_gpio_bits[8]	auto[0]	auto[0]	6421860	1			T23	119		T24	1		T25	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	198197	1			T26	11		T27	6		T31	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	198462	1			T26	11		T27	6		T31	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	4480048	1			T23	135		T26	99		T27	97
bins_for_gpio_bits[9]	auto[0]	auto[0]	6430772	1			T23	143		T24	1		T25	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	199126	1			T26	14		T27	9		T31	19
bins_for_gpio_bits[9]	auto[1]	auto[0]	199370	1			T26	15		T27	10		T31	20
bins_for_gpio_bits[9]	auto[1]	auto[1]	4469299	1			T23	111		T26	110		T27	125
bins_for_gpio_bits[10]	auto[0]	auto[0]	6435502	1			T23	138		T24	1		T25	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	198238	1			T26	12		T27	5		T31	23
bins_for_gpio_bits[10]	auto[1]	auto[0]	198531	1			T26	12		T27	5		T31	23
bins_for_gpio_bits[10]	auto[1]	auto[1]	4466296	1			T23	116		T26	115		T27	81
bins_for_gpio_bits[11]	auto[0]	auto[0]	6435661	1			T23	141		T24	1		T25	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	199426	1			T26	9		T27	9		T31	27
bins_for_gpio_bits[11]	auto[1]	auto[0]	199701	1			T26	9		T27	9		T31	27
bins_for_gpio_bits[11]	auto[1]	auto[1]	4463779	1			T23	113		T26	80		T27	91
bins_for_gpio_bits[12]	auto[0]	auto[0]	6432846	1			T23	116		T24	1		T25	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	199316	1			T26	14		T27	10		T31	21
bins_for_gpio_bits[12]	auto[1]	auto[0]	199571	1			T26	14		T27	10		T31	21
bins_for_gpio_bits[12]	auto[1]	auto[1]	4466834	1			T23	138		T26	110		T27	84
bins_for_gpio_bits[13]	auto[0]	auto[0]	6418274	1			T23	127		T24	1		T25	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	199074	1			T26	15		T27	7		T31	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	199331	1			T26	15		T27	7		T31	21
bins_for_gpio_bits[13]	auto[1]	auto[1]	4481888	1			T23	127		T26	126		T27	92
bins_for_gpio_bits[14]	auto[0]	auto[0]	6433883	1			T23	190		T24	1		T25	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	198849	1			T26	19		T27	5		T31	20
bins_for_gpio_bits[14]	auto[1]	auto[0]	199120	1			T26	19		T27	5		T31	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	4466715	1			T23	64		T26	135		T27	94
bins_for_gpio_bits[15]	auto[0]	auto[0]	6431903	1			T23	164		T24	1		T25	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	198568	1			T26	12		T27	8		T31	23
bins_for_gpio_bits[15]	auto[1]	auto[0]	198870	1			T26	12		T27	9		T31	23
bins_for_gpio_bits[15]	auto[1]	auto[1]	4469226	1			T23	90		T26	117		T27	88
bins_for_gpio_bits[16]	auto[0]	auto[0]	6438222	1			T23	158		T24	1		T25	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	198231	1			T26	11		T27	6		T31	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	198478	1			T26	11		T27	7		T31	25
bins_for_gpio_bits[16]	auto[1]	auto[1]	4463636	1			T23	96		T26	103		T27	90
bins_for_gpio_bits[17]	auto[0]	auto[0]	6430607	1			T23	153		T24	1		T25	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	198995	1			T26	14		T27	6		T31	21
bins_for_gpio_bits[17]	auto[1]	auto[0]	199259	1			T26	14		T27	6		T31	21
bins_for_gpio_bits[17]	auto[1]	auto[1]	4469706	1			T23	101		T26	103		T27	84
bins_for_gpio_bits[18]	auto[0]	auto[0]	6438721	1			T23	112		T24	1		T25	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	198415	1			T26	12		T27	7		T31	25
bins_for_gpio_bits[18]	auto[1]	auto[0]	198628	1			T26	12		T27	8		T31	25
bins_for_gpio_bits[18]	auto[1]	auto[1]	4462803	1			T23	142		T26	104		T27	102
bins_for_gpio_bits[19]	auto[0]	auto[0]	6434908	1			T23	78		T24	1		T25	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	199147	1			T26	15		T27	7		T31	26
bins_for_gpio_bits[19]	auto[1]	auto[0]	199423	1			T26	15		T27	7		T31	26
bins_for_gpio_bits[19]	auto[1]	auto[1]	4465089	1			T23	176		T26	106		T27	89
bins_for_gpio_bits[20]	auto[0]	auto[0]	6435361	1			T23	131		T24	1		T25	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	198934	1			T26	12		T27	8		T31	23
bins_for_gpio_bits[20]	auto[1]	auto[0]	199165	1			T26	12		T27	8		T31	23
bins_for_gpio_bits[20]	auto[1]	auto[1]	4465107	1			T23	123		T26	87		T27	80
bins_for_gpio_bits[21]	auto[0]	auto[0]	6441264	1			T23	150		T24	1		T25	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	198757	1			T26	12		T27	7		T31	22
bins_for_gpio_bits[21]	auto[1]	auto[0]	199017	1			T26	13		T27	7		T31	22
bins_for_gpio_bits[21]	auto[1]	auto[1]	4459529	1			T23	104		T26	135		T27	103
bins_for_gpio_bits[22]	auto[0]	auto[0]	6436797	1			T23	136		T24	1		T25	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	198854	1			T26	18		T27	9		T31	22
bins_for_gpio_bits[22]	auto[1]	auto[0]	199137	1			T26	18		T27	9		T31	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	4463779	1			T23	118		T26	121		T27	98
bins_for_gpio_bits[23]	auto[0]	auto[0]	6430345	1			T23	114		T24	1		T25	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	199178	1			T26	15		T27	8		T31	19
bins_for_gpio_bits[23]	auto[1]	auto[0]	199428	1			T26	16		T27	8		T31	19
bins_for_gpio_bits[23]	auto[1]	auto[1]	4469616	1			T23	140		T26	126		T27	94
bins_for_gpio_bits[24]	auto[0]	auto[0]	6435062	1			T23	135		T24	1		T25	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	199313	1			T26	11		T27	6		T31	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	199528	1			T26	11		T27	6		T31	17
bins_for_gpio_bits[24]	auto[1]	auto[1]	4464664	1			T23	119		T26	115		T27	93
bins_for_gpio_bits[25]	auto[0]	auto[0]	6448472	1			T23	162		T24	1		T25	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	199048	1			T26	12		T27	7		T31	21
bins_for_gpio_bits[25]	auto[1]	auto[0]	199293	1			T26	13		T27	7		T31	21
bins_for_gpio_bits[25]	auto[1]	auto[1]	4451754	1			T23	92		T26	128		T27	78
bins_for_gpio_bits[26]	auto[0]	auto[0]	6426356	1			T23	141		T24	1		T25	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	199244	1			T26	11		T27	6		T31	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	199497	1			T26	12		T27	6		T31	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	4473470	1			T23	113		T26	103		T27	101
bins_for_gpio_bits[27]	auto[0]	auto[0]	6438559	1			T23	121		T24	1		T25	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	199317	1			T26	14		T27	7		T31	24
bins_for_gpio_bits[27]	auto[1]	auto[0]	199557	1			T26	14		T27	7		T31	24
bins_for_gpio_bits[27]	auto[1]	auto[1]	4461134	1			T23	133		T26	106		T27	75
bins_for_gpio_bits[28]	auto[0]	auto[0]	6440250	1			T23	131		T24	1		T25	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	199124	1			T26	13		T27	6		T31	23
bins_for_gpio_bits[28]	auto[1]	auto[0]	199355	1			T26	13		T27	6		T31	23
bins_for_gpio_bits[28]	auto[1]	auto[1]	4459838	1			T23	123		T26	102		T27	118
bins_for_gpio_bits[29]	auto[0]	auto[0]	6438793	1			T23	130		T24	1		T25	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	198484	1			T26	11		T27	7		T31	17
bins_for_gpio_bits[29]	auto[1]	auto[0]	198734	1			T26	12		T27	7		T31	17
bins_for_gpio_bits[29]	auto[1]	auto[1]	4462556	1			T23	124		T26	109		T27	77
bins_for_gpio_bits[30]	auto[0]	auto[0]	6430902	1			T23	124		T24	1		T25	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	199474	1			T26	17		T27	7		T31	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	199687	1			T26	18		T27	7		T31	27
bins_for_gpio_bits[30]	auto[1]	auto[1]	4468504	1			T23	130		T26	151		T27	101
bins_for_gpio_bits[31]	auto[0]	auto[0]	6439250	1			T23	180		T24	1		T25	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	199133	1			T26	13		T27	8		T29	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	199392	1			T26	13		T27	8		T31	19
bins_for_gpio_bits[31]	auto[1]	auto[1]	4460792	1			T23	74		T26	112		T27	96