Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6724859 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4737600 |
1 |
|
|
T29 |
14 |
|
T44 |
25 |
|
T45 |
1487 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10862000 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
600459 |
1 |
|
|
T29 |
1 |
|
T44 |
1 |
|
T45 |
205 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6715166 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4747293 |
1 |
|
|
T29 |
10 |
|
T44 |
15 |
|
T45 |
1052 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2062043 |
1 |
|
|
T29 |
3 |
|
T44 |
1 |
|
T45 |
313 |
| auto[1] |
auto[0] |
auto[1] |
298326 |
1 |
|
|
T45 |
77 |
|
T34 |
7267 |
|
T58 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2084791 |
1 |
|
|
T29 |
6 |
|
T44 |
13 |
|
T45 |
534 |
| auto[1] |
auto[1] |
auto[1] |
302133 |
1 |
|
|
T29 |
1 |
|
T44 |
1 |
|
T45 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |