Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6731373 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4731086 |
1 |
|
|
T29 |
28 |
|
T44 |
11 |
|
T45 |
1202 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9493148 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
1969311 |
1 |
|
|
T29 |
6 |
|
T45 |
536 |
|
T34 |
41707 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6754702 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4707757 |
1 |
|
|
T29 |
6 |
|
T45 |
1009 |
|
T34 |
111296 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1372687 |
1 |
|
|
T45 |
270 |
|
T34 |
33241 |
|
T58 |
34 |
| auto[1] |
auto[0] |
auto[1] |
988950 |
1 |
|
|
T29 |
4 |
|
T45 |
287 |
|
T34 |
20193 |
| auto[1] |
auto[1] |
auto[0] |
1365759 |
1 |
|
|
T45 |
203 |
|
T34 |
36348 |
|
T58 |
32 |
| auto[1] |
auto[1] |
auto[1] |
980361 |
1 |
|
|
T29 |
2 |
|
T45 |
249 |
|
T34 |
21514 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |