Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6742528 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4719931 |
1 |
|
|
T29 |
33 |
|
T44 |
5 |
|
T45 |
823 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9484590 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
1977869 |
1 |
|
|
T29 |
7 |
|
T44 |
11 |
|
T45 |
702 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728164 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4734295 |
1 |
|
|
T29 |
21 |
|
T44 |
15 |
|
T45 |
1430 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1387943 |
1 |
|
|
T29 |
7 |
|
T44 |
4 |
|
T45 |
537 |
| auto[1] |
auto[0] |
auto[1] |
994006 |
1 |
|
|
T29 |
1 |
|
T44 |
11 |
|
T45 |
527 |
| auto[1] |
auto[1] |
auto[0] |
1368483 |
1 |
|
|
T29 |
7 |
|
T45 |
191 |
|
T34 |
35423 |
| auto[1] |
auto[1] |
auto[1] |
983863 |
1 |
|
|
T29 |
6 |
|
T45 |
175 |
|
T34 |
21206 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |