Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6763822 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4698637 |
1 |
|
|
T29 |
20 |
|
T44 |
12 |
|
T45 |
924 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9486759 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
1975700 |
1 |
|
|
T29 |
16 |
|
T44 |
5 |
|
T45 |
758 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6734322 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4728137 |
1 |
|
|
T29 |
16 |
|
T44 |
9 |
|
T45 |
1391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1385414 |
1 |
|
|
T44 |
3 |
|
T45 |
380 |
|
T33 |
5 |
| auto[1] |
auto[0] |
auto[1] |
992708 |
1 |
|
|
T29 |
13 |
|
T44 |
5 |
|
T45 |
448 |
| auto[1] |
auto[1] |
auto[0] |
1367023 |
1 |
|
|
T44 |
1 |
|
T45 |
253 |
|
T34 |
33515 |
| auto[1] |
auto[1] |
auto[1] |
982992 |
1 |
|
|
T29 |
3 |
|
T45 |
310 |
|
T34 |
19655 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |