Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6712112 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4750347 |
1 |
|
|
T29 |
33 |
|
T44 |
11 |
|
T45 |
1305 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10865437 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
597022 |
1 |
|
|
T29 |
2 |
|
T45 |
246 |
|
T33 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732814 |
1 |
|
|
T23 |
254 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
4729645 |
1 |
|
|
T29 |
29 |
|
T44 |
9 |
|
T45 |
1237 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2065111 |
1 |
|
|
T29 |
10 |
|
T44 |
5 |
|
T45 |
445 |
| auto[1] |
auto[0] |
auto[1] |
297606 |
1 |
|
|
T45 |
116 |
|
T33 |
1 |
|
T34 |
7495 |
| auto[1] |
auto[1] |
auto[0] |
2067512 |
1 |
|
|
T29 |
17 |
|
T44 |
4 |
|
T45 |
546 |
| auto[1] |
auto[1] |
auto[1] |
299416 |
1 |
|
|
T29 |
2 |
|
T45 |
130 |
|
T34 |
7295 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |