Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T764 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1231555127 Apr 16 12:20:20 PM PDT 24 Apr 16 12:20:22 PM PDT 24 129299504 ps
T765 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4128948252 Apr 16 12:21:43 PM PDT 24 Apr 16 12:21:46 PM PDT 24 45929741 ps
T81 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.708462320 Apr 16 12:17:55 PM PDT 24 Apr 16 12:17:58 PM PDT 24 83916516 ps
T766 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3865033818 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:10 PM PDT 24 39730948 ps
T767 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.468206797 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:43 PM PDT 24 128469115 ps
T82 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2040751967 Apr 16 12:19:05 PM PDT 24 Apr 16 12:19:07 PM PDT 24 136421965 ps
T768 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1668156030 Apr 16 12:20:08 PM PDT 24 Apr 16 12:20:10 PM PDT 24 17070795 ps
T769 /workspace/coverage/cover_reg_top/7.gpio_intr_test.870853565 Apr 16 12:21:11 PM PDT 24 Apr 16 12:21:13 PM PDT 24 88974389 ps
T99 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1957670200 Apr 16 12:21:31 PM PDT 24 Apr 16 12:21:33 PM PDT 24 511818030 ps
T770 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2643886618 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 56342089 ps
T771 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1597200574 Apr 16 12:21:13 PM PDT 24 Apr 16 12:21:15 PM PDT 24 17532814 ps
T772 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2921515375 Apr 16 12:20:08 PM PDT 24 Apr 16 12:20:10 PM PDT 24 20150181 ps
T773 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4054411577 Apr 16 12:21:02 PM PDT 24 Apr 16 12:21:04 PM PDT 24 66378479 ps
T774 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4015396023 Apr 16 12:20:05 PM PDT 24 Apr 16 12:20:07 PM PDT 24 20174094 ps
T775 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1612817698 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:09 PM PDT 24 37997502 ps
T776 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3971218689 Apr 16 12:17:45 PM PDT 24 Apr 16 12:17:46 PM PDT 24 13568349 ps
T777 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2655134319 Apr 16 12:21:27 PM PDT 24 Apr 16 12:21:29 PM PDT 24 36240714 ps
T778 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4148039928 Apr 16 12:20:33 PM PDT 24 Apr 16 12:20:35 PM PDT 24 60729728 ps
T83 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1612871847 Apr 16 12:21:21 PM PDT 24 Apr 16 12:21:23 PM PDT 24 16857463 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2851705441 Apr 16 12:19:38 PM PDT 24 Apr 16 12:19:40 PM PDT 24 37846271 ps
T84 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2402074059 Apr 16 12:21:49 PM PDT 24 Apr 16 12:21:52 PM PDT 24 20054063 ps
T780 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2837579388 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:49 PM PDT 24 25544956 ps
T781 /workspace/coverage/cover_reg_top/16.gpio_intr_test.813367951 Apr 16 12:22:57 PM PDT 24 Apr 16 12:23:01 PM PDT 24 16371509 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3758884685 Apr 16 12:21:45 PM PDT 24 Apr 16 12:21:48 PM PDT 24 94541277 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3266734946 Apr 16 12:17:58 PM PDT 24 Apr 16 12:18:01 PM PDT 24 139778204 ps
T784 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1217416803 Apr 16 12:22:59 PM PDT 24 Apr 16 12:23:03 PM PDT 24 41829803 ps
T785 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1071769754 Apr 16 12:21:44 PM PDT 24 Apr 16 12:21:48 PM PDT 24 40622754 ps
T786 /workspace/coverage/cover_reg_top/42.gpio_intr_test.780030633 Apr 16 12:21:26 PM PDT 24 Apr 16 12:21:29 PM PDT 24 16158637 ps
T787 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1791941606 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:50 PM PDT 24 102473215 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3423717496 Apr 16 12:21:00 PM PDT 24 Apr 16 12:21:03 PM PDT 24 227889372 ps
T789 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2608519846 Apr 16 12:21:07 PM PDT 24 Apr 16 12:21:10 PM PDT 24 38664079 ps
T790 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.314883677 Apr 16 12:19:09 PM PDT 24 Apr 16 12:19:11 PM PDT 24 36001990 ps
T791 /workspace/coverage/cover_reg_top/29.gpio_intr_test.133768213 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:08 PM PDT 24 30151836 ps
T792 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1135817234 Apr 16 12:22:06 PM PDT 24 Apr 16 12:22:09 PM PDT 24 20842912 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.234243018 Apr 16 12:18:51 PM PDT 24 Apr 16 12:18:53 PM PDT 24 14321714 ps
T794 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2481310066 Apr 16 12:20:58 PM PDT 24 Apr 16 12:21:00 PM PDT 24 41080292 ps
T795 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2751796269 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:50 PM PDT 24 86418420 ps
T796 /workspace/coverage/cover_reg_top/36.gpio_intr_test.831304584 Apr 16 12:22:40 PM PDT 24 Apr 16 12:22:47 PM PDT 24 50502003 ps
T797 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1267475867 Apr 16 12:21:19 PM PDT 24 Apr 16 12:21:21 PM PDT 24 41845655 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.779399344 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:49 PM PDT 24 28122905 ps
T799 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2517445570 Apr 16 12:23:25 PM PDT 24 Apr 16 12:23:27 PM PDT 24 14838329 ps
T800 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1310592314 Apr 16 12:20:05 PM PDT 24 Apr 16 12:20:07 PM PDT 24 11361700 ps
T801 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3441910882 Apr 16 12:20:19 PM PDT 24 Apr 16 12:20:23 PM PDT 24 164368411 ps
T802 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.765452631 Apr 16 12:17:42 PM PDT 24 Apr 16 12:17:43 PM PDT 24 13220432 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2710046604 Apr 16 12:18:51 PM PDT 24 Apr 16 12:18:53 PM PDT 24 11735418 ps
T804 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2497790950 Apr 16 12:20:18 PM PDT 24 Apr 16 12:20:21 PM PDT 24 175414974 ps
T805 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.247634950 Apr 16 12:21:34 PM PDT 24 Apr 16 12:21:36 PM PDT 24 127602498 ps
T90 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4090889812 Apr 16 12:21:11 PM PDT 24 Apr 16 12:21:13 PM PDT 24 12613508 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4031158010 Apr 16 12:20:59 PM PDT 24 Apr 16 12:21:02 PM PDT 24 50664151 ps
T806 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.308081884 Apr 16 12:22:06 PM PDT 24 Apr 16 12:22:09 PM PDT 24 15511768 ps
T807 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4204828 Apr 16 12:19:35 PM PDT 24 Apr 16 12:19:37 PM PDT 24 155029890 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1054787487 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:44 PM PDT 24 23039376 ps
T809 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2361498251 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:50 PM PDT 24 37109306 ps
T87 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1910952894 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 33196005 ps
T810 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3302309207 Apr 16 12:21:11 PM PDT 24 Apr 16 12:21:13 PM PDT 24 21828897 ps
T811 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3867279087 Apr 16 12:22:40 PM PDT 24 Apr 16 12:22:48 PM PDT 24 30299091 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_intr_test.40462318 Apr 16 12:21:01 PM PDT 24 Apr 16 12:21:03 PM PDT 24 12230320 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1776362520 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:10 PM PDT 24 514617837 ps
T813 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2846015999 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 56637181 ps
T100 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1837110603 Apr 16 12:18:24 PM PDT 24 Apr 16 12:18:26 PM PDT 24 118632129 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.310309439 Apr 16 12:21:04 PM PDT 24 Apr 16 12:21:07 PM PDT 24 122684957 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1393255393 Apr 16 12:20:42 PM PDT 24 Apr 16 12:20:45 PM PDT 24 161918652 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3068630658 Apr 16 12:19:51 PM PDT 24 Apr 16 12:19:52 PM PDT 24 13249662 ps
T817 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2689709608 Apr 16 12:20:56 PM PDT 24 Apr 16 12:20:59 PM PDT 24 30595503 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.953617101 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:44 PM PDT 24 41243492 ps
T819 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1733774257 Apr 16 12:21:25 PM PDT 24 Apr 16 12:21:28 PM PDT 24 56395263 ps
T820 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2001512989 Apr 16 12:19:20 PM PDT 24 Apr 16 12:19:23 PM PDT 24 102558941 ps
T821 /workspace/coverage/cover_reg_top/19.gpio_intr_test.639021762 Apr 16 12:19:49 PM PDT 24 Apr 16 12:19:51 PM PDT 24 13026996 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3572016851 Apr 16 12:20:18 PM PDT 24 Apr 16 12:20:21 PM PDT 24 273843018 ps
T823 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3887994582 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 460153274 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.808841479 Apr 16 12:18:06 PM PDT 24 Apr 16 12:18:07 PM PDT 24 48026685 ps
T824 /workspace/coverage/cover_reg_top/31.gpio_intr_test.252602787 Apr 16 12:21:14 PM PDT 24 Apr 16 12:21:17 PM PDT 24 21433587 ps
T825 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3689771542 Apr 16 12:21:31 PM PDT 24 Apr 16 12:21:33 PM PDT 24 42170836 ps
T826 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3664205456 Apr 16 12:20:01 PM PDT 24 Apr 16 12:20:02 PM PDT 24 23266996 ps
T52 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4126206566 Apr 16 12:21:07 PM PDT 24 Apr 16 12:21:11 PM PDT 24 542236580 ps
T827 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1533201722 Apr 16 12:21:31 PM PDT 24 Apr 16 12:21:35 PM PDT 24 1815288856 ps
T828 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.625422016 Apr 16 12:19:02 PM PDT 24 Apr 16 12:19:03 PM PDT 24 45703248 ps
T829 /workspace/coverage/cover_reg_top/49.gpio_intr_test.633050610 Apr 16 12:20:18 PM PDT 24 Apr 16 12:20:20 PM PDT 24 14084630 ps
T830 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1021333287 Apr 16 12:21:52 PM PDT 24 Apr 16 12:21:55 PM PDT 24 67316269 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3795786409 Apr 16 12:20:58 PM PDT 24 Apr 16 12:21:00 PM PDT 24 41742740 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.952202177 Apr 16 12:22:42 PM PDT 24 Apr 16 12:22:51 PM PDT 24 82626264 ps
T89 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2433109933 Apr 16 12:19:35 PM PDT 24 Apr 16 12:19:36 PM PDT 24 58568054 ps
T833 /workspace/coverage/cover_reg_top/47.gpio_intr_test.140787764 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:43 PM PDT 24 14071188 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2519391107 Apr 16 12:18:50 PM PDT 24 Apr 16 12:18:52 PM PDT 24 319459747 ps
T835 /workspace/coverage/cover_reg_top/14.gpio_intr_test.692297853 Apr 16 12:20:51 PM PDT 24 Apr 16 12:20:53 PM PDT 24 10626586 ps
T836 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4084881836 Apr 16 12:19:39 PM PDT 24 Apr 16 12:19:41 PM PDT 24 22472236 ps
T837 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1210137684 Apr 16 12:18:50 PM PDT 24 Apr 16 12:18:51 PM PDT 24 27894216 ps
T838 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.82553134 Apr 16 12:19:53 PM PDT 24 Apr 16 12:19:57 PM PDT 24 52936410 ps
T839 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3232873702 Apr 16 12:20:52 PM PDT 24 Apr 16 12:20:54 PM PDT 24 89905836 ps
T840 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2000881525 Apr 16 12:21:01 PM PDT 24 Apr 16 12:21:03 PM PDT 24 211797126 ps
T841 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1104455697 Apr 16 12:21:05 PM PDT 24 Apr 16 12:21:07 PM PDT 24 333077007 ps
T842 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.766999673 Apr 16 12:21:05 PM PDT 24 Apr 16 12:21:08 PM PDT 24 151444296 ps
T843 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3110354293 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 55779295 ps
T844 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1224507734 Apr 16 12:21:20 PM PDT 24 Apr 16 12:21:23 PM PDT 24 140668907 ps
T845 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1569065829 Apr 16 12:21:47 PM PDT 24 Apr 16 12:21:51 PM PDT 24 237178148 ps
T846 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1516250736 Apr 16 12:18:18 PM PDT 24 Apr 16 12:18:20 PM PDT 24 92519884 ps
T847 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4049732244 Apr 16 12:21:45 PM PDT 24 Apr 16 12:21:49 PM PDT 24 50951984 ps
T848 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894081747 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 1322380513 ps
T849 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.142434210 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 43011759 ps
T850 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1249948393 Apr 16 12:20:48 PM PDT 24 Apr 16 12:20:50 PM PDT 24 88160934 ps
T851 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2963182973 Apr 16 12:21:51 PM PDT 24 Apr 16 12:21:55 PM PDT 24 109740224 ps
T852 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1445681518 Apr 16 12:18:09 PM PDT 24 Apr 16 12:18:11 PM PDT 24 151633489 ps
T853 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3596923450 Apr 16 12:21:03 PM PDT 24 Apr 16 12:21:05 PM PDT 24 275201362 ps
T854 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2444464352 Apr 16 12:18:17 PM PDT 24 Apr 16 12:18:19 PM PDT 24 81696370 ps
T855 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942755170 Apr 16 12:18:32 PM PDT 24 Apr 16 12:18:34 PM PDT 24 303025719 ps
T856 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1610780028 Apr 16 12:19:20 PM PDT 24 Apr 16 12:19:22 PM PDT 24 121703408 ps
T857 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2211415728 Apr 16 12:21:16 PM PDT 24 Apr 16 12:21:18 PM PDT 24 55029901 ps
T858 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1560062471 Apr 16 12:21:45 PM PDT 24 Apr 16 12:21:49 PM PDT 24 360567055 ps
T859 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1407114717 Apr 16 12:19:20 PM PDT 24 Apr 16 12:19:21 PM PDT 24 45103217 ps
T860 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.692941781 Apr 16 12:21:04 PM PDT 24 Apr 16 12:21:06 PM PDT 24 364024295 ps
T861 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3681170528 Apr 16 12:21:57 PM PDT 24 Apr 16 12:22:00 PM PDT 24 332007694 ps
T862 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1144592295 Apr 16 12:18:11 PM PDT 24 Apr 16 12:18:12 PM PDT 24 262147440 ps
T863 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2371771139 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:44 PM PDT 24 126902337 ps
T864 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3453970451 Apr 16 12:20:56 PM PDT 24 Apr 16 12:20:59 PM PDT 24 65145340 ps
T865 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2977361669 Apr 16 12:20:47 PM PDT 24 Apr 16 12:20:49 PM PDT 24 26784313 ps
T866 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2743461793 Apr 16 12:21:56 PM PDT 24 Apr 16 12:21:58 PM PDT 24 34661520 ps
T867 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787768377 Apr 16 12:21:20 PM PDT 24 Apr 16 12:21:23 PM PDT 24 110394435 ps
T868 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3513762216 Apr 16 12:21:02 PM PDT 24 Apr 16 12:21:05 PM PDT 24 114057651 ps
T869 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3839334956 Apr 16 12:21:47 PM PDT 24 Apr 16 12:21:51 PM PDT 24 919486699 ps
T870 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2242815505 Apr 16 12:22:43 PM PDT 24 Apr 16 12:22:50 PM PDT 24 244029465 ps
T871 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2088886399 Apr 16 12:17:55 PM PDT 24 Apr 16 12:17:57 PM PDT 24 81425538 ps
T872 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459224723 Apr 16 12:21:50 PM PDT 24 Apr 16 12:21:54 PM PDT 24 134296478 ps
T873 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844871494 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 71972766 ps
T874 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.342025631 Apr 16 12:22:41 PM PDT 24 Apr 16 12:22:49 PM PDT 24 98255071 ps
T875 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1969568845 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 130736415 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1552680179 Apr 16 12:21:34 PM PDT 24 Apr 16 12:21:36 PM PDT 24 29186409 ps
T877 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4064501522 Apr 16 12:21:31 PM PDT 24 Apr 16 12:21:34 PM PDT 24 285855695 ps
T878 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097644928 Apr 16 12:20:58 PM PDT 24 Apr 16 12:21:01 PM PDT 24 165693815 ps
T879 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4060456323 Apr 16 12:18:53 PM PDT 24 Apr 16 12:18:55 PM PDT 24 76817311 ps
T880 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4075902316 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 235032893 ps
T881 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2225129313 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:09 PM PDT 24 137934749 ps
T882 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1734376607 Apr 16 12:18:11 PM PDT 24 Apr 16 12:18:14 PM PDT 24 278200380 ps
T883 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348413662 Apr 16 12:18:24 PM PDT 24 Apr 16 12:18:26 PM PDT 24 52312906 ps
T884 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2617528112 Apr 16 12:17:59 PM PDT 24 Apr 16 12:18:00 PM PDT 24 42229284 ps
T885 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1962578706 Apr 16 12:21:45 PM PDT 24 Apr 16 12:21:48 PM PDT 24 78896893 ps
T886 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.41492524 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 101269047 ps
T887 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3512508555 Apr 16 12:18:22 PM PDT 24 Apr 16 12:18:24 PM PDT 24 88239850 ps
T888 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1175240361 Apr 16 12:19:40 PM PDT 24 Apr 16 12:19:42 PM PDT 24 32284008 ps
T889 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607553040 Apr 16 12:20:40 PM PDT 24 Apr 16 12:20:42 PM PDT 24 66295067 ps
T890 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3955693803 Apr 16 12:18:20 PM PDT 24 Apr 16 12:18:22 PM PDT 24 37592938 ps
T891 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2938210488 Apr 16 12:21:02 PM PDT 24 Apr 16 12:21:05 PM PDT 24 165480646 ps
T892 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.523503788 Apr 16 12:22:43 PM PDT 24 Apr 16 12:22:50 PM PDT 24 300953738 ps
T893 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2210305074 Apr 16 12:19:20 PM PDT 24 Apr 16 12:19:22 PM PDT 24 83370085 ps
T894 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.986144721 Apr 16 12:19:30 PM PDT 24 Apr 16 12:19:32 PM PDT 24 893891470 ps
T895 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3861246472 Apr 16 12:21:43 PM PDT 24 Apr 16 12:21:47 PM PDT 24 175344679 ps
T896 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.968171743 Apr 16 12:21:11 PM PDT 24 Apr 16 12:21:13 PM PDT 24 61726975 ps
T897 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1782821144 Apr 16 12:19:41 PM PDT 24 Apr 16 12:19:43 PM PDT 24 47087582 ps
T898 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3760021739 Apr 16 12:20:58 PM PDT 24 Apr 16 12:21:01 PM PDT 24 167924110 ps
T899 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.121581521 Apr 16 12:21:52 PM PDT 24 Apr 16 12:21:56 PM PDT 24 72140543 ps
T900 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310427500 Apr 16 12:22:42 PM PDT 24 Apr 16 12:22:49 PM PDT 24 68263540 ps
T901 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4186808326 Apr 16 12:21:56 PM PDT 24 Apr 16 12:21:59 PM PDT 24 39011805 ps
T902 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.448936838 Apr 16 12:17:56 PM PDT 24 Apr 16 12:17:58 PM PDT 24 80931154 ps
T903 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1619306710 Apr 16 12:18:37 PM PDT 24 Apr 16 12:18:40 PM PDT 24 285478104 ps
T904 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4138907681 Apr 16 12:19:17 PM PDT 24 Apr 16 12:19:18 PM PDT 24 37302807 ps
T905 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3157786344 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 96651925 ps
T906 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3426700871 Apr 16 12:21:20 PM PDT 24 Apr 16 12:21:22 PM PDT 24 161421431 ps
T907 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3826132320 Apr 16 12:21:05 PM PDT 24 Apr 16 12:21:07 PM PDT 24 53102208 ps
T908 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4237028709 Apr 16 12:21:05 PM PDT 24 Apr 16 12:21:07 PM PDT 24 153169169 ps
T909 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.750733710 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 50357920 ps
T910 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3104824389 Apr 16 12:21:13 PM PDT 24 Apr 16 12:21:16 PM PDT 24 198736971 ps
T911 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3169791190 Apr 16 12:22:43 PM PDT 24 Apr 16 12:22:50 PM PDT 24 64199431 ps
T912 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2701391646 Apr 16 12:20:33 PM PDT 24 Apr 16 12:20:34 PM PDT 24 58625031 ps
T913 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3743581312 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 91565485 ps
T914 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3211880359 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 64345191 ps
T915 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151806994 Apr 16 12:18:38 PM PDT 24 Apr 16 12:18:41 PM PDT 24 64536812 ps
T916 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865735875 Apr 16 12:21:52 PM PDT 24 Apr 16 12:21:56 PM PDT 24 690235410 ps
T917 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3654772786 Apr 16 12:20:56 PM PDT 24 Apr 16 12:20:59 PM PDT 24 169687486 ps
T918 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2625103294 Apr 16 12:20:57 PM PDT 24 Apr 16 12:21:00 PM PDT 24 559321093 ps
T919 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1555273333 Apr 16 12:21:02 PM PDT 24 Apr 16 12:21:04 PM PDT 24 55020417 ps
T920 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849733279 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:09 PM PDT 24 187085735 ps
T921 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4282196929 Apr 16 12:18:38 PM PDT 24 Apr 16 12:18:40 PM PDT 24 534021242 ps
T922 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1980578972 Apr 16 12:18:38 PM PDT 24 Apr 16 12:18:41 PM PDT 24 216319139 ps
T923 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3160999321 Apr 16 12:21:04 PM PDT 24 Apr 16 12:21:07 PM PDT 24 41523755 ps
T924 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545944327 Apr 16 12:21:06 PM PDT 24 Apr 16 12:21:10 PM PDT 24 183904129 ps
T925 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3070920332 Apr 16 12:22:42 PM PDT 24 Apr 16 12:22:49 PM PDT 24 36169345 ps
T926 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2548111047 Apr 16 12:21:48 PM PDT 24 Apr 16 12:21:52 PM PDT 24 136792798 ps
T927 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1386967004 Apr 16 12:19:18 PM PDT 24 Apr 16 12:19:20 PM PDT 24 196892012 ps
T928 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1395979549 Apr 16 12:21:05 PM PDT 24 Apr 16 12:21:07 PM PDT 24 677127613 ps
T929 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.955504652 Apr 16 12:18:46 PM PDT 24 Apr 16 12:18:48 PM PDT 24 608893309 ps
T930 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4227312260 Apr 16 12:17:49 PM PDT 24 Apr 16 12:17:50 PM PDT 24 129324802 ps
T931 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.506977554 Apr 16 12:21:41 PM PDT 24 Apr 16 12:21:44 PM PDT 24 216964929 ps
T932 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2354468692 Apr 16 12:19:14 PM PDT 24 Apr 16 12:19:16 PM PDT 24 88955321 ps
T933 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162097780 Apr 16 12:23:24 PM PDT 24 Apr 16 12:23:25 PM PDT 24 125924155 ps
T934 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.506085837 Apr 16 12:21:57 PM PDT 24 Apr 16 12:22:00 PM PDT 24 77857718 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2429855041 Apr 16 12:22:53 PM PDT 24 Apr 16 12:22:59 PM PDT 24 321615713 ps
T936 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3036980024 Apr 16 12:20:57 PM PDT 24 Apr 16 12:20:59 PM PDT 24 49774380 ps
T937 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.357719541 Apr 16 12:19:54 PM PDT 24 Apr 16 12:19:56 PM PDT 24 155746224 ps
T938 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3320354458 Apr 16 12:21:34 PM PDT 24 Apr 16 12:21:36 PM PDT 24 218762645 ps

Test location /workspace/coverage/default/43.gpio_full_random.3542459229
Short name T29
Test name
Test status
Simulation time 64678888 ps
CPU time 0.86 seconds
Started Apr 16 12:23:59 PM PDT 24
Finished Apr 16 12:24:01 PM PDT 24
Peak memory 196232 kb
Host smart-2aedd2a4-5a57-47f5-b7a2-44c768ead181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542459229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3542459229
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3137313377
Short name T30
Test name
Test status
Simulation time 875017370 ps
CPU time 2.61 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 198116 kb
Host smart-cc413805-fb49-43e0-94a0-166e01627f2b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137313377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3137313377
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3945347103
Short name T34
Test name
Test status
Simulation time 466467338010 ps
CPU time 1183.06 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:44:03 PM PDT 24
Peak memory 198180 kb
Host smart-96219f53-759e-498e-9bde-3925ad2dde11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3945347103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3945347103
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1809813269
Short name T41
Test name
Test status
Simulation time 104708506 ps
CPU time 0.76 seconds
Started Apr 16 12:22:24 PM PDT 24
Finished Apr 16 12:22:27 PM PDT 24
Peak memory 213568 kb
Host smart-fb0d7829-e35e-46e1-ad3f-486fef5a1d94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809813269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1809813269
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.274182590
Short name T76
Test name
Test status
Simulation time 101891945 ps
CPU time 0.62 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 194852 kb
Host smart-7186dbca-8b18-4057-abe5-42fcdd5c1313
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274182590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.274182590
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1222771777
Short name T1
Test name
Test status
Simulation time 826876173 ps
CPU time 5.44 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 197912 kb
Host smart-dcae8e83-d29c-4f62-8e98-947e944de1e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222771777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1222771777
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3585620068
Short name T48
Test name
Test status
Simulation time 434789303 ps
CPU time 1.33 seconds
Started Apr 16 12:21:08 PM PDT 24
Finished Apr 16 12:21:12 PM PDT 24
Peak memory 198056 kb
Host smart-767f3760-e05c-4d50-822b-2137b4141836
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585620068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3585620068
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3233562937
Short name T160
Test name
Test status
Simulation time 33853615 ps
CPU time 0.54 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 193848 kb
Host smart-5bd08fc6-cc25-47d2-89f1-61ab815d0fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233562937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3233562937
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2854584199
Short name T94
Test name
Test status
Simulation time 247873665 ps
CPU time 0.85 seconds
Started Apr 16 12:21:51 PM PDT 24
Finished Apr 16 12:21:54 PM PDT 24
Peak memory 196060 kb
Host smart-702d3e2c-7051-4fd7-9df1-763e15d9c676
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854584199 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2854584199
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.129774395
Short name T26
Test name
Test status
Simulation time 94974175 ps
CPU time 1.1 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:20 PM PDT 24
Peak memory 196016 kb
Host smart-dbceb05c-531e-4598-aedf-5734b1dd4c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129774395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.129774395
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2299067952
Short name T54
Test name
Test status
Simulation time 323240286 ps
CPU time 1.51 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 194692 kb
Host smart-471b49a5-83a0-43c9-833f-d35df4434fd7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299067952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2299067952
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4126206566
Short name T52
Test name
Test status
Simulation time 542236580 ps
CPU time 1.84 seconds
Started Apr 16 12:21:07 PM PDT 24
Finished Apr 16 12:21:11 PM PDT 24
Peak memory 197840 kb
Host smart-cf64d167-ed56-43f3-b7cd-41c8e1c04833
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126206566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4126206566
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3463626122
Short name T746
Test name
Test status
Simulation time 63944174 ps
CPU time 0.85 seconds
Started Apr 16 12:20:48 PM PDT 24
Finished Apr 16 12:20:49 PM PDT 24
Peak memory 195408 kb
Host smart-4f829fe1-c894-477a-a508-deaeba8d74e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463626122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3463626122
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1393255393
Short name T815
Test name
Test status
Simulation time 161918652 ps
CPU time 2.96 seconds
Started Apr 16 12:20:42 PM PDT 24
Finished Apr 16 12:20:45 PM PDT 24
Peak memory 197168 kb
Host smart-42b37b3d-77b4-47ca-b472-46d7fad4e2f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393255393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1393255393
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.808841479
Short name T86
Test name
Test status
Simulation time 48026685 ps
CPU time 0.64 seconds
Started Apr 16 12:18:06 PM PDT 24
Finished Apr 16 12:18:07 PM PDT 24
Peak memory 194844 kb
Host smart-365ee44e-0964-4e41-ac1f-b2b3c9f2c41d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808841479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.808841479
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2894624818
Short name T720
Test name
Test status
Simulation time 22585057 ps
CPU time 1.06 seconds
Started Apr 16 12:20:17 PM PDT 24
Finished Apr 16 12:20:19 PM PDT 24
Peak memory 198120 kb
Host smart-f1bce42e-f2b5-4fe5-a590-3371b1f29432
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894624818 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2894624818
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2047368930
Short name T751
Test name
Test status
Simulation time 13822982 ps
CPU time 0.63 seconds
Started Apr 16 12:17:47 PM PDT 24
Finished Apr 16 12:17:48 PM PDT 24
Peak memory 195332 kb
Host smart-649ca35f-6252-4f00-9925-55baebcda955
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047368930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2047368930
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3971218689
Short name T776
Test name
Test status
Simulation time 13568349 ps
CPU time 0.73 seconds
Started Apr 16 12:17:45 PM PDT 24
Finished Apr 16 12:17:46 PM PDT 24
Peak memory 193704 kb
Host smart-2298ac29-54b7-4762-a043-c0713fb03134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971218689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3971218689
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.884684308
Short name T756
Test name
Test status
Simulation time 22581116 ps
CPU time 0.64 seconds
Started Apr 16 12:18:32 PM PDT 24
Finished Apr 16 12:18:34 PM PDT 24
Peak memory 194964 kb
Host smart-0d2873d1-a235-4363-97fc-39493475a198
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884684308 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.884684308
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2001512989
Short name T820
Test name
Test status
Simulation time 102558941 ps
CPU time 2.53 seconds
Started Apr 16 12:19:20 PM PDT 24
Finished Apr 16 12:19:23 PM PDT 24
Peak memory 198048 kb
Host smart-cd86282f-30f9-4dde-854d-c742bc009dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001512989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2001512989
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1837110603
Short name T100
Test name
Test status
Simulation time 118632129 ps
CPU time 1.46 seconds
Started Apr 16 12:18:24 PM PDT 24
Finished Apr 16 12:18:26 PM PDT 24
Peak memory 198048 kb
Host smart-d89e64dd-56e1-4d0c-ba07-3e83baaac9e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837110603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1837110603
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2295899320
Short name T78
Test name
Test status
Simulation time 33457128 ps
CPU time 0.69 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 193120 kb
Host smart-854a1ade-69d8-4f8f-9be5-8b0841dffe19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295899320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2295899320
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.708462320
Short name T81
Test name
Test status
Simulation time 83916516 ps
CPU time 3.07 seconds
Started Apr 16 12:17:55 PM PDT 24
Finished Apr 16 12:17:58 PM PDT 24
Peak memory 197176 kb
Host smart-a05c0f15-c31d-4f3c-9496-69c5e77927b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708462320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.708462320
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.765452631
Short name T802
Test name
Test status
Simulation time 13220432 ps
CPU time 0.65 seconds
Started Apr 16 12:17:42 PM PDT 24
Finished Apr 16 12:17:43 PM PDT 24
Peak memory 194680 kb
Host smart-6c5a9440-0ea4-4c0d-882f-5c8d78caadf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765452631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.765452631
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3017252789
Short name T762
Test name
Test status
Simulation time 155994609 ps
CPU time 0.69 seconds
Started Apr 16 12:20:48 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 196860 kb
Host smart-6dac4773-2ce8-4d8a-8885-01ff29488ca3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017252789 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3017252789
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4084881836
Short name T836
Test name
Test status
Simulation time 22472236 ps
CPU time 0.71 seconds
Started Apr 16 12:19:39 PM PDT 24
Finished Apr 16 12:19:41 PM PDT 24
Peak memory 195436 kb
Host smart-ccee47db-c325-4283-82ee-715beb39db78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084881836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4084881836
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2837579388
Short name T780
Test name
Test status
Simulation time 25544956 ps
CPU time 0.69 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:49 PM PDT 24
Peak memory 191600 kb
Host smart-816fa53c-2131-4082-bfa9-3de54f8c77ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837579388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2837579388
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1021333287
Short name T830
Test name
Test status
Simulation time 67316269 ps
CPU time 0.82 seconds
Started Apr 16 12:21:52 PM PDT 24
Finished Apr 16 12:21:55 PM PDT 24
Peak memory 197072 kb
Host smart-bfbd5807-d375-407d-9d32-5d50ac3eea65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021333287 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1021333287
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3572016851
Short name T822
Test name
Test status
Simulation time 273843018 ps
CPU time 1.69 seconds
Started Apr 16 12:20:18 PM PDT 24
Finished Apr 16 12:20:21 PM PDT 24
Peak memory 198468 kb
Host smart-73f2d6ff-344f-4678-ad72-fe7f154dfae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572016851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3572016851
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3820682973
Short name T46
Test name
Test status
Simulation time 242872135 ps
CPU time 1.4 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:45 PM PDT 24
Peak memory 196472 kb
Host smart-7b42cf5a-aec8-4cbf-b313-655f6601af6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820682973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3820682973
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.741816274
Short name T737
Test name
Test status
Simulation time 41818019 ps
CPU time 0.74 seconds
Started Apr 16 12:21:04 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 196012 kb
Host smart-2e6be434-5e14-4c91-9d5a-19250adae296
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741816274 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.741816274
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.468206797
Short name T767
Test name
Test status
Simulation time 128469115 ps
CPU time 0.58 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:43 PM PDT 24
Peak memory 194696 kb
Host smart-c712ba7e-3845-4354-88b7-db52eb97aa81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468206797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.468206797
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2710046604
Short name T803
Test name
Test status
Simulation time 11735418 ps
CPU time 0.61 seconds
Started Apr 16 12:18:51 PM PDT 24
Finished Apr 16 12:18:53 PM PDT 24
Peak memory 194288 kb
Host smart-b5c7927e-ba97-4080-b891-f41114c56580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710046604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2710046604
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3441910882
Short name T801
Test name
Test status
Simulation time 164368411 ps
CPU time 3.5 seconds
Started Apr 16 12:20:19 PM PDT 24
Finished Apr 16 12:20:23 PM PDT 24
Peak memory 198068 kb
Host smart-be9b5fee-73f3-486c-98c0-5d274040b71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441910882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3441910882
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.594927620
Short name T38
Test name
Test status
Simulation time 47780539 ps
CPU time 0.86 seconds
Started Apr 16 12:21:40 PM PDT 24
Finished Apr 16 12:21:43 PM PDT 24
Peak memory 197196 kb
Host smart-2f38bd8c-622c-45bc-bbd8-3feb75a2f561
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594927620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.594927620
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1732622859
Short name T738
Test name
Test status
Simulation time 29057805 ps
CPU time 1.42 seconds
Started Apr 16 12:20:17 PM PDT 24
Finished Apr 16 12:20:19 PM PDT 24
Peak memory 198256 kb
Host smart-6699eeea-c42a-4916-8155-ec21878b0702
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732622859 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1732622859
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.107202634
Short name T73
Test name
Test status
Simulation time 38896269 ps
CPU time 0.57 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:45 PM PDT 24
Peak memory 195004 kb
Host smart-c9cfe7a3-4c57-440d-83e6-b4117954948a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107202634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.107202634
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.412764818
Short name T724
Test name
Test status
Simulation time 16674493 ps
CPU time 0.58 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:45 PM PDT 24
Peak memory 193764 kb
Host smart-e32451a3-ae9d-42ac-b8a7-f60b331f3583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412764818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.412764818
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1135817234
Short name T792
Test name
Test status
Simulation time 20842912 ps
CPU time 0.67 seconds
Started Apr 16 12:22:06 PM PDT 24
Finished Apr 16 12:22:09 PM PDT 24
Peak memory 194360 kb
Host smart-87ca9b14-026b-4cc8-a0b2-755c01ce7f94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135817234 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1135817234
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1504322770
Short name T734
Test name
Test status
Simulation time 28066326 ps
CPU time 1.26 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:45 PM PDT 24
Peak memory 196952 kb
Host smart-c11ddc2a-0a24-4096-9125-a9757a88df46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504322770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1504322770
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.681663946
Short name T39
Test name
Test status
Simulation time 138827857 ps
CPU time 1.37 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:47 PM PDT 24
Peak memory 198020 kb
Host smart-dd9ac620-df75-4ead-a330-4cd617f6b52f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681663946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.681663946
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3867279087
Short name T811
Test name
Test status
Simulation time 30299091 ps
CPU time 1.28 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:48 PM PDT 24
Peak memory 196676 kb
Host smart-62e2d23e-5027-44f3-b66a-23c82f7e6fae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867279087 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3867279087
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2040751967
Short name T82
Test name
Test status
Simulation time 136421965 ps
CPU time 0.63 seconds
Started Apr 16 12:19:05 PM PDT 24
Finished Apr 16 12:19:07 PM PDT 24
Peak memory 194392 kb
Host smart-bde359cb-3831-44b5-81d9-e7860e732d3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040751967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2040751967
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1573830337
Short name T740
Test name
Test status
Simulation time 60141056 ps
CPU time 0.62 seconds
Started Apr 16 12:21:04 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 192164 kb
Host smart-3d23e6f7-c6bb-46ea-9a90-9930c8f6c3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573830337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1573830337
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.55965114
Short name T96
Test name
Test status
Simulation time 52002313 ps
CPU time 0.71 seconds
Started Apr 16 12:19:03 PM PDT 24
Finished Apr 16 12:19:04 PM PDT 24
Peak memory 194968 kb
Host smart-06cf24a2-e3bb-4c5c-bfb3-ec10300d66b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55965114 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.gpio_same_csr_outstanding.55965114
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3711957221
Short name T741
Test name
Test status
Simulation time 42290622 ps
CPU time 1.25 seconds
Started Apr 16 12:20:54 PM PDT 24
Finished Apr 16 12:20:56 PM PDT 24
Peak memory 196936 kb
Host smart-5166a3b5-0ade-4fd0-abf5-15e054b91b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711957221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3711957221
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.625422016
Short name T828
Test name
Test status
Simulation time 45703248 ps
CPU time 0.94 seconds
Started Apr 16 12:19:02 PM PDT 24
Finished Apr 16 12:19:03 PM PDT 24
Peak memory 197612 kb
Host smart-f7e5750d-9bdc-4768-9e4c-ff8d741f9d2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625422016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.625422016
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1231555127
Short name T764
Test name
Test status
Simulation time 129299504 ps
CPU time 0.94 seconds
Started Apr 16 12:20:20 PM PDT 24
Finished Apr 16 12:20:22 PM PDT 24
Peak memory 198032 kb
Host smart-13b98e60-66ad-499e-9e58-7be0a860530e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231555127 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1231555127
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2238663510
Short name T763
Test name
Test status
Simulation time 17904172 ps
CPU time 0.58 seconds
Started Apr 16 12:21:18 PM PDT 24
Finished Apr 16 12:21:19 PM PDT 24
Peak memory 193988 kb
Host smart-9941a04a-a478-40b9-b5a4-068840f48868
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238663510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2238663510
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2082906928
Short name T759
Test name
Test status
Simulation time 15146640 ps
CPU time 0.64 seconds
Started Apr 16 12:19:39 PM PDT 24
Finished Apr 16 12:19:40 PM PDT 24
Peak memory 194856 kb
Host smart-40b2ea7c-db6e-4c14-b6d9-d0c898b4ada8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082906928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2082906928
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.310309439
Short name T814
Test name
Test status
Simulation time 122684957 ps
CPU time 0.82 seconds
Started Apr 16 12:21:04 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 194832 kb
Host smart-94895438-f5f7-4d5d-9543-b7e823897dbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310309439 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.310309439
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.314883677
Short name T790
Test name
Test status
Simulation time 36001990 ps
CPU time 1.79 seconds
Started Apr 16 12:19:09 PM PDT 24
Finished Apr 16 12:19:11 PM PDT 24
Peak memory 198084 kb
Host smart-f9f76894-be10-43de-9b09-fc10fae50193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314883677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.314883677
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.155770347
Short name T725
Test name
Test status
Simulation time 35564065 ps
CPU time 0.79 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:54 PM PDT 24
Peak memory 197844 kb
Host smart-d2102245-7b33-49f7-917c-431db7b9d62a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155770347 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.155770347
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2517445570
Short name T799
Test name
Test status
Simulation time 14838329 ps
CPU time 0.56 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 193260 kb
Host smart-610f9e1c-1854-4324-81bd-16c330ce1369
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517445570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2517445570
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.692297853
Short name T835
Test name
Test status
Simulation time 10626586 ps
CPU time 0.63 seconds
Started Apr 16 12:20:51 PM PDT 24
Finished Apr 16 12:20:53 PM PDT 24
Peak memory 191476 kb
Host smart-debc077a-640f-4a9b-9628-f5fa719aaea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692297853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.692297853
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.154945603
Short name T80
Test name
Test status
Simulation time 36061782 ps
CPU time 0.92 seconds
Started Apr 16 12:19:23 PM PDT 24
Finished Apr 16 12:19:25 PM PDT 24
Peak memory 196524 kb
Host smart-e5fe6425-5793-40dc-b02c-057874839b9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154945603 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.154945603
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4057449534
Short name T718
Test name
Test status
Simulation time 732248057 ps
CPU time 2.89 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:55 PM PDT 24
Peak memory 197796 kb
Host smart-50e801ac-c94c-4845-8cb1-9facae184f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057449534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4057449534
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3351085806
Short name T37
Test name
Test status
Simulation time 63300088 ps
CPU time 0.89 seconds
Started Apr 16 12:21:12 PM PDT 24
Finished Apr 16 12:21:14 PM PDT 24
Peak memory 197940 kb
Host smart-a83bfd9b-50ea-429f-9b24-282c8c038e24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351085806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3351085806
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2643886618
Short name T770
Test name
Test status
Simulation time 56342089 ps
CPU time 0.82 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 197540 kb
Host smart-001fb055-2df4-4952-963c-30cb2a16f55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643886618 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2643886618
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.619207349
Short name T97
Test name
Test status
Simulation time 179736813 ps
CPU time 0.68 seconds
Started Apr 16 12:20:51 PM PDT 24
Finished Apr 16 12:20:53 PM PDT 24
Peak memory 193124 kb
Host smart-0a3e3438-1f46-4a3a-abdc-6d9a35cd8126
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619207349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.619207349
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.669263944
Short name T761
Test name
Test status
Simulation time 35712190 ps
CPU time 0.61 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:54 PM PDT 24
Peak memory 193592 kb
Host smart-06b13dee-d05a-42af-9a3a-9da1be8d7e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669263944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.669263944
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1034198853
Short name T74
Test name
Test status
Simulation time 51498179 ps
CPU time 0.71 seconds
Started Apr 16 12:19:31 PM PDT 24
Finished Apr 16 12:19:32 PM PDT 24
Peak memory 195720 kb
Host smart-40142707-69fb-46f6-b32f-bdb336e57a63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034198853 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1034198853
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2049017582
Short name T747
Test name
Test status
Simulation time 90249490 ps
CPU time 1.89 seconds
Started Apr 16 12:20:52 PM PDT 24
Finished Apr 16 12:20:55 PM PDT 24
Peak memory 197708 kb
Host smart-2f2fa33e-91dc-4e56-b20c-143370109a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049017582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2049017582
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2731695538
Short name T49
Test name
Test status
Simulation time 526556449 ps
CPU time 1.34 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:54 PM PDT 24
Peak memory 197816 kb
Host smart-b977a3bd-5e5b-46f6-8038-94d8bf69769c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731695538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2731695538
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.646535208
Short name T750
Test name
Test status
Simulation time 66145247 ps
CPU time 1.09 seconds
Started Apr 16 12:19:31 PM PDT 24
Finished Apr 16 12:19:33 PM PDT 24
Peak memory 197932 kb
Host smart-0a6cbf64-bb50-4f44-a6a4-3441415a6a73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646535208 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.646535208
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.813367951
Short name T781
Test name
Test status
Simulation time 16371509 ps
CPU time 0.57 seconds
Started Apr 16 12:22:57 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 193652 kb
Host smart-b796bfb4-f1a2-4806-a656-a4c0cd39b94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813367951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.813367951
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1246349874
Short name T753
Test name
Test status
Simulation time 72058386 ps
CPU time 0.83 seconds
Started Apr 16 12:20:51 PM PDT 24
Finished Apr 16 12:20:53 PM PDT 24
Peak memory 194416 kb
Host smart-51e52ada-1c24-4a3e-a666-3a4c076def72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246349874 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1246349874
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.952202177
Short name T832
Test name
Test status
Simulation time 82626264 ps
CPU time 2.16 seconds
Started Apr 16 12:22:42 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 196988 kb
Host smart-57947364-fee1-4e91-8f4b-ddaada57bc2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952202177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.952202177
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3887994582
Short name T823
Test name
Test status
Simulation time 460153274 ps
CPU time 1.38 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 197684 kb
Host smart-4acd4476-2e6b-41da-8c3a-fedb2699e6e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887994582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3887994582
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2851705441
Short name T779
Test name
Test status
Simulation time 37846271 ps
CPU time 1.8 seconds
Started Apr 16 12:19:38 PM PDT 24
Finished Apr 16 12:19:40 PM PDT 24
Peak memory 198264 kb
Host smart-d440bb0e-4712-4760-8d2d-9ca13fa891fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851705441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2851705441
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2433109933
Short name T89
Test name
Test status
Simulation time 58568054 ps
CPU time 0.62 seconds
Started Apr 16 12:19:35 PM PDT 24
Finished Apr 16 12:19:36 PM PDT 24
Peak memory 194580 kb
Host smart-a69e75f5-7a3c-461a-a8fb-cae2a317865f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433109933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2433109933
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3795786409
Short name T831
Test name
Test status
Simulation time 41742740 ps
CPU time 0.56 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 193392 kb
Host smart-385361dd-4302-4c37-a02e-5669a90c568d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795786409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3795786409
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2689709608
Short name T817
Test name
Test status
Simulation time 30595503 ps
CPU time 0.77 seconds
Started Apr 16 12:20:56 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195808 kb
Host smart-1222b63c-caf6-4892-bf38-b8d0086147bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689709608 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2689709608
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1370967959
Short name T743
Test name
Test status
Simulation time 103096673 ps
CPU time 1.82 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 197632 kb
Host smart-6d51cc5f-dbda-4fd3-aba5-9d8f21ba5b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370967959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1370967959
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.4204828
Short name T807
Test name
Test status
Simulation time 155029890 ps
CPU time 0.93 seconds
Started Apr 16 12:19:35 PM PDT 24
Finished Apr 16 12:19:37 PM PDT 24
Peak memory 197216 kb
Host smart-a1c64f2d-2be7-4db2-91aa-38192fe26957
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.gpio_tl_intg_err.4204828
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2846015999
Short name T813
Test name
Test status
Simulation time 56637181 ps
CPU time 0.78 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195904 kb
Host smart-dad3600f-c1b3-42d5-8055-c10e1083c7d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846015999 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2846015999
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4090889812
Short name T90
Test name
Test status
Simulation time 12613508 ps
CPU time 0.63 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 194732 kb
Host smart-4fed3b38-7c41-4115-b81d-a68aeacdd531
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090889812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4090889812
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2481310066
Short name T794
Test name
Test status
Simulation time 41080292 ps
CPU time 0.59 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 193384 kb
Host smart-a0c00785-3200-47ba-95f7-595cc9e1514a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481310066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2481310066
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3936030102
Short name T72
Test name
Test status
Simulation time 219808314 ps
CPU time 0.74 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 194828 kb
Host smart-1620cdcc-fded-41e7-8ab8-a3145e5c3307
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936030102 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3936030102
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.989508693
Short name T731
Test name
Test status
Simulation time 383167560 ps
CPU time 2.17 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:15 PM PDT 24
Peak memory 197752 kb
Host smart-2e080b9f-84ff-4db5-8115-571c6ec97172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989508693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.989508693
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.636860763
Short name T51
Test name
Test status
Simulation time 75204017 ps
CPU time 0.85 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:01 PM PDT 24
Peak memory 197612 kb
Host smart-74ac5509-1920-4a1e-9311-4a4a66b0b83b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636860763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.636860763
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.356346479
Short name T715
Test name
Test status
Simulation time 25317150 ps
CPU time 0.64 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 196664 kb
Host smart-515bebe4-e1e9-4505-a050-073b41506468
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356346479 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.356346479
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1910952894
Short name T87
Test name
Test status
Simulation time 33196005 ps
CPU time 0.57 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195196 kb
Host smart-5100e371-721e-4a75-b698-89050072d6b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910952894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1910952894
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.639021762
Short name T821
Test name
Test status
Simulation time 13026996 ps
CPU time 0.6 seconds
Started Apr 16 12:19:49 PM PDT 24
Finished Apr 16 12:19:51 PM PDT 24
Peak memory 193768 kb
Host smart-fe236582-b68a-4cdd-bacf-7a98abc6737e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639021762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.639021762
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3254369700
Short name T93
Test name
Test status
Simulation time 65540510 ps
CPU time 0.71 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:01 PM PDT 24
Peak memory 194508 kb
Host smart-68d7a177-714e-4762-b7b0-461a2d7eda37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254369700 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3254369700
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3865033818
Short name T766
Test name
Test status
Simulation time 39730948 ps
CPU time 1.68 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 197816 kb
Host smart-5b87848c-dec6-4b46-8489-c650c0891312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865033818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3865033818
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2608519846
Short name T789
Test name
Test status
Simulation time 38664079 ps
CPU time 0.82 seconds
Started Apr 16 12:21:07 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 196736 kb
Host smart-a69f2091-e229-4d22-8edf-b477a19e3d45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608519846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2608519846
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3905863265
Short name T77
Test name
Test status
Simulation time 42252355 ps
CPU time 0.86 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 194552 kb
Host smart-af2a49dc-59aa-4247-8fba-f500ad0dbaff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905863265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3905863265
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3266734946
Short name T783
Test name
Test status
Simulation time 139778204 ps
CPU time 1.56 seconds
Started Apr 16 12:17:58 PM PDT 24
Finished Apr 16 12:18:01 PM PDT 24
Peak memory 197096 kb
Host smart-ae80d29b-5779-44fc-9505-0932704a5de8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266734946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3266734946
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2402074059
Short name T84
Test name
Test status
Simulation time 20054063 ps
CPU time 0.61 seconds
Started Apr 16 12:21:49 PM PDT 24
Finished Apr 16 12:21:52 PM PDT 24
Peak memory 194484 kb
Host smart-454febc7-19be-488e-bd79-e94a7edb9032
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402074059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2402074059
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1054787487
Short name T808
Test name
Test status
Simulation time 23039376 ps
CPU time 0.76 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 195376 kb
Host smart-c8b09afa-0a9b-473c-a345-0469cf872c74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054787487 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1054787487
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3103039157
Short name T75
Test name
Test status
Simulation time 13707772 ps
CPU time 0.64 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:49 PM PDT 24
Peak memory 193116 kb
Host smart-677710c2-d8e9-4f34-8f9a-4c780a44f9cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103039157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3103039157
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2957914072
Short name T748
Test name
Test status
Simulation time 42651016 ps
CPU time 0.58 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 193772 kb
Host smart-6439c3f1-f285-4822-b36e-979ea2e55ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957914072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2957914072
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.779399344
Short name T798
Test name
Test status
Simulation time 28122905 ps
CPU time 0.71 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:49 PM PDT 24
Peak memory 193796 kb
Host smart-3dc08279-ee6a-43bf-a065-c28daa8baaa4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779399344 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.779399344
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1791941606
Short name T787
Test name
Test status
Simulation time 102473215 ps
CPU time 1.17 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 194620 kb
Host smart-d76c60ff-2fc0-4c0e-9111-7d54a7fab29f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791941606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1791941606
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2751796269
Short name T795
Test name
Test status
Simulation time 86418420 ps
CPU time 1.19 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 195172 kb
Host smart-1f5ac7e4-bf61-46ea-a6c7-f4f3b6fb389f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751796269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2751796269
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3360726802
Short name T739
Test name
Test status
Simulation time 31869495 ps
CPU time 0.6 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:08 PM PDT 24
Peak memory 194068 kb
Host smart-a0d7f540-74f1-41fa-af1e-39bf60c6a505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360726802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3360726802
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1916601462
Short name T732
Test name
Test status
Simulation time 177835903 ps
CPU time 0.61 seconds
Started Apr 16 12:21:08 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 192284 kb
Host smart-1af95e31-98f8-43ce-a389-17c89c55bfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916601462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1916601462
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1964788637
Short name T727
Test name
Test status
Simulation time 39898192 ps
CPU time 0.56 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 193404 kb
Host smart-84bedc66-1d50-421d-93e1-fac2c08d2d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964788637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1964788637
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2118028583
Short name T730
Test name
Test status
Simulation time 13249809 ps
CPU time 0.56 seconds
Started Apr 16 12:21:07 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 193480 kb
Host smart-ccecc888-0249-4463-abe4-730d238f1732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118028583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2118028583
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1880258802
Short name T716
Test name
Test status
Simulation time 32022903 ps
CPU time 0.61 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:08 PM PDT 24
Peak memory 193372 kb
Host smart-c9a89bf3-d10b-4295-8ff8-cca0d9640599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880258802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1880258802
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1640783196
Short name T726
Test name
Test status
Simulation time 30846587 ps
CPU time 0.63 seconds
Started Apr 16 12:21:08 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 192292 kb
Host smart-5f61a499-12ab-4bdd-ae60-bee1480217ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640783196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1640783196
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1597200574
Short name T771
Test name
Test status
Simulation time 17532814 ps
CPU time 0.62 seconds
Started Apr 16 12:21:13 PM PDT 24
Finished Apr 16 12:21:15 PM PDT 24
Peak memory 193740 kb
Host smart-349b6537-5088-474b-b785-6f117a9937b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597200574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1597200574
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2004873610
Short name T735
Test name
Test status
Simulation time 28530885 ps
CPU time 0.58 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 192588 kb
Host smart-283ab83f-c638-4d08-9bd8-1e50dd8b49a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004873610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2004873610
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1612817698
Short name T775
Test name
Test status
Simulation time 37997502 ps
CPU time 0.56 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 194024 kb
Host smart-4eec96cb-535f-435a-a40c-bdeb45db8155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612817698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1612817698
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.133768213
Short name T791
Test name
Test status
Simulation time 30151836 ps
CPU time 0.61 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:08 PM PDT 24
Peak memory 192724 kb
Host smart-959b5033-3f3b-4648-8ee6-06c2fb539aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133768213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.133768213
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3758884685
Short name T782
Test name
Test status
Simulation time 94541277 ps
CPU time 0.74 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:48 PM PDT 24
Peak memory 196408 kb
Host smart-a76c2da9-1b4c-4bcc-a790-b61353f89cb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758884685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3758884685
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1776362520
Short name T88
Test name
Test status
Simulation time 514617837 ps
CPU time 2.37 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 196264 kb
Host smart-09c894b0-8084-495f-95c9-b06bb1a647eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776362520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1776362520
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2854217119
Short name T98
Test name
Test status
Simulation time 18745400 ps
CPU time 0.63 seconds
Started Apr 16 12:21:46 PM PDT 24
Finished Apr 16 12:21:49 PM PDT 24
Peak memory 194652 kb
Host smart-e01abca0-3d02-440a-b16c-2f3c53141306
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854217119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2854217119
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4093239473
Short name T714
Test name
Test status
Simulation time 31796961 ps
CPU time 0.98 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:05 PM PDT 24
Peak memory 196028 kb
Host smart-b50baf13-12be-4a04-b6dc-eea192beb8a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093239473 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4093239473
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3068630658
Short name T816
Test name
Test status
Simulation time 13249662 ps
CPU time 0.63 seconds
Started Apr 16 12:19:51 PM PDT 24
Finished Apr 16 12:19:52 PM PDT 24
Peak memory 195160 kb
Host smart-f453fc3a-5eec-4e99-bd3e-977918c13730
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068630658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3068630658
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3296840654
Short name T729
Test name
Test status
Simulation time 44915184 ps
CPU time 0.61 seconds
Started Apr 16 12:21:46 PM PDT 24
Finished Apr 16 12:21:49 PM PDT 24
Peak memory 193488 kb
Host smart-e0b6cbdc-16b1-4f07-9126-52382df18e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296840654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3296840654
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.953617101
Short name T818
Test name
Test status
Simulation time 41243492 ps
CPU time 0.7 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 192984 kb
Host smart-d67f7d91-5667-4da6-8456-aa78fd3b83c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953617101 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.953617101
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1533201722
Short name T827
Test name
Test status
Simulation time 1815288856 ps
CPU time 2.67 seconds
Started Apr 16 12:21:31 PM PDT 24
Finished Apr 16 12:21:35 PM PDT 24
Peak memory 198060 kb
Host smart-cf2727e8-09cc-473e-9531-94c7c475646d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533201722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1533201722
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3423717496
Short name T788
Test name
Test status
Simulation time 227889372 ps
CPU time 1.44 seconds
Started Apr 16 12:21:00 PM PDT 24
Finished Apr 16 12:21:03 PM PDT 24
Peak memory 197768 kb
Host smart-f4557963-0024-4770-aeff-ce4afef2b1ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423717496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3423717496
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.62245362
Short name T744
Test name
Test status
Simulation time 24583906 ps
CPU time 0.59 seconds
Started Apr 16 12:21:14 PM PDT 24
Finished Apr 16 12:21:17 PM PDT 24
Peak memory 192044 kb
Host smart-d0e26aa0-8ffd-460a-975b-1e8bccaf6719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62245362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.62245362
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.252602787
Short name T824
Test name
Test status
Simulation time 21433587 ps
CPU time 0.57 seconds
Started Apr 16 12:21:14 PM PDT 24
Finished Apr 16 12:21:17 PM PDT 24
Peak memory 193140 kb
Host smart-0a5f8dbb-8de1-4a86-b032-57add521bda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252602787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.252602787
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3511667939
Short name T742
Test name
Test status
Simulation time 14936171 ps
CPU time 0.6 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 194228 kb
Host smart-08626b96-f4d5-461a-b3f2-83a5d737ea1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511667939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3511667939
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4256062925
Short name T728
Test name
Test status
Simulation time 52218168 ps
CPU time 0.6 seconds
Started Apr 16 12:21:14 PM PDT 24
Finished Apr 16 12:21:17 PM PDT 24
Peak memory 193228 kb
Host smart-24dbbdd4-0c91-46ae-bfe3-ec06b004f643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256062925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4256062925
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3282090653
Short name T721
Test name
Test status
Simulation time 20818652 ps
CPU time 0.55 seconds
Started Apr 16 12:21:14 PM PDT 24
Finished Apr 16 12:21:17 PM PDT 24
Peak memory 192608 kb
Host smart-6d8e8f4c-0830-4120-9ce6-030da97e0605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282090653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3282090653
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3664205456
Short name T826
Test name
Test status
Simulation time 23266996 ps
CPU time 0.62 seconds
Started Apr 16 12:20:01 PM PDT 24
Finished Apr 16 12:20:02 PM PDT 24
Peak memory 193864 kb
Host smart-36440eb2-e2b8-461b-a30e-70ca8285e2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664205456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3664205456
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.831304584
Short name T796
Test name
Test status
Simulation time 50502003 ps
CPU time 0.61 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:47 PM PDT 24
Peak memory 192592 kb
Host smart-9f8163f7-455d-4b41-86bd-565f8f446b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831304584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.831304584
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4015396023
Short name T774
Test name
Test status
Simulation time 20174094 ps
CPU time 0.6 seconds
Started Apr 16 12:20:05 PM PDT 24
Finished Apr 16 12:20:07 PM PDT 24
Peak memory 194308 kb
Host smart-65e11c87-13e4-4ef2-a0f6-1ee5105630b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015396023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4015396023
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1733774257
Short name T819
Test name
Test status
Simulation time 56395263 ps
CPU time 0.58 seconds
Started Apr 16 12:21:25 PM PDT 24
Finished Apr 16 12:21:28 PM PDT 24
Peak memory 194372 kb
Host smart-8833026d-e464-4073-8f8d-000e2bfbea8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733774257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1733774257
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2655134319
Short name T777
Test name
Test status
Simulation time 36240714 ps
CPU time 0.6 seconds
Started Apr 16 12:21:27 PM PDT 24
Finished Apr 16 12:21:29 PM PDT 24
Peak memory 193660 kb
Host smart-b8e1f806-a7d6-4663-8517-08b8f6554622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655134319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2655134319
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.4031158010
Short name T85
Test name
Test status
Simulation time 50664151 ps
CPU time 0.71 seconds
Started Apr 16 12:20:59 PM PDT 24
Finished Apr 16 12:21:02 PM PDT 24
Peak memory 195360 kb
Host smart-7e5a2324-629c-48b1-b8ec-883bdb23175f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031158010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.4031158010
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3256399300
Short name T752
Test name
Test status
Simulation time 1012417979 ps
CPU time 3.24 seconds
Started Apr 16 12:19:50 PM PDT 24
Finished Apr 16 12:19:54 PM PDT 24
Peak memory 196844 kb
Host smart-b7693032-f03f-452f-9b02-bb77f949765a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256399300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3256399300
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1071769754
Short name T785
Test name
Test status
Simulation time 40622754 ps
CPU time 0.57 seconds
Started Apr 16 12:21:44 PM PDT 24
Finished Apr 16 12:21:48 PM PDT 24
Peak memory 194236 kb
Host smart-b8d8be25-a43b-45af-93ad-d6cae08c5c8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071769754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1071769754
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.4148039928
Short name T778
Test name
Test status
Simulation time 60729728 ps
CPU time 1.39 seconds
Started Apr 16 12:20:33 PM PDT 24
Finished Apr 16 12:20:35 PM PDT 24
Peak memory 198520 kb
Host smart-5dea9cff-9e23-4174-b255-9fee859692e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148039928 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.4148039928
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3880453802
Short name T71
Test name
Test status
Simulation time 58355654 ps
CPU time 0.67 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:48 PM PDT 24
Peak memory 192788 kb
Host smart-69f18ba9-44e8-491c-9e22-b0f3de4c122c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880453802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3880453802
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.691310253
Short name T736
Test name
Test status
Simulation time 42290973 ps
CPU time 0.63 seconds
Started Apr 16 12:21:50 PM PDT 24
Finished Apr 16 12:21:54 PM PDT 24
Peak memory 192044 kb
Host smart-63b37540-c765-45f4-ad5d-69dfc7f9a3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691310253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.691310253
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4246464698
Short name T91
Test name
Test status
Simulation time 136889703 ps
CPU time 0.89 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:49 PM PDT 24
Peak memory 194252 kb
Host smart-c3881975-0ce5-400a-a522-844584332904
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246464698 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4246464698
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2896763918
Short name T755
Test name
Test status
Simulation time 167018503 ps
CPU time 1.96 seconds
Started Apr 16 12:21:50 PM PDT 24
Finished Apr 16 12:21:55 PM PDT 24
Peak memory 196432 kb
Host smart-1b67b72d-a4ee-4ec2-925b-b04dbc02094b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896763918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2896763918
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2466231986
Short name T754
Test name
Test status
Simulation time 37084120 ps
CPU time 0.62 seconds
Started Apr 16 12:20:07 PM PDT 24
Finished Apr 16 12:20:09 PM PDT 24
Peak memory 194412 kb
Host smart-b630b14a-71b0-474c-ae6b-905e599b7b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466231986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2466231986
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1310592314
Short name T800
Test name
Test status
Simulation time 11361700 ps
CPU time 0.63 seconds
Started Apr 16 12:20:05 PM PDT 24
Finished Apr 16 12:20:07 PM PDT 24
Peak memory 193656 kb
Host smart-90473448-e2a4-4fd7-abbc-d95893c1a246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310592314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1310592314
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.780030633
Short name T786
Test name
Test status
Simulation time 16158637 ps
CPU time 0.57 seconds
Started Apr 16 12:21:26 PM PDT 24
Finished Apr 16 12:21:29 PM PDT 24
Peak memory 194324 kb
Host smart-750a0120-fea6-409b-bba8-323ecaf775b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780030633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.780030633
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3302309207
Short name T810
Test name
Test status
Simulation time 21828897 ps
CPU time 0.61 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 192848 kb
Host smart-ed22328e-0e4a-4deb-a8f9-f6f0cd10920f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302309207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3302309207
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1668156030
Short name T768
Test name
Test status
Simulation time 17070795 ps
CPU time 0.65 seconds
Started Apr 16 12:20:08 PM PDT 24
Finished Apr 16 12:20:10 PM PDT 24
Peak memory 193916 kb
Host smart-624b7d4f-e1ba-42b9-9991-87f1e72e35b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668156030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1668156030
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2137833935
Short name T733
Test name
Test status
Simulation time 13928333 ps
CPU time 0.56 seconds
Started Apr 16 12:21:31 PM PDT 24
Finished Apr 16 12:21:33 PM PDT 24
Peak memory 193788 kb
Host smart-c3c33378-a5da-4a01-b950-cce6cbd69d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137833935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2137833935
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.21498088
Short name T719
Test name
Test status
Simulation time 13654133 ps
CPU time 0.6 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:43 PM PDT 24
Peak memory 193764 kb
Host smart-aa6d892c-5a01-4517-a5ac-d9fdd6348fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.21498088
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.140787764
Short name T833
Test name
Test status
Simulation time 14071188 ps
CPU time 0.57 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:43 PM PDT 24
Peak memory 193664 kb
Host smart-2a48f1c1-e944-4a19-9fc3-176492abdcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140787764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.140787764
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2921515375
Short name T772
Test name
Test status
Simulation time 20150181 ps
CPU time 0.65 seconds
Started Apr 16 12:20:08 PM PDT 24
Finished Apr 16 12:20:10 PM PDT 24
Peak memory 193852 kb
Host smart-bafa641f-870d-4fdb-bb67-2a15f456281a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921515375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2921515375
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.633050610
Short name T829
Test name
Test status
Simulation time 14084630 ps
CPU time 0.61 seconds
Started Apr 16 12:20:18 PM PDT 24
Finished Apr 16 12:20:20 PM PDT 24
Peak memory 194180 kb
Host smart-340e2cbc-b779-4339-890e-955f4084fb95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633050610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.633050610
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.387061476
Short name T760
Test name
Test status
Simulation time 22361712 ps
CPU time 0.86 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 195868 kb
Host smart-f5f2494f-eb96-46eb-a2f8-5598f88ae171
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387061476 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.387061476
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3600163976
Short name T757
Test name
Test status
Simulation time 30939654 ps
CPU time 0.55 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 193028 kb
Host smart-5b74acb9-1498-48e8-86f2-ab671994e33a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600163976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3600163976
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1217416803
Short name T784
Test name
Test status
Simulation time 41829803 ps
CPU time 0.6 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 192836 kb
Host smart-1339d53f-619c-4410-a842-b82a887a9241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217416803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1217416803
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1556264718
Short name T758
Test name
Test status
Simulation time 26176763 ps
CPU time 0.65 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 193260 kb
Host smart-83401012-77f2-4385-bcef-31acecb7a9ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556264718 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1556264718
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1627582307
Short name T722
Test name
Test status
Simulation time 202515675 ps
CPU time 2.41 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:48 PM PDT 24
Peak memory 198052 kb
Host smart-34b2916a-47fe-4323-a60a-689eb688cc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627582307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1627582307
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4079186451
Short name T47
Test name
Test status
Simulation time 77542339 ps
CPU time 0.92 seconds
Started Apr 16 12:22:24 PM PDT 24
Finished Apr 16 12:22:27 PM PDT 24
Peak memory 195804 kb
Host smart-def75331-7901-45f0-ad6a-0b88c38c8a9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079186451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4079186451
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2361498251
Short name T809
Test name
Test status
Simulation time 37109306 ps
CPU time 1.75 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 195316 kb
Host smart-b92bcd5a-b38a-4b74-8c5e-c3d7f5ff4482
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361498251 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2361498251
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1612871847
Short name T83
Test name
Test status
Simulation time 16857463 ps
CPU time 0.64 seconds
Started Apr 16 12:21:21 PM PDT 24
Finished Apr 16 12:21:23 PM PDT 24
Peak memory 194924 kb
Host smart-8decf4c2-0275-44f8-97bd-1a0039064495
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612871847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1612871847
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.40462318
Short name T812
Test name
Test status
Simulation time 12230320 ps
CPU time 0.58 seconds
Started Apr 16 12:21:01 PM PDT 24
Finished Apr 16 12:21:03 PM PDT 24
Peak memory 193912 kb
Host smart-e3d18127-f781-432c-bc24-36331e144fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.40462318
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3825585734
Short name T92
Test name
Test status
Simulation time 50726494 ps
CPU time 0.7 seconds
Started Apr 16 12:22:47 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 192884 kb
Host smart-2847f9aa-d91d-48e0-b4f3-861005e60a49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825585734 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3825585734
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4038574889
Short name T723
Test name
Test status
Simulation time 120818933 ps
CPU time 1.6 seconds
Started Apr 16 12:21:54 PM PDT 24
Finished Apr 16 12:21:58 PM PDT 24
Peak memory 198132 kb
Host smart-4da29db6-793c-4910-8b1b-7e159222a9d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038574889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4038574889
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.247634950
Short name T805
Test name
Test status
Simulation time 127602498 ps
CPU time 0.82 seconds
Started Apr 16 12:21:34 PM PDT 24
Finished Apr 16 12:21:36 PM PDT 24
Peak memory 197352 kb
Host smart-a833fa2b-6188-4d5f-9a45-4a73ff659457
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247634950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.247634950
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4054411577
Short name T773
Test name
Test status
Simulation time 66378479 ps
CPU time 0.87 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:04 PM PDT 24
Peak memory 197732 kb
Host smart-29564201-c543-450e-aa81-9c55f4232993
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054411577 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4054411577
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.308081884
Short name T806
Test name
Test status
Simulation time 15511768 ps
CPU time 0.61 seconds
Started Apr 16 12:22:06 PM PDT 24
Finished Apr 16 12:22:09 PM PDT 24
Peak memory 194728 kb
Host smart-47a6ae89-23a0-41b7-a2a9-f7ccde22b71d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308081884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.308081884
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.870853565
Short name T769
Test name
Test status
Simulation time 88974389 ps
CPU time 0.62 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 191616 kb
Host smart-d7a83656-221b-44e0-8d89-bed7730e394a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870853565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.870853565
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.332587220
Short name T79
Test name
Test status
Simulation time 37603113 ps
CPU time 0.85 seconds
Started Apr 16 12:21:01 PM PDT 24
Finished Apr 16 12:21:03 PM PDT 24
Peak memory 195356 kb
Host smart-fcd390ad-3276-42d2-b9e1-910b8d947111
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332587220 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.332587220
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2497790950
Short name T804
Test name
Test status
Simulation time 175414974 ps
CPU time 1.95 seconds
Started Apr 16 12:20:18 PM PDT 24
Finished Apr 16 12:20:21 PM PDT 24
Peak memory 197860 kb
Host smart-52359197-be22-4458-b561-e7d61523a6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497790950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2497790950
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.986129795
Short name T717
Test name
Test status
Simulation time 114781372 ps
CPU time 0.86 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 196188 kb
Host smart-63488f8a-01db-4b3e-ad26-9808b4dc41ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986129795 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.986129795
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.234243018
Short name T793
Test name
Test status
Simulation time 14321714 ps
CPU time 0.65 seconds
Started Apr 16 12:18:51 PM PDT 24
Finished Apr 16 12:18:53 PM PDT 24
Peak memory 195072 kb
Host smart-9793a335-fa2f-4863-8bdb-c513bfffe8b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234243018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.234243018
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1600559435
Short name T749
Test name
Test status
Simulation time 12162732 ps
CPU time 0.59 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 193272 kb
Host smart-918ad018-62e7-4b12-b2af-29847bb59df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600559435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1600559435
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2932439687
Short name T95
Test name
Test status
Simulation time 26884186 ps
CPU time 0.87 seconds
Started Apr 16 12:21:19 PM PDT 24
Finished Apr 16 12:21:21 PM PDT 24
Peak memory 195404 kb
Host smart-9acea7d5-9cd9-4076-8d26-d820d1464241
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932439687 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2932439687
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2274180526
Short name T745
Test name
Test status
Simulation time 549728959 ps
CPU time 2.35 seconds
Started Apr 16 12:21:19 PM PDT 24
Finished Apr 16 12:21:23 PM PDT 24
Peak memory 196536 kb
Host smart-f02e78e4-e10f-47cd-8dfb-b9a83c3af667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274180526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2274180526
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3689771542
Short name T825
Test name
Test status
Simulation time 42170836 ps
CPU time 0.83 seconds
Started Apr 16 12:21:31 PM PDT 24
Finished Apr 16 12:21:33 PM PDT 24
Peak memory 197280 kb
Host smart-bbefe921-692f-4e12-b622-8b6b55c0ca13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689771542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3689771542
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1267475867
Short name T797
Test name
Test status
Simulation time 41845655 ps
CPU time 0.93 seconds
Started Apr 16 12:21:19 PM PDT 24
Finished Apr 16 12:21:21 PM PDT 24
Peak memory 196528 kb
Host smart-aa95a98d-42aa-40b0-b6db-d98a3259c26e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267475867 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1267475867
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1210137684
Short name T837
Test name
Test status
Simulation time 27894216 ps
CPU time 0.59 seconds
Started Apr 16 12:18:50 PM PDT 24
Finished Apr 16 12:18:51 PM PDT 24
Peak memory 194728 kb
Host smart-fd002569-9d87-475d-ba85-37ef256f9c94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210137684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1210137684
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4128948252
Short name T765
Test name
Test status
Simulation time 45929741 ps
CPU time 0.59 seconds
Started Apr 16 12:21:43 PM PDT 24
Finished Apr 16 12:21:46 PM PDT 24
Peak memory 194396 kb
Host smart-e5fefc98-e95f-48c6-ab33-6729bd6359bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128948252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4128948252
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2519391107
Short name T834
Test name
Test status
Simulation time 319459747 ps
CPU time 0.91 seconds
Started Apr 16 12:18:50 PM PDT 24
Finished Apr 16 12:18:52 PM PDT 24
Peak memory 196364 kb
Host smart-78d5a499-d8b1-4761-9fdc-1065707fed17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519391107 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2519391107
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.82553134
Short name T838
Test name
Test status
Simulation time 52936410 ps
CPU time 2.65 seconds
Started Apr 16 12:19:53 PM PDT 24
Finished Apr 16 12:19:57 PM PDT 24
Peak memory 198132 kb
Host smart-4db73948-1213-40c9-947e-66c02288034e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82553134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.82553134
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1957670200
Short name T99
Test name
Test status
Simulation time 511818030 ps
CPU time 1.33 seconds
Started Apr 16 12:21:31 PM PDT 24
Finished Apr 16 12:21:33 PM PDT 24
Peak memory 198000 kb
Host smart-0b66c215-22be-468b-a502-c3ecdf035c8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957670200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1957670200
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3112311111
Short name T362
Test name
Test status
Simulation time 39495215 ps
CPU time 0.57 seconds
Started Apr 16 12:17:55 PM PDT 24
Finished Apr 16 12:17:56 PM PDT 24
Peak memory 194636 kb
Host smart-1953cced-b8b2-4067-abf3-b313307a96d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112311111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3112311111
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4163504575
Short name T291
Test name
Test status
Simulation time 14313406 ps
CPU time 0.6 seconds
Started Apr 16 12:21:13 PM PDT 24
Finished Apr 16 12:21:15 PM PDT 24
Peak memory 193084 kb
Host smart-980cf142-1d1e-4450-865f-4e6ca2343b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163504575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4163504575
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2772635283
Short name T352
Test name
Test status
Simulation time 1326119632 ps
CPU time 19.36 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:18 PM PDT 24
Peak memory 195652 kb
Host smart-cacc4f91-6f41-4e68-b6e9-5a65b4e5edc4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772635283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2772635283
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.4160707245
Short name T152
Test name
Test status
Simulation time 352865018 ps
CPU time 0.99 seconds
Started Apr 16 12:21:44 PM PDT 24
Finished Apr 16 12:21:48 PM PDT 24
Peak memory 198292 kb
Host smart-107f9890-bf1f-4045-a435-0277a37f1768
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160707245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.4160707245
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1854330863
Short name T118
Test name
Test status
Simulation time 232564980 ps
CPU time 1.34 seconds
Started Apr 16 12:18:35 PM PDT 24
Finished Apr 16 12:18:38 PM PDT 24
Peak memory 196460 kb
Host smart-1a0e5913-9415-41ff-9410-54917b2744a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854330863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1854330863
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2799213543
Short name T176
Test name
Test status
Simulation time 238707486 ps
CPU time 2.46 seconds
Started Apr 16 12:18:10 PM PDT 24
Finished Apr 16 12:18:13 PM PDT 24
Peak memory 197944 kb
Host smart-cc30c34d-770e-4a6f-b96f-ed254b265a63
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799213543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2799213543
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.618289785
Short name T614
Test name
Test status
Simulation time 281669952 ps
CPU time 3.4 seconds
Started Apr 16 12:18:38 PM PDT 24
Finished Apr 16 12:18:43 PM PDT 24
Peak memory 197532 kb
Host smart-c1562ecd-12b0-4a35-9323-5a88e8149041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618289785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.618289785
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3877589232
Short name T124
Test name
Test status
Simulation time 119199815 ps
CPU time 1.24 seconds
Started Apr 16 12:21:16 PM PDT 24
Finished Apr 16 12:21:18 PM PDT 24
Peak memory 195864 kb
Host smart-553c2c70-e561-4809-a8ce-b13e232ed927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877589232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3877589232
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1872761325
Short name T272
Test name
Test status
Simulation time 111865731 ps
CPU time 1.34 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:48 PM PDT 24
Peak memory 195140 kb
Host smart-4fbf08cf-6ab0-4f7a-bd6f-f9edb1fc802d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872761325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1872761325
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.587229397
Short name T324
Test name
Test status
Simulation time 339495473 ps
CPU time 3.1 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:06 PM PDT 24
Peak memory 198380 kb
Host smart-4e1e5d82-c1d3-45a7-a8fd-55d40b2815a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587229397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.587229397
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3199156964
Short name T56
Test name
Test status
Simulation time 191572222 ps
CPU time 0.85 seconds
Started Apr 16 12:20:51 PM PDT 24
Finished Apr 16 12:20:53 PM PDT 24
Peak memory 212700 kb
Host smart-28ddfe66-1365-4475-9f19-3947ba805172
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199156964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3199156964
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1147903400
Short name T399
Test name
Test status
Simulation time 58217635 ps
CPU time 0.83 seconds
Started Apr 16 12:21:12 PM PDT 24
Finished Apr 16 12:21:14 PM PDT 24
Peak memory 195608 kb
Host smart-790510c2-5342-4668-ad72-51a83e2554f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147903400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1147903400
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.5414828
Short name T709
Test name
Test status
Simulation time 281184072 ps
CPU time 1.34 seconds
Started Apr 16 12:22:41 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 196520 kb
Host smart-f61f1389-73f6-483f-9fb6-1f7d655b35ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5414828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.5414828
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.558508711
Short name T510
Test name
Test status
Simulation time 11864891678 ps
CPU time 161.21 seconds
Started Apr 16 12:19:26 PM PDT 24
Finished Apr 16 12:22:08 PM PDT 24
Peak memory 198140 kb
Host smart-3e64e4fc-e9ea-4287-8c9a-ee5c9a2f7281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558508711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.558508711
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4075529520
Short name T692
Test name
Test status
Simulation time 13692091 ps
CPU time 0.57 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 193604 kb
Host smart-94329e22-6f9d-4115-a9fc-e430812f5274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075529520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4075529520
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.545027769
Short name T685
Test name
Test status
Simulation time 37336580 ps
CPU time 0.76 seconds
Started Apr 16 12:19:05 PM PDT 24
Finished Apr 16 12:19:07 PM PDT 24
Peak memory 194816 kb
Host smart-770013fe-d319-40b0-8890-e088ffbb1378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545027769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.545027769
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.266910603
Short name T702
Test name
Test status
Simulation time 686197644 ps
CPU time 6.14 seconds
Started Apr 16 12:20:56 PM PDT 24
Finished Apr 16 12:21:04 PM PDT 24
Peak memory 194548 kb
Host smart-98970340-47ae-46ca-9c78-882e3d2ed3fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266910603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.266910603
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2196546746
Short name T273
Test name
Test status
Simulation time 97507212 ps
CPU time 1.06 seconds
Started Apr 16 12:20:59 PM PDT 24
Finished Apr 16 12:21:02 PM PDT 24
Peak memory 195532 kb
Host smart-3ff3fb6a-77bc-411e-a93c-b7c9593ff2dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196546746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2196546746
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.729853878
Short name T131
Test name
Test status
Simulation time 139774355 ps
CPU time 1.11 seconds
Started Apr 16 12:21:16 PM PDT 24
Finished Apr 16 12:21:18 PM PDT 24
Peak memory 195412 kb
Host smart-b1511385-39f9-46d6-a27b-2f41c534dc62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729853878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.729853878
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.842851433
Short name T693
Test name
Test status
Simulation time 313966660 ps
CPU time 2.67 seconds
Started Apr 16 12:21:29 PM PDT 24
Finished Apr 16 12:21:33 PM PDT 24
Peak memory 196436 kb
Host smart-2512eee7-ab8d-4154-a50b-2ad03a4a26bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842851433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.842851433
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.161224482
Short name T690
Test name
Test status
Simulation time 227613904 ps
CPU time 3.71 seconds
Started Apr 16 12:18:59 PM PDT 24
Finished Apr 16 12:19:03 PM PDT 24
Peak memory 196776 kb
Host smart-2e647841-55ae-41c3-ae86-ff7c7ec72f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161224482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.161224482
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2534750505
Short name T121
Test name
Test status
Simulation time 46898136 ps
CPU time 0.9 seconds
Started Apr 16 12:18:11 PM PDT 24
Finished Apr 16 12:18:13 PM PDT 24
Peak memory 196592 kb
Host smart-eda03494-2a67-4a23-b29e-cb9d16a6f09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534750505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2534750505
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2221288029
Short name T163
Test name
Test status
Simulation time 24241481 ps
CPU time 0.98 seconds
Started Apr 16 12:20:56 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 193828 kb
Host smart-55841941-a38e-420e-a449-3e32eff68d35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221288029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2221288029
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1435827482
Short name T629
Test name
Test status
Simulation time 137756811 ps
CPU time 3.89 seconds
Started Apr 16 12:21:46 PM PDT 24
Finished Apr 16 12:21:52 PM PDT 24
Peak memory 197684 kb
Host smart-27ed306e-880b-4bc1-be64-d460133fb179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435827482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1435827482
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.292225865
Short name T43
Test name
Test status
Simulation time 62278295 ps
CPU time 0.89 seconds
Started Apr 16 12:20:20 PM PDT 24
Finished Apr 16 12:20:22 PM PDT 24
Peak memory 213580 kb
Host smart-97234302-8fd6-493d-8fe5-906fecfb2805
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292225865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.292225865
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2260192276
Short name T430
Test name
Test status
Simulation time 62705178 ps
CPU time 0.74 seconds
Started Apr 16 12:22:03 PM PDT 24
Finished Apr 16 12:22:05 PM PDT 24
Peak memory 195232 kb
Host smart-ea06ab2e-020e-4a1b-8095-d02093b33053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260192276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2260192276
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2168651450
Short name T356
Test name
Test status
Simulation time 196201312 ps
CPU time 1.37 seconds
Started Apr 16 12:20:07 PM PDT 24
Finished Apr 16 12:20:09 PM PDT 24
Peak memory 196844 kb
Host smart-3e7b8e16-3f3a-4c5d-8c16-954c7883e125
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168651450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2168651450
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.665087168
Short name T621
Test name
Test status
Simulation time 8721245319 ps
CPU time 135.51 seconds
Started Apr 16 12:19:26 PM PDT 24
Finished Apr 16 12:21:43 PM PDT 24
Peak memory 198548 kb
Host smart-a938334b-813a-4ffc-bfb3-a9004b1c3111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665087168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.665087168
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2939836604
Short name T672
Test name
Test status
Simulation time 134404341789 ps
CPU time 1558.83 seconds
Started Apr 16 12:22:04 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 206372 kb
Host smart-648ffa53-006f-45b4-982f-77a252b1bc00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2939836604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2939836604
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1674329826
Short name T460
Test name
Test status
Simulation time 16550844 ps
CPU time 0.6 seconds
Started Apr 16 12:22:46 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 193928 kb
Host smart-c6487e73-c752-4110-b7f1-b44167bb1f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674329826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1674329826
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3634724024
Short name T492
Test name
Test status
Simulation time 41279236 ps
CPU time 0.71 seconds
Started Apr 16 12:22:44 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 195116 kb
Host smart-2cd29ecc-a021-4d9b-b5d2-7487112d2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634724024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3634724024
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1042108691
Short name T603
Test name
Test status
Simulation time 348264487 ps
CPU time 18.36 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 196868 kb
Host smart-8e2b576d-ad21-40df-82cd-5801fe9d0a0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042108691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1042108691
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.277316096
Short name T441
Test name
Test status
Simulation time 87883002 ps
CPU time 1.24 seconds
Started Apr 16 12:22:46 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 198000 kb
Host smart-b545748d-60e9-4463-ba7d-126c3f00e885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277316096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.277316096
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2193195886
Short name T418
Test name
Test status
Simulation time 231013791 ps
CPU time 1.1 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:58 PM PDT 24
Peak memory 196248 kb
Host smart-29c0c9df-282e-49bf-a0d7-bcb08e9bcc0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193195886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2193195886
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2080449534
Short name T556
Test name
Test status
Simulation time 163012764 ps
CPU time 3.22 seconds
Started Apr 16 12:22:47 PM PDT 24
Finished Apr 16 12:22:55 PM PDT 24
Peak memory 198152 kb
Host smart-dfbbe56e-9fc7-4a0d-9a31-1590b225233b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080449534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2080449534
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.4084338259
Short name T260
Test name
Test status
Simulation time 83637786 ps
CPU time 1.84 seconds
Started Apr 16 12:22:49 PM PDT 24
Finished Apr 16 12:22:56 PM PDT 24
Peak memory 196820 kb
Host smart-79863936-becd-4cdb-899e-1ea9eee9e9ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084338259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.4084338259
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3197732241
Short name T687
Test name
Test status
Simulation time 24963858 ps
CPU time 1.03 seconds
Started Apr 16 12:22:50 PM PDT 24
Finished Apr 16 12:22:56 PM PDT 24
Peak memory 195952 kb
Host smart-8d52a2b0-f5a3-406f-b93a-d91c7f546928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197732241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3197732241
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3335832142
Short name T320
Test name
Test status
Simulation time 41148332 ps
CPU time 0.8 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:47 PM PDT 24
Peak memory 195628 kb
Host smart-4d785aab-0809-4a15-b397-8b987136a5e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335832142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3335832142
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1355178736
Short name T150
Test name
Test status
Simulation time 818843085 ps
CPU time 4.28 seconds
Started Apr 16 12:22:53 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 198092 kb
Host smart-c91d3ea8-ba67-45d3-bc39-0f7ccd5e7258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355178736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1355178736
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2845471082
Short name T462
Test name
Test status
Simulation time 28835964 ps
CPU time 0.7 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:46 PM PDT 24
Peak memory 195288 kb
Host smart-e9f5142d-eccb-4343-aad2-2b6640e5b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845471082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2845471082
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.971272271
Short name T200
Test name
Test status
Simulation time 295250953 ps
CPU time 1.21 seconds
Started Apr 16 12:22:44 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 197916 kb
Host smart-92420b10-ea8c-494b-9f58-7cfc8cd98738
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971272271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.971272271
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2964357635
Short name T396
Test name
Test status
Simulation time 8108646917 ps
CPU time 101.69 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:24:32 PM PDT 24
Peak memory 198188 kb
Host smart-04d036a7-02a8-4037-a0e4-814f6f218796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964357635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2964357635
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1264931422
Short name T519
Test name
Test status
Simulation time 14977672 ps
CPU time 0.57 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 193968 kb
Host smart-d3832952-117d-465a-9be1-e644d0b246fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264931422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1264931422
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2067756113
Short name T175
Test name
Test status
Simulation time 51222172 ps
CPU time 0.71 seconds
Started Apr 16 12:22:48 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 194516 kb
Host smart-2f22da0d-cc5e-429c-b2ad-ad95fdba51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067756113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2067756113
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2555437053
Short name T651
Test name
Test status
Simulation time 351485307 ps
CPU time 18.06 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 197052 kb
Host smart-e58db4b5-c502-408c-bd37-2851e5c5ca6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555437053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2555437053
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.400791949
Short name T675
Test name
Test status
Simulation time 226947308 ps
CPU time 0.84 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 196160 kb
Host smart-46d099b0-4fcc-4cdc-923a-e5d7f61f0c1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400791949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.400791949
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2610163202
Short name T580
Test name
Test status
Simulation time 16270257 ps
CPU time 0.7 seconds
Started Apr 16 12:22:46 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 194288 kb
Host smart-73ae7201-4fa4-4e89-8ad9-896eb52ae573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610163202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2610163202
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3805834231
Short name T305
Test name
Test status
Simulation time 115813437 ps
CPU time 1.31 seconds
Started Apr 16 12:22:46 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 196588 kb
Host smart-a761da1d-1d8d-4f17-b53f-b925c537eb51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805834231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3805834231
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3680263477
Short name T129
Test name
Test status
Simulation time 159366537 ps
CPU time 1.13 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:58 PM PDT 24
Peak memory 195424 kb
Host smart-670bade0-f318-4b01-9b64-3770bc51fd3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680263477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3680263477
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3489924848
Short name T189
Test name
Test status
Simulation time 215599324 ps
CPU time 1.14 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 195756 kb
Host smart-8bb36e64-8870-4caa-8388-ed90a5a58908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489924848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3489924848
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1377889529
Short name T420
Test name
Test status
Simulation time 220468924 ps
CPU time 1.06 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 196048 kb
Host smart-83536796-dd36-4e49-a5d0-0d2e1c32788a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377889529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1377889529
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_smoke.1722294002
Short name T578
Test name
Test status
Simulation time 325954975 ps
CPU time 1.06 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 196376 kb
Host smart-cad1649b-cb07-434e-9014-66b748ea8ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722294002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1722294002
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1068328358
Short name T599
Test name
Test status
Simulation time 26897823 ps
CPU time 0.98 seconds
Started Apr 16 12:22:53 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 196432 kb
Host smart-1d3be525-724f-48ad-8a0e-23301d80e033
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068328358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1068328358
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3195900390
Short name T153
Test name
Test status
Simulation time 11396517998 ps
CPU time 212.68 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:26:29 PM PDT 24
Peak memory 198068 kb
Host smart-14f912cc-86ed-410b-9de7-fffdfdb1b746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195900390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3195900390
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.297724404
Short name T365
Test name
Test status
Simulation time 23443389 ps
CPU time 0.6 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 195088 kb
Host smart-b664a073-cca6-4c03-b085-56036befebab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297724404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.297724404
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2838540836
Short name T483
Test name
Test status
Simulation time 29375587 ps
CPU time 0.8 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 196600 kb
Host smart-657bb66f-34d2-470f-8bea-563f246a2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838540836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2838540836
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2075284775
Short name T106
Test name
Test status
Simulation time 3151972092 ps
CPU time 21.64 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 196660 kb
Host smart-cf968779-9b08-4acd-ba0b-161167650e6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075284775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2075284775
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1267281294
Short name T516
Test name
Test status
Simulation time 88315385 ps
CPU time 0.66 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 195104 kb
Host smart-1b4e0fc5-e194-4e82-9d13-57ad378946ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267281294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1267281294
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1530947101
Short name T321
Test name
Test status
Simulation time 109168915 ps
CPU time 0.95 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 196596 kb
Host smart-7772893e-9898-442e-9d97-6fc8bbf03c16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530947101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1530947101
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2774491075
Short name T421
Test name
Test status
Simulation time 303647081 ps
CPU time 2.86 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:15 PM PDT 24
Peak memory 198048 kb
Host smart-b20f1cca-651c-45c6-a976-7a07e0cb1ca4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774491075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2774491075
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.167655828
Short name T263
Test name
Test status
Simulation time 107310135 ps
CPU time 2.28 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 198020 kb
Host smart-ba6789e9-dcc2-4248-9d44-0c4d41dbe2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167655828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
167655828
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2852570330
Short name T218
Test name
Test status
Simulation time 67301682 ps
CPU time 1.19 seconds
Started Apr 16 12:22:46 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 197212 kb
Host smart-26263347-cffd-4499-b2cf-d70a0fd16ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852570330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2852570330
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.159791458
Short name T158
Test name
Test status
Simulation time 82112621 ps
CPU time 1.23 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 197188 kb
Host smart-d470a583-5db2-43e5-b2c1-46099b92b877
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159791458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.159791458
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.775433813
Short name T394
Test name
Test status
Simulation time 229791740 ps
CPU time 3.24 seconds
Started Apr 16 12:22:53 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 197916 kb
Host smart-71d3e0e5-e450-4838-9114-55ed21da4ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775433813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.775433813
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3870013949
Short name T185
Test name
Test status
Simulation time 20483092 ps
CPU time 0.74 seconds
Started Apr 16 12:22:47 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 194960 kb
Host smart-3460502a-0654-400a-be14-557f03a8af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870013949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3870013949
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1914226601
Short name T363
Test name
Test status
Simulation time 531672315 ps
CPU time 1.1 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 195508 kb
Host smart-c6392f07-fb42-4a7d-872c-385f995a3369
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914226601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1914226601
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4247299044
Short name T21
Test name
Test status
Simulation time 132876836089 ps
CPU time 164.96 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:25:42 PM PDT 24
Peak memory 198044 kb
Host smart-da306c2d-c43d-4d6e-8668-2474a2b7b5ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247299044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4247299044
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1748416286
Short name T482
Test name
Test status
Simulation time 41879459147 ps
CPU time 885.04 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:37:42 PM PDT 24
Peak memory 198296 kb
Host smart-daa5f134-654c-49b8-8f52-e484e2287954
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1748416286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1748416286
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2056208267
Short name T457
Test name
Test status
Simulation time 49161726 ps
CPU time 0.66 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:13 PM PDT 24
Peak memory 194900 kb
Host smart-3eac4a0c-5a8e-488c-a658-0022e77e2b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056208267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2056208267
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2385422355
Short name T355
Test name
Test status
Simulation time 2823192541 ps
CPU time 15.67 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:29 PM PDT 24
Peak memory 197136 kb
Host smart-f4f72f41-2a9d-465a-94c2-55290c35a116
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385422355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2385422355
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.41525483
Short name T604
Test name
Test status
Simulation time 193603796 ps
CPU time 0.82 seconds
Started Apr 16 12:22:54 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 196088 kb
Host smart-12ead064-cc86-41a3-ab98-d31214bccff3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.41525483
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.896536632
Short name T666
Test name
Test status
Simulation time 53531965 ps
CPU time 0.76 seconds
Started Apr 16 12:23:56 PM PDT 24
Finished Apr 16 12:23:59 PM PDT 24
Peak memory 193796 kb
Host smart-6f6f8789-bc61-4c87-beb3-65d92b5dcf72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896536632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.896536632
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2616428687
Short name T224
Test name
Test status
Simulation time 95548699 ps
CPU time 3.41 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 196580 kb
Host smart-08e4a722-2afa-4b72-a985-be2352b2e62b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616428687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2616428687
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.91650907
Short name T235
Test name
Test status
Simulation time 113019709 ps
CPU time 1.86 seconds
Started Apr 16 12:22:49 PM PDT 24
Finished Apr 16 12:22:56 PM PDT 24
Peak memory 197364 kb
Host smart-81c55428-8511-40c5-bc83-a10ab7e71106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91650907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.91650907
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3215086050
Short name T282
Test name
Test status
Simulation time 68125959 ps
CPU time 1.22 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 196620 kb
Host smart-40dde1cf-ae14-4420-ba67-3538b55f859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215086050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3215086050
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1397648399
Short name T342
Test name
Test status
Simulation time 79458858 ps
CPU time 0.82 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:58 PM PDT 24
Peak memory 196672 kb
Host smart-1956ca53-2a8b-4e0d-ad08-cc5048e993fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397648399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1397648399
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1308311723
Short name T366
Test name
Test status
Simulation time 285480934 ps
CPU time 3.38 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:15 PM PDT 24
Peak memory 197944 kb
Host smart-a8106e1f-de29-4999-bda2-5d3e3c320618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308311723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1308311723
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1706005919
Short name T485
Test name
Test status
Simulation time 247356246 ps
CPU time 1.27 seconds
Started Apr 16 12:23:03 PM PDT 24
Finished Apr 16 12:23:06 PM PDT 24
Peak memory 196892 kb
Host smart-23f2c05e-4099-4f59-b07a-cbd49ee50b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706005919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1706005919
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2004810657
Short name T550
Test name
Test status
Simulation time 139019203 ps
CPU time 1.04 seconds
Started Apr 16 12:22:57 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 195608 kb
Host smart-912ed58d-8545-4fed-beb0-8daf3dd8775f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004810657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2004810657
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.4168207801
Short name T677
Test name
Test status
Simulation time 7174176232 ps
CPU time 183.1 seconds
Started Apr 16 12:23:14 PM PDT 24
Finished Apr 16 12:26:18 PM PDT 24
Peak memory 198200 kb
Host smart-376377d3-b059-46cf-9971-4552340544b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168207801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.4168207801
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1051938854
Short name T70
Test name
Test status
Simulation time 609484879878 ps
CPU time 1250.5 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:43:50 PM PDT 24
Peak memory 198148 kb
Host smart-bbb7c74f-6d16-4d3e-97a4-fe40edf5ac0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1051938854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1051938854
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2900566510
Short name T284
Test name
Test status
Simulation time 87745452 ps
CPU time 0.61 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 194116 kb
Host smart-9e9ccf1f-2df7-4391-a231-560c22fced05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900566510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2900566510
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1485130220
Short name T50
Test name
Test status
Simulation time 162612080 ps
CPU time 0.92 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 195976 kb
Host smart-0ab0fadf-3f91-4da4-b1f8-d758bf878815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485130220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1485130220
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3269572153
Short name T592
Test name
Test status
Simulation time 1226561088 ps
CPU time 10.71 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:13 PM PDT 24
Peak memory 196812 kb
Host smart-f9de9bfb-ae0c-4fe9-9d11-a79f96770ee3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269572153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3269572153
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2972024504
Short name T240
Test name
Test status
Simulation time 376901480 ps
CPU time 1.01 seconds
Started Apr 16 12:23:03 PM PDT 24
Finished Apr 16 12:23:06 PM PDT 24
Peak memory 197980 kb
Host smart-212b79d6-ff39-44a9-ac6d-1edfe55a6fa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972024504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2972024504
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.23921039
Short name T490
Test name
Test status
Simulation time 337480495 ps
CPU time 0.74 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:58 PM PDT 24
Peak memory 195440 kb
Host smart-dbf75871-dfcf-456f-95fd-773a5c4e692a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23921039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.23921039
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.311188393
Short name T671
Test name
Test status
Simulation time 27747012 ps
CPU time 1.19 seconds
Started Apr 16 12:23:04 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 197252 kb
Host smart-1782b612-f541-49b6-b794-4bb0d08bab1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311188393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.311188393
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1198355640
Short name T350
Test name
Test status
Simulation time 41714765 ps
CPU time 1.13 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 195672 kb
Host smart-a5f63c7b-be73-46c1-a46a-30fc28387cfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198355640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1198355640
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3330631166
Short name T329
Test name
Test status
Simulation time 110003117 ps
CPU time 1.21 seconds
Started Apr 16 12:23:56 PM PDT 24
Finished Apr 16 12:23:59 PM PDT 24
Peak memory 195436 kb
Host smart-4444785d-f3b7-48f3-a297-f2107382a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330631166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3330631166
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4229418065
Short name T254
Test name
Test status
Simulation time 15353861 ps
CPU time 0.66 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 194292 kb
Host smart-11ee8835-9dca-4622-b6fc-937c866f5fed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229418065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4229418065
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3770544226
Short name T241
Test name
Test status
Simulation time 151369269 ps
CPU time 3.39 seconds
Started Apr 16 12:23:01 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 198092 kb
Host smart-433e598d-23fc-49ab-8d5a-5d767c1a6129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770544226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3770544226
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2871506623
Short name T587
Test name
Test status
Simulation time 132679300 ps
CPU time 1.1 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 195684 kb
Host smart-f3184432-e28a-43aa-bdd4-f5fe584e9596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871506623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2871506623
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3628442827
Short name T522
Test name
Test status
Simulation time 72444965 ps
CPU time 1.28 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:22:57 PM PDT 24
Peak memory 196772 kb
Host smart-bcf83a81-17e5-49c9-b507-dcfff64d709b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628442827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3628442827
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2273374590
Short name T159
Test name
Test status
Simulation time 34731368628 ps
CPU time 122.14 seconds
Started Apr 16 12:22:58 PM PDT 24
Finished Apr 16 12:25:04 PM PDT 24
Peak memory 198180 kb
Host smart-04267f0d-ec0c-4c77-b3c1-0b245ebd8c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273374590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2273374590
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1450141505
Short name T105
Test name
Test status
Simulation time 26055813 ps
CPU time 0.59 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 194100 kb
Host smart-89da759d-97be-40f0-98a0-6f1e68a45119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450141505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1450141505
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1587175911
Short name T239
Test name
Test status
Simulation time 27668514 ps
CPU time 0.85 seconds
Started Apr 16 12:23:01 PM PDT 24
Finished Apr 16 12:23:04 PM PDT 24
Peak memory 195352 kb
Host smart-143c0168-1cea-4264-8a38-3ef3ec6ec82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587175911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1587175911
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3019981533
Short name T446
Test name
Test status
Simulation time 446096135 ps
CPU time 12.13 seconds
Started Apr 16 12:23:03 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 198112 kb
Host smart-a5c027ff-52a3-4ea4-8b3c-8dd79ee0aa47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019981533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3019981533
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4046119468
Short name T391
Test name
Test status
Simulation time 306863774 ps
CPU time 0.99 seconds
Started Apr 16 12:23:08 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 197840 kb
Host smart-068b79d8-44ac-4a5c-9f61-24bff78f412a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046119468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4046119468
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1161494413
Short name T214
Test name
Test status
Simulation time 81853579 ps
CPU time 0.89 seconds
Started Apr 16 12:23:00 PM PDT 24
Finished Apr 16 12:23:04 PM PDT 24
Peak memory 196480 kb
Host smart-111e25fd-b287-44f6-952d-1eb253ba77e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161494413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1161494413
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2695862782
Short name T682
Test name
Test status
Simulation time 561189673 ps
CPU time 2.84 seconds
Started Apr 16 12:23:01 PM PDT 24
Finished Apr 16 12:23:06 PM PDT 24
Peak memory 198248 kb
Host smart-ccf91419-7b79-4cce-978f-4606daab2a24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695862782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2695862782
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1549612023
Short name T686
Test name
Test status
Simulation time 551178855 ps
CPU time 1.75 seconds
Started Apr 16 12:22:57 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 196448 kb
Host smart-f14a78b5-3f82-4592-958e-f282f36d6db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549612023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1549612023
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3499728691
Short name T434
Test name
Test status
Simulation time 122482230 ps
CPU time 1.27 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:03 PM PDT 24
Peak memory 195952 kb
Host smart-74b88492-e437-4725-9b02-7bc38bf1280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499728691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3499728691
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1306645909
Short name T264
Test name
Test status
Simulation time 33495829 ps
CPU time 1.15 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 198092 kb
Host smart-45bdb39f-1725-4b09-bfc6-4f3d15b5ac38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306645909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1306645909
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2712479727
Short name T660
Test name
Test status
Simulation time 5891611376 ps
CPU time 5.69 seconds
Started Apr 16 12:23:01 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 198212 kb
Host smart-3767fbdb-5fb7-4667-b40c-a40af8868363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712479727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2712479727
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4267316941
Short name T625
Test name
Test status
Simulation time 50941838 ps
CPU time 0.97 seconds
Started Apr 16 12:23:10 PM PDT 24
Finished Apr 16 12:23:13 PM PDT 24
Peak memory 196416 kb
Host smart-b7d5546b-222e-469c-b503-a900d0850251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267316941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4267316941
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.303329336
Short name T169
Test name
Test status
Simulation time 39678941 ps
CPU time 1.19 seconds
Started Apr 16 12:23:08 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 196688 kb
Host smart-769cd0d8-58b6-44e4-bbb1-f8351d72ba1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303329336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.303329336
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.4269576657
Short name T290
Test name
Test status
Simulation time 29247331773 ps
CPU time 139.24 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:25:21 PM PDT 24
Peak memory 198220 kb
Host smart-85af8918-713d-44ed-bd0c-c3aa090a7dd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269576657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.4269576657
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3287443151
Short name T25
Test name
Test status
Simulation time 41378114 ps
CPU time 0.6 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 194476 kb
Host smart-eed4125f-6543-4b89-9f8a-868701df3e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287443151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3287443151
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1814861936
Short name T608
Test name
Test status
Simulation time 144760002 ps
CPU time 0.9 seconds
Started Apr 16 12:23:01 PM PDT 24
Finished Apr 16 12:23:05 PM PDT 24
Peak memory 196592 kb
Host smart-49e697c3-b719-42e1-a69c-d692a8b1dec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814861936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1814861936
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.674067747
Short name T395
Test name
Test status
Simulation time 1765762723 ps
CPU time 14.39 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:31 PM PDT 24
Peak memory 196860 kb
Host smart-aa5d2c02-9af5-4c7a-82a4-52b53287752e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674067747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.674067747
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3126908253
Short name T309
Test name
Test status
Simulation time 269607001 ps
CPU time 0.84 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 196120 kb
Host smart-6f83cb4f-d942-459a-9f42-6b5d3ec257b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126908253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3126908253
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.349454460
Short name T498
Test name
Test status
Simulation time 425622357 ps
CPU time 1.43 seconds
Started Apr 16 12:23:20 PM PDT 24
Finished Apr 16 12:23:23 PM PDT 24
Peak memory 197188 kb
Host smart-487521e5-0d3f-4ad3-9728-750e39bca595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349454460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.349454460
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3191445563
Short name T665
Test name
Test status
Simulation time 169145073 ps
CPU time 1.22 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 196620 kb
Host smart-ba859a3a-a3c8-4c7d-a106-6f3072579f2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191445563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3191445563
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3015394550
Short name T520
Test name
Test status
Simulation time 123482614 ps
CPU time 3.52 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 196664 kb
Host smart-42bc01d9-f440-480a-b36c-e0537aec552a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015394550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3015394550
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1208811316
Short name T630
Test name
Test status
Simulation time 67120359 ps
CPU time 0.7 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 194400 kb
Host smart-106f08b4-76f2-469a-abbf-38d0a4c28909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208811316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1208811316
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2688879677
Short name T562
Test name
Test status
Simulation time 27829353 ps
CPU time 1.1 seconds
Started Apr 16 12:23:02 PM PDT 24
Finished Apr 16 12:23:06 PM PDT 24
Peak memory 196732 kb
Host smart-0076bf9a-5322-4053-b800-e61db21ba7cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688879677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2688879677
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3428815138
Short name T549
Test name
Test status
Simulation time 1454025631 ps
CPU time 2.56 seconds
Started Apr 16 12:23:07 PM PDT 24
Finished Apr 16 12:23:11 PM PDT 24
Peak memory 198012 kb
Host smart-7bd5fcd1-d09e-49e5-a618-558f83f07d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428815138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3428815138
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1213360569
Short name T581
Test name
Test status
Simulation time 132590329 ps
CPU time 1.21 seconds
Started Apr 16 12:22:56 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 195920 kb
Host smart-7cd38dc7-fd34-4178-9727-db60fc2717dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213360569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1213360569
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2589275448
Short name T647
Test name
Test status
Simulation time 210053708 ps
CPU time 1.15 seconds
Started Apr 16 12:22:59 PM PDT 24
Finished Apr 16 12:23:04 PM PDT 24
Peak memory 195620 kb
Host smart-871662ce-8aa5-4ba1-b4d1-5f7b2b4c249f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589275448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2589275448
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2895282543
Short name T384
Test name
Test status
Simulation time 3123936515 ps
CPU time 72.08 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:25:04 PM PDT 24
Peak memory 198176 kb
Host smart-43c013a7-71a8-4332-aae3-1daceede00f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895282543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2895282543
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3904499751
Short name T292
Test name
Test status
Simulation time 10390581 ps
CPU time 0.61 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:57 PM PDT 24
Peak memory 194712 kb
Host smart-707478ea-7d18-4909-ba40-ef5baa892d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904499751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3904499751
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3808433496
Short name T278
Test name
Test status
Simulation time 116253505 ps
CPU time 0.77 seconds
Started Apr 16 12:23:08 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 195988 kb
Host smart-43f22b16-ca1b-4be7-b5fa-fb952eba0c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808433496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3808433496
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3557898969
Short name T407
Test name
Test status
Simulation time 1257646806 ps
CPU time 21.22 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 196868 kb
Host smart-77494b56-7cad-4847-8a0b-730933b6e865
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557898969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3557898969
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.138182871
Short name T435
Test name
Test status
Simulation time 168199762 ps
CPU time 0.67 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 194916 kb
Host smart-975bfb4b-65c0-47f5-bfaa-cb8b687eda66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138182871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.138182871
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2047832530
Short name T542
Test name
Test status
Simulation time 22584071 ps
CPU time 0.78 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 196492 kb
Host smart-8199d600-334b-4526-8a92-bc431266e08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047832530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2047832530
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3353495383
Short name T231
Test name
Test status
Simulation time 172982968 ps
CPU time 1.96 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:22 PM PDT 24
Peak memory 197952 kb
Host smart-18320cde-7976-4258-808b-85de27c93d1a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353495383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3353495383
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.353462875
Short name T156
Test name
Test status
Simulation time 351744811 ps
CPU time 1.9 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 195928 kb
Host smart-6c944531-49a6-4945-9b7b-15f2cc639a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353462875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
353462875
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1778031686
Short name T187
Test name
Test status
Simulation time 26306017 ps
CPU time 0.92 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 196164 kb
Host smart-3688d126-c9db-4fbf-b235-1209c47c9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778031686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1778031686
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3792899174
Short name T370
Test name
Test status
Simulation time 159754516 ps
CPU time 0.92 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 195948 kb
Host smart-43937ff8-3c05-44df-a6ea-4140660b4bcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792899174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3792899174
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2213873074
Short name T411
Test name
Test status
Simulation time 1874650099 ps
CPU time 4.29 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:24 PM PDT 24
Peak memory 197888 kb
Host smart-a749dea5-7a33-4a26-b68c-88c3cc95974a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213873074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2213873074
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2541925428
Short name T334
Test name
Test status
Simulation time 148217692 ps
CPU time 0.85 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:42 PM PDT 24
Peak memory 196544 kb
Host smart-c6c56850-74ab-4bf3-b10d-4084f6f43d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541925428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2541925428
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2156888992
Short name T232
Test name
Test status
Simulation time 109397345 ps
CPU time 0.99 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 195768 kb
Host smart-697b9b68-77fa-4ce9-b6ee-6e12d434f4d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156888992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2156888992
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2741027220
Short name T458
Test name
Test status
Simulation time 6965735446 ps
CPU time 90.02 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:24:37 PM PDT 24
Peak memory 198548 kb
Host smart-2b288c3a-c296-4284-837d-dcd6d91d43ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741027220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2741027220
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1881755074
Short name T653
Test name
Test status
Simulation time 104591455 ps
CPU time 0.59 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 193956 kb
Host smart-ea93e5fd-01f5-47a3-b082-7cfd49e4d588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881755074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1881755074
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.275421071
Short name T713
Test name
Test status
Simulation time 33488659 ps
CPU time 0.91 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 196620 kb
Host smart-b37588de-8494-4a95-a1df-72665951215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275421071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.275421071
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1843169987
Short name T563
Test name
Test status
Simulation time 74178740 ps
CPU time 3.82 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 195836 kb
Host smart-945c3b22-e483-4988-8a36-58590e49fa04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843169987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1843169987
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1735347080
Short name T233
Test name
Test status
Simulation time 69244433 ps
CPU time 1.08 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:23:09 PM PDT 24
Peak memory 198200 kb
Host smart-2f354fe7-e3d8-4c27-99b9-e27f96d4b916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735347080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1735347080
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4033108865
Short name T293
Test name
Test status
Simulation time 71252371 ps
CPU time 1.28 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 196548 kb
Host smart-ff3ba73e-1aa9-4d7d-990c-f9e8a91125c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033108865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4033108865
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2301126969
Short name T223
Test name
Test status
Simulation time 43087268 ps
CPU time 1.69 seconds
Started Apr 16 12:23:04 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 198144 kb
Host smart-b11a847f-e124-47b4-82fd-46bc32c93e6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301126969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2301126969
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1987982622
Short name T387
Test name
Test status
Simulation time 215951782 ps
CPU time 3.22 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:23:11 PM PDT 24
Peak memory 198036 kb
Host smart-b8b6381d-8bcf-4bb0-9d1b-0044a1d32809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987982622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1987982622
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4255067506
Short name T500
Test name
Test status
Simulation time 58002622 ps
CPU time 0.68 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 195116 kb
Host smart-0c0b370c-6136-4822-8b02-d8ddefe26074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255067506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4255067506
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2457950628
Short name T506
Test name
Test status
Simulation time 21798465 ps
CPU time 0.65 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 194896 kb
Host smart-bb17d9d5-0207-4243-af24-bb127cd7ac84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457950628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2457950628
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.931414945
Short name T8
Test name
Test status
Simulation time 1531551645 ps
CPU time 2.07 seconds
Started Apr 16 12:23:03 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 198056 kb
Host smart-248c20d1-c280-44f7-9df8-30cadac4aff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931414945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.931414945
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.853018276
Short name T703
Test name
Test status
Simulation time 37903174 ps
CPU time 0.9 seconds
Started Apr 16 12:23:07 PM PDT 24
Finished Apr 16 12:23:09 PM PDT 24
Peak memory 196472 kb
Host smart-8e630fae-20d4-440b-b1d1-8ff46395afa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853018276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.853018276
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.676192021
Short name T316
Test name
Test status
Simulation time 40102837 ps
CPU time 1.17 seconds
Started Apr 16 12:23:04 PM PDT 24
Finished Apr 16 12:23:07 PM PDT 24
Peak memory 195772 kb
Host smart-a00dda1f-8f53-45ee-829d-bad7b0d6d049
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676192021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.676192021
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.363819982
Short name T367
Test name
Test status
Simulation time 6907968592 ps
CPU time 171.22 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:26:47 PM PDT 24
Peak memory 198276 kb
Host smart-981cc83d-a0ab-4b6e-bffd-ec357b95176e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363819982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.363819982
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4138586423
Short name T564
Test name
Test status
Simulation time 17044711 ps
CPU time 0.54 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:13 PM PDT 24
Peak memory 193972 kb
Host smart-a59ea839-69c1-47c4-882b-058116f0c75d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138586423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4138586423
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1146949275
Short name T184
Test name
Test status
Simulation time 62637653 ps
CPU time 0.77 seconds
Started Apr 16 12:23:58 PM PDT 24
Finished Apr 16 12:24:00 PM PDT 24
Peak memory 195856 kb
Host smart-5c104f19-0941-454f-94eb-dcf9d3821274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146949275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1146949275
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1753057220
Short name T389
Test name
Test status
Simulation time 369938827 ps
CPU time 9.9 seconds
Started Apr 16 12:23:13 PM PDT 24
Finished Apr 16 12:23:25 PM PDT 24
Peak memory 197964 kb
Host smart-fe0bf8bb-d407-4292-8e6c-00c29d057321
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753057220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1753057220
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.184319110
Short name T195
Test name
Test status
Simulation time 61987702 ps
CPU time 0.79 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 195976 kb
Host smart-2ccbeedb-accc-4c56-a7a4-6cd11d72629f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184319110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.184319110
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3868141547
Short name T298
Test name
Test status
Simulation time 53893334 ps
CPU time 0.98 seconds
Started Apr 16 12:23:09 PM PDT 24
Finished Apr 16 12:23:10 PM PDT 24
Peak memory 196080 kb
Host smart-1784dad2-cece-4bcc-928f-b01a2b27158d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868141547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3868141547
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1546567398
Short name T219
Test name
Test status
Simulation time 24100127 ps
CPU time 1.08 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 196488 kb
Host smart-033d7896-9340-41c7-bdee-a59c98b349e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546567398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1546567398
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2142577556
Short name T45
Test name
Test status
Simulation time 505693114 ps
CPU time 2.48 seconds
Started Apr 16 12:24:20 PM PDT 24
Finished Apr 16 12:24:27 PM PDT 24
Peak memory 196732 kb
Host smart-2448d232-746b-4455-9f63-3b95084f4170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142577556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2142577556
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.462499942
Short name T408
Test name
Test status
Simulation time 44771136 ps
CPU time 0.91 seconds
Started Apr 16 12:23:09 PM PDT 24
Finished Apr 16 12:23:11 PM PDT 24
Peak memory 195964 kb
Host smart-078ce648-8393-449a-a402-2ca4f05294d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462499942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.462499942
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3967726492
Short name T9
Test name
Test status
Simulation time 857131368 ps
CPU time 5.07 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 197952 kb
Host smart-15be7821-4361-4d97-8250-290c6d99a387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967726492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3967726492
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2062726771
Short name T575
Test name
Test status
Simulation time 346416331 ps
CPU time 1.27 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 197100 kb
Host smart-9f9d6c8b-865c-47ba-86ce-5f43bd2e0706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062726771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2062726771
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1343468313
Short name T486
Test name
Test status
Simulation time 53236923 ps
CPU time 0.73 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 195932 kb
Host smart-093f2dce-e035-45af-9eae-81cc332a90ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343468313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1343468313
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2137167590
Short name T249
Test name
Test status
Simulation time 25440762060 ps
CPU time 81.92 seconds
Started Apr 16 12:23:24 PM PDT 24
Finished Apr 16 12:24:47 PM PDT 24
Peak memory 198064 kb
Host smart-a7bb0d29-8951-447a-bbe4-495cc213754b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137167590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2137167590
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.649697879
Short name T573
Test name
Test status
Simulation time 15276837 ps
CPU time 0.58 seconds
Started Apr 16 12:22:26 PM PDT 24
Finished Apr 16 12:22:28 PM PDT 24
Peak memory 193848 kb
Host smart-ccd56bb6-f32f-4e93-88f1-cc708d1874fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649697879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.649697879
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.51190548
Short name T53
Test name
Test status
Simulation time 24786845 ps
CPU time 0.58 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 194752 kb
Host smart-edb635fc-55eb-41ea-9732-c6cbad7cfbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51190548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.51190548
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3966547437
Short name T557
Test name
Test status
Simulation time 1369177129 ps
CPU time 18.32 seconds
Started Apr 16 12:22:23 PM PDT 24
Finished Apr 16 12:22:42 PM PDT 24
Peak memory 196860 kb
Host smart-d7bb0009-8da7-497a-bc9c-603634db11b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966547437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3966547437
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4056348538
Short name T590
Test name
Test status
Simulation time 224075220 ps
CPU time 0.86 seconds
Started Apr 16 12:22:28 PM PDT 24
Finished Apr 16 12:22:30 PM PDT 24
Peak memory 197164 kb
Host smart-bffa4bb0-39be-43b9-86ac-800c3b7d1ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056348538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4056348538
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3354229336
Short name T144
Test name
Test status
Simulation time 51956168 ps
CPU time 1.09 seconds
Started Apr 16 12:22:44 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 196924 kb
Host smart-c4c7f61e-9569-4b16-b9ac-e529b015f792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354229336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3354229336
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3858971040
Short name T700
Test name
Test status
Simulation time 83267513 ps
CPU time 0.99 seconds
Started Apr 16 12:22:23 PM PDT 24
Finished Apr 16 12:22:25 PM PDT 24
Peak memory 196128 kb
Host smart-4d8b50ca-2820-4160-9bed-6de5300c8560
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858971040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3858971040
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.810361839
Short name T357
Test name
Test status
Simulation time 626184088 ps
CPU time 3.12 seconds
Started Apr 16 12:22:44 PM PDT 24
Finished Apr 16 12:22:53 PM PDT 24
Peak memory 197208 kb
Host smart-9b5dd855-3b84-4dbf-aa4a-9678b2bc1fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810361839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.810361839
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2631020924
Short name T314
Test name
Test status
Simulation time 242086668 ps
CPU time 0.86 seconds
Started Apr 16 12:22:35 PM PDT 24
Finished Apr 16 12:22:41 PM PDT 24
Peak memory 196464 kb
Host smart-efe7a325-5a7d-4b2b-9448-9dda29655b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631020924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2631020924
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4232230474
Short name T130
Test name
Test status
Simulation time 132251986 ps
CPU time 0.97 seconds
Started Apr 16 12:22:23 PM PDT 24
Finished Apr 16 12:22:25 PM PDT 24
Peak memory 196628 kb
Host smart-909728b7-60af-40ea-a548-78764094bda7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232230474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4232230474
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.435891963
Short name T346
Test name
Test status
Simulation time 285680522 ps
CPU time 3.46 seconds
Started Apr 16 12:23:20 PM PDT 24
Finished Apr 16 12:23:25 PM PDT 24
Peak memory 198148 kb
Host smart-aff851fb-7a35-4511-9c5e-41dfe57db354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435891963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.435891963
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2555021470
Short name T55
Test name
Test status
Simulation time 338034052 ps
CPU time 0.89 seconds
Started Apr 16 12:22:42 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 214740 kb
Host smart-cd28f01f-4300-4788-b238-1f12d9133ac3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555021470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2555021470
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2451535777
Short name T304
Test name
Test status
Simulation time 53907381 ps
CPU time 0.75 seconds
Started Apr 16 12:22:44 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 195292 kb
Host smart-62aa8586-9a1e-49e4-8ed0-a9ad43ecde2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451535777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2451535777
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3954060803
Short name T322
Test name
Test status
Simulation time 26802890 ps
CPU time 0.85 seconds
Started Apr 16 12:22:25 PM PDT 24
Finished Apr 16 12:22:27 PM PDT 24
Peak memory 195244 kb
Host smart-184bc023-44bf-4551-b000-1fd29958b0cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954060803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3954060803
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.656083009
Short name T3
Test name
Test status
Simulation time 27119506980 ps
CPU time 146.07 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:24:58 PM PDT 24
Peak memory 198112 kb
Host smart-b3a36522-8607-4647-ad8b-5bed58390a13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656083009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.656083009
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.15102359
Short name T649
Test name
Test status
Simulation time 33595575 ps
CPU time 0.56 seconds
Started Apr 16 12:23:16 PM PDT 24
Finished Apr 16 12:23:19 PM PDT 24
Peak memory 193840 kb
Host smart-f9d66c80-0a69-42c2-9d30-6c9916d10c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.15102359
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.963453016
Short name T586
Test name
Test status
Simulation time 36139767 ps
CPU time 0.82 seconds
Started Apr 16 12:23:14 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 195292 kb
Host smart-c5a03cd3-4f0d-4df4-a37d-244db568137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963453016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.963453016
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.999221980
Short name T344
Test name
Test status
Simulation time 616059264 ps
CPU time 14.47 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 196792 kb
Host smart-16bd696a-6c9f-485f-8a6d-bc306aa8639b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999221980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.999221980
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2903043401
Short name T6
Test name
Test status
Simulation time 92674999 ps
CPU time 0.95 seconds
Started Apr 16 12:23:14 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 197876 kb
Host smart-8e5ff0aa-cb4d-4565-9d08-2f83fb09e6e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903043401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2903043401
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2889709761
Short name T518
Test name
Test status
Simulation time 140227958 ps
CPU time 0.71 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 195444 kb
Host smart-dc08c675-7a3c-41c3-8d84-36885b0791c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889709761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2889709761
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1631259234
Short name T628
Test name
Test status
Simulation time 1182579948 ps
CPU time 3.05 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:19 PM PDT 24
Peak memory 196624 kb
Host smart-bf4f252e-82fc-4cfe-8aa2-7e9704f25964
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631259234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1631259234
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3535272891
Short name T286
Test name
Test status
Simulation time 71383970 ps
CPU time 1.55 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:15 PM PDT 24
Peak memory 196740 kb
Host smart-2408df4c-2a7d-407e-b8fc-8768c49f2c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535272891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3535272891
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.801816759
Short name T32
Test name
Test status
Simulation time 62376803 ps
CPU time 0.69 seconds
Started Apr 16 12:23:13 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 195244 kb
Host smart-90573fec-8494-4eef-927d-29d1ee68d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801816759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.801816759
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4044556160
Short name T374
Test name
Test status
Simulation time 78197979 ps
CPU time 1.04 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 195816 kb
Host smart-3f63776f-1e2e-4136-ae0a-be15c62cbc4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044556160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4044556160
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.354316542
Short name T597
Test name
Test status
Simulation time 1823525733 ps
CPU time 5.4 seconds
Started Apr 16 12:23:20 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 197988 kb
Host smart-85c4a957-da1e-47e0-b19d-7884ae070bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354316542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.354316542
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1611273889
Short name T191
Test name
Test status
Simulation time 131869218 ps
CPU time 1.4 seconds
Started Apr 16 12:23:11 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 196696 kb
Host smart-ece80a3c-a4d6-41f6-b360-a7be4cb6ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611273889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1611273889
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1525597469
Short name T238
Test name
Test status
Simulation time 59104844 ps
CPU time 1.16 seconds
Started Apr 16 12:23:13 PM PDT 24
Finished Apr 16 12:23:16 PM PDT 24
Peak memory 195672 kb
Host smart-5f239b98-9598-4a9a-9a11-594632bedcc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525597469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1525597469
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3776028121
Short name T193
Test name
Test status
Simulation time 36184735557 ps
CPU time 66.48 seconds
Started Apr 16 12:23:21 PM PDT 24
Finished Apr 16 12:24:29 PM PDT 24
Peak memory 198288 kb
Host smart-06762e24-06ba-4664-9718-54663ad199a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776028121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3776028121
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2990468484
Short name T572
Test name
Test status
Simulation time 14563324 ps
CPU time 0.57 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 194012 kb
Host smart-797dd3ff-1d59-4344-ae0f-42c0b55d5c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990468484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2990468484
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.781847421
Short name T348
Test name
Test status
Simulation time 29852343 ps
CPU time 0.71 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:26 PM PDT 24
Peak memory 194164 kb
Host smart-67364dc5-02a3-4ddc-aeb5-9a1dfe0a74f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781847421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.781847421
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3151454211
Short name T708
Test name
Test status
Simulation time 1633985285 ps
CPU time 26.62 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:44 PM PDT 24
Peak memory 197116 kb
Host smart-fd5f758c-78f8-4a2e-b31a-18d04614e809
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151454211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3151454211
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3655413886
Short name T609
Test name
Test status
Simulation time 42736859 ps
CPU time 0.78 seconds
Started Apr 16 12:23:20 PM PDT 24
Finished Apr 16 12:23:22 PM PDT 24
Peak memory 195960 kb
Host smart-388e0ac5-4e14-4442-8c12-5cd8bb2075de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655413886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3655413886
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3786296565
Short name T505
Test name
Test status
Simulation time 114757169 ps
CPU time 1.09 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 196156 kb
Host smart-acabe9ee-6a36-49ae-aa96-eda6b465da3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786296565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3786296565
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2224647096
Short name T409
Test name
Test status
Simulation time 66511909 ps
CPU time 2.55 seconds
Started Apr 16 12:23:14 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 198136 kb
Host smart-c5c415a5-2994-441c-850a-93b05ebe21b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224647096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2224647096
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1550345422
Short name T405
Test name
Test status
Simulation time 220510655 ps
CPU time 2.16 seconds
Started Apr 16 12:23:13 PM PDT 24
Finished Apr 16 12:23:17 PM PDT 24
Peak memory 198016 kb
Host smart-0b8f9653-ac4b-4546-8946-04216f2021a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550345422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1550345422
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1186283713
Short name T276
Test name
Test status
Simulation time 42232871 ps
CPU time 0.86 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 196880 kb
Host smart-38f44693-c088-448e-b370-2b82587eadba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186283713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1186283713
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.940705790
Short name T397
Test name
Test status
Simulation time 51333607 ps
CPU time 1.08 seconds
Started Apr 16 12:23:20 PM PDT 24
Finished Apr 16 12:23:22 PM PDT 24
Peak memory 196784 kb
Host smart-018026a2-0645-4b3f-a61a-4a6ba3719aaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940705790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.940705790
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.79846587
Short name T376
Test name
Test status
Simulation time 332905463 ps
CPU time 2.92 seconds
Started Apr 16 12:23:14 PM PDT 24
Finished Apr 16 12:23:19 PM PDT 24
Peak memory 198000 kb
Host smart-c519a2f0-521f-463f-8656-c1aaf8dacd95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79846587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand
om_long_reg_writes_reg_reads.79846587
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2975443398
Short name T479
Test name
Test status
Simulation time 72063236 ps
CPU time 1.25 seconds
Started Apr 16 12:23:12 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 196160 kb
Host smart-e0680cd6-a4c7-4e79-903e-a63e85ac8838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975443398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2975443398
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3426485461
Short name T470
Test name
Test status
Simulation time 19703554 ps
CPU time 0.72 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 195204 kb
Host smart-142883be-68f1-4b6c-a646-912676380860
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426485461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3426485461
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4007037723
Short name T711
Test name
Test status
Simulation time 11567861652 ps
CPU time 24.62 seconds
Started Apr 16 12:23:18 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 198080 kb
Host smart-4665977d-cd0b-4f42-9030-9e03962723bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007037723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4007037723
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1558583143
Short name T404
Test name
Test status
Simulation time 205905816695 ps
CPU time 1417.41 seconds
Started Apr 16 12:23:17 PM PDT 24
Finished Apr 16 12:46:56 PM PDT 24
Peak memory 198304 kb
Host smart-920fcd33-a00d-4680-8537-aca36320fd9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1558583143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1558583143
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2488928488
Short name T712
Test name
Test status
Simulation time 14451128 ps
CPU time 0.58 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 194072 kb
Host smart-001c880e-f45a-42b5-94ff-520d1b770f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488928488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2488928488
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1439237832
Short name T242
Test name
Test status
Simulation time 52171763 ps
CPU time 0.86 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 196008 kb
Host smart-62585af6-3de8-435a-9751-6f207d3f686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439237832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1439237832
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.520886594
Short name T674
Test name
Test status
Simulation time 214444703 ps
CPU time 3.06 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 196592 kb
Host smart-4a3fe594-ffb3-4677-9176-993d36ff7901
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520886594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.520886594
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.406072998
Short name T445
Test name
Test status
Simulation time 46058437 ps
CPU time 0.8 seconds
Started Apr 16 12:23:59 PM PDT 24
Finished Apr 16 12:24:01 PM PDT 24
Peak memory 195608 kb
Host smart-03b05223-1bcb-4e33-aa6f-0b2049eec26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406072998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.406072998
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.118080614
Short name T659
Test name
Test status
Simulation time 52684381 ps
CPU time 1.5 seconds
Started Apr 16 12:23:19 PM PDT 24
Finished Apr 16 12:23:22 PM PDT 24
Peak memory 197416 kb
Host smart-446d4102-8ada-4df9-8e75-d27357ae5cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118080614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.118080614
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3158111785
Short name T343
Test name
Test status
Simulation time 64362887 ps
CPU time 2.54 seconds
Started Apr 16 12:23:19 PM PDT 24
Finished Apr 16 12:23:24 PM PDT 24
Peak memory 198120 kb
Host smart-86a010fb-6c66-4a16-b361-1d1774fabc5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158111785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3158111785
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.184345954
Short name T658
Test name
Test status
Simulation time 95896123 ps
CPU time 1.93 seconds
Started Apr 16 12:23:19 PM PDT 24
Finished Apr 16 12:23:22 PM PDT 24
Peak memory 196504 kb
Host smart-27693870-722c-4dae-a551-d97c6a839741
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184345954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
184345954
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3477110730
Short name T199
Test name
Test status
Simulation time 35592831 ps
CPU time 1.19 seconds
Started Apr 16 12:23:17 PM PDT 24
Finished Apr 16 12:23:20 PM PDT 24
Peak memory 197000 kb
Host smart-3fa07311-9369-40c3-9099-f89f6efb0ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477110730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3477110730
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2094603345
Short name T452
Test name
Test status
Simulation time 15641611 ps
CPU time 0.67 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 194284 kb
Host smart-e2a75501-43f3-4163-beeb-797ee9808169
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094603345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2094603345
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2726441249
Short name T112
Test name
Test status
Simulation time 358958205 ps
CPU time 3.15 seconds
Started Apr 16 12:23:18 PM PDT 24
Finished Apr 16 12:23:23 PM PDT 24
Peak memory 198092 kb
Host smart-ff1514ec-7085-4776-baad-b25ec44248ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726441249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2726441249
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3352177991
Short name T444
Test name
Test status
Simulation time 60706899 ps
CPU time 1.19 seconds
Started Apr 16 12:23:19 PM PDT 24
Finished Apr 16 12:23:22 PM PDT 24
Peak memory 196740 kb
Host smart-fd72ece0-d04a-4173-a1fc-41768e124ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352177991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3352177991
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2325827478
Short name T31
Test name
Test status
Simulation time 67364503 ps
CPU time 0.91 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 196528 kb
Host smart-0723f476-a9f1-4b0c-aa33-4542d6339c41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325827478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2325827478
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.582633899
Short name T2
Test name
Test status
Simulation time 91684400888 ps
CPU time 79.01 seconds
Started Apr 16 12:23:18 PM PDT 24
Finished Apr 16 12:24:39 PM PDT 24
Peak memory 198040 kb
Host smart-7eef3ca3-0dd9-4c0a-9e5b-4a8c3b505c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582633899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.582633899
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1520105475
Short name T515
Test name
Test status
Simulation time 22675913 ps
CPU time 0.57 seconds
Started Apr 16 12:23:18 PM PDT 24
Finished Apr 16 12:23:20 PM PDT 24
Peak memory 194112 kb
Host smart-a17dd6cb-e1c3-47fd-9fac-a3b9084958f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520105475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1520105475
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2601884149
Short name T167
Test name
Test status
Simulation time 34732377 ps
CPU time 0.91 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 195700 kb
Host smart-80a409af-84dc-4f62-88ae-89fe6fc71ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601884149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2601884149
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.4186876314
Short name T412
Test name
Test status
Simulation time 188884731 ps
CPU time 9.59 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 197048 kb
Host smart-0787e2c3-e1eb-43ae-88e1-0a7fb205896d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186876314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.4186876314
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1143195425
Short name T265
Test name
Test status
Simulation time 1518001375 ps
CPU time 1.07 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:28 PM PDT 24
Peak memory 197664 kb
Host smart-63defdaa-9281-49cf-bc42-8b8c4c26cbcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143195425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1143195425
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.252910878
Short name T58
Test name
Test status
Simulation time 37418493 ps
CPU time 1.15 seconds
Started Apr 16 12:23:27 PM PDT 24
Finished Apr 16 12:23:29 PM PDT 24
Peak memory 196824 kb
Host smart-8614d9be-993e-4b2c-9174-cd5c74fed9b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252910878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.252910878
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1468845168
Short name T133
Test name
Test status
Simulation time 1785457509 ps
CPU time 3.62 seconds
Started Apr 16 12:23:27 PM PDT 24
Finished Apr 16 12:23:32 PM PDT 24
Peak memory 198180 kb
Host smart-5dd56489-cd1a-4462-8fce-7f3946601098
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468845168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1468845168
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3930585500
Short name T438
Test name
Test status
Simulation time 228304780 ps
CPU time 3.24 seconds
Started Apr 16 12:23:19 PM PDT 24
Finished Apr 16 12:23:24 PM PDT 24
Peak memory 197048 kb
Host smart-3fe094f3-3609-47f1-a215-cf2da33374bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930585500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3930585500
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2177002322
Short name T349
Test name
Test status
Simulation time 66046361 ps
CPU time 1.17 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:38 PM PDT 24
Peak memory 195800 kb
Host smart-7500da07-e776-4551-ac5d-c963a60b2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177002322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2177002322
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1972152253
Short name T306
Test name
Test status
Simulation time 88893820 ps
CPU time 0.76 seconds
Started Apr 16 12:23:18 PM PDT 24
Finished Apr 16 12:23:21 PM PDT 24
Peak memory 195540 kb
Host smart-2a678547-8785-4cec-9fd4-7fb8d903fd97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972152253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1972152253
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4133735021
Short name T642
Test name
Test status
Simulation time 115916124 ps
CPU time 5.12 seconds
Started Apr 16 12:23:27 PM PDT 24
Finished Apr 16 12:23:33 PM PDT 24
Peak memory 198180 kb
Host smart-875754ba-83b2-4229-a97f-f565ec61ab22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133735021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4133735021
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1704632075
Short name T615
Test name
Test status
Simulation time 25900982 ps
CPU time 0.91 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 195740 kb
Host smart-dd831e08-b378-4c58-8f6b-bcfa81e284ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704632075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1704632075
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2412379559
Short name T13
Test name
Test status
Simulation time 756429215 ps
CPU time 1.35 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 197964 kb
Host smart-ff601acf-3552-4453-97fa-fc7ad631ee1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412379559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2412379559
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2322038811
Short name T417
Test name
Test status
Simulation time 17624970412 ps
CPU time 170.97 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:26:32 PM PDT 24
Peak memory 198072 kb
Host smart-5570b49a-596d-4266-8a88-bfab0b27fbdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322038811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2322038811
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2412223644
Short name T638
Test name
Test status
Simulation time 201573580196 ps
CPU time 599.88 seconds
Started Apr 16 12:23:27 PM PDT 24
Finished Apr 16 12:33:28 PM PDT 24
Peak memory 198188 kb
Host smart-43df306c-bb2d-4844-be4d-983c7ff02709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2412223644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2412223644
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2658293378
Short name T174
Test name
Test status
Simulation time 13471061 ps
CPU time 0.56 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 194708 kb
Host smart-2579e2c6-380d-4754-b6a0-3977aff1823f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658293378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2658293378
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1919319864
Short name T196
Test name
Test status
Simulation time 291149021 ps
CPU time 0.79 seconds
Started Apr 16 12:23:41 PM PDT 24
Finished Apr 16 12:23:44 PM PDT 24
Peak memory 196328 kb
Host smart-03acb5fa-9704-41dc-9e58-bf4292fb9c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919319864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1919319864
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.521403049
Short name T704
Test name
Test status
Simulation time 209044227 ps
CPU time 6.8 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 196852 kb
Host smart-2d9a43cc-d503-492e-bb55-431dd18fa2dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521403049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.521403049
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.638306058
Short name T598
Test name
Test status
Simulation time 30300891 ps
CPU time 0.7 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:34 PM PDT 24
Peak memory 194860 kb
Host smart-fc24f862-236b-4e31-adbc-bfeb4c592ffd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638306058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.638306058
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3871238006
Short name T119
Test name
Test status
Simulation time 38845728 ps
CPU time 1.03 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 196084 kb
Host smart-345d58d2-5d31-430a-acea-70d39d42f7bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871238006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3871238006
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2555251370
Short name T161
Test name
Test status
Simulation time 48433295 ps
CPU time 1.18 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:38 PM PDT 24
Peak memory 196280 kb
Host smart-915750f7-47d4-4d06-aa48-c5f78d19b86e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555251370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2555251370
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1209278911
Short name T433
Test name
Test status
Simulation time 84638081 ps
CPU time 1.71 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 196076 kb
Host smart-a6fc2e2d-564c-4c26-8f31-279cb8c19074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209278911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1209278911
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2383989274
Short name T429
Test name
Test status
Simulation time 60558736 ps
CPU time 1.3 seconds
Started Apr 16 12:23:30 PM PDT 24
Finished Apr 16 12:23:32 PM PDT 24
Peak memory 196000 kb
Host smart-a3be72a3-e398-4ef0-bf4d-bce52dc62a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383989274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2383989274
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.996774891
Short name T656
Test name
Test status
Simulation time 17442485 ps
CPU time 0.64 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 194256 kb
Host smart-ced16d67-1849-422a-86e2-1872da835731
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996774891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.996774891
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3322595621
Short name T116
Test name
Test status
Simulation time 61235439 ps
CPU time 2.5 seconds
Started Apr 16 12:23:27 PM PDT 24
Finished Apr 16 12:23:31 PM PDT 24
Peak memory 197968 kb
Host smart-a11930fa-1971-4e54-9dc1-5df7f36239d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322595621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3322595621
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3185941268
Short name T317
Test name
Test status
Simulation time 73464460 ps
CPU time 1.11 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 195536 kb
Host smart-5e55b863-b8d7-4031-aebb-993132087d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185941268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3185941268
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.73094253
Short name T553
Test name
Test status
Simulation time 520944612 ps
CPU time 0.82 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 195136 kb
Host smart-b48478cd-1169-4545-9c11-a6d06db3f915
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73094253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.73094253
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3885405580
Short name T478
Test name
Test status
Simulation time 6831092706 ps
CPU time 83.34 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:25:01 PM PDT 24
Peak memory 198292 kb
Host smart-4ec7c965-077c-48a5-bb02-a6c30e394231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885405580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3885405580
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1788221990
Short name T489
Test name
Test status
Simulation time 42264659 ps
CPU time 0.55 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 193840 kb
Host smart-1391205e-4737-418e-9b1c-9ebb01578df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788221990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1788221990
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.240282884
Short name T310
Test name
Test status
Simulation time 77649233 ps
CPU time 0.88 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 197184 kb
Host smart-ed38f22a-0605-4eaf-9002-3932680c14ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240282884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.240282884
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1337176423
Short name T605
Test name
Test status
Simulation time 82522356 ps
CPU time 4.09 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:42 PM PDT 24
Peak memory 195916 kb
Host smart-c268c35c-8d24-4006-a02e-9534a4896afa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337176423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1337176423
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1282433773
Short name T523
Test name
Test status
Simulation time 291324325 ps
CPU time 1.06 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:02 PM PDT 24
Peak memory 196760 kb
Host smart-2a48ee5c-f4e5-46df-8369-0b440417cd37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282433773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1282433773
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3738271646
Short name T696
Test name
Test status
Simulation time 77735701 ps
CPU time 0.75 seconds
Started Apr 16 12:23:30 PM PDT 24
Finished Apr 16 12:23:31 PM PDT 24
Peak memory 196356 kb
Host smart-cf06fc49-91db-4f8a-8271-68b28de28d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738271646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3738271646
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3670437685
Short name T215
Test name
Test status
Simulation time 126517445 ps
CPU time 1.16 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:34 PM PDT 24
Peak memory 197856 kb
Host smart-1d946691-6a93-45aa-a9c7-1aaf78a425fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670437685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3670437685
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3064254638
Short name T493
Test name
Test status
Simulation time 63790138 ps
CPU time 0.9 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 195564 kb
Host smart-6c0556cf-1ee4-4b17-bf0b-633f541beb5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064254638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3064254638
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1697087544
Short name T312
Test name
Test status
Simulation time 132864566 ps
CPU time 1.31 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 197956 kb
Host smart-e82dad8a-73a6-4d04-ba68-8a02abf78417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697087544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1697087544
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3882391907
Short name T688
Test name
Test status
Simulation time 114005542 ps
CPU time 1.2 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 195760 kb
Host smart-edbb3e78-e869-47b6-a973-3f306d511fe7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882391907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3882391907
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.521909313
Short name T135
Test name
Test status
Simulation time 353538168 ps
CPU time 3.35 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 197976 kb
Host smart-d7576644-fbe5-4eac-bd9a-bf2fc2927ce0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521909313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.521909313
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1386156315
Short name T177
Test name
Test status
Simulation time 59924765 ps
CPU time 1.11 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 195844 kb
Host smart-8aa81d48-85b6-43d2-9122-29937151a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386156315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1386156315
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2954768504
Short name T543
Test name
Test status
Simulation time 160721353 ps
CPU time 1.15 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 195616 kb
Host smart-92d1b7ae-1499-4e49-b4c5-06e3c359fd12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954768504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2954768504
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1748289821
Short name T313
Test name
Test status
Simulation time 11716285069 ps
CPU time 56.24 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:24:31 PM PDT 24
Peak memory 198244 kb
Host smart-a9bb844c-926f-4281-8b3d-f33f2884211a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748289821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1748289821
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1457326629
Short name T35
Test name
Test status
Simulation time 55654392108 ps
CPU time 738.25 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:35:55 PM PDT 24
Peak memory 198136 kb
Host smart-e142c593-cdb5-43c3-b4df-044ad352ef2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1457326629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1457326629
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3677137709
Short name T287
Test name
Test status
Simulation time 10838367 ps
CPU time 0.55 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 194504 kb
Host smart-1d2e87df-4881-4fb1-9dd0-e6f1c6980b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677137709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3677137709
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2579333530
Short name T544
Test name
Test status
Simulation time 29744211 ps
CPU time 0.91 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 196592 kb
Host smart-e77a4b60-5d51-436d-bca3-ae995cd22565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579333530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2579333530
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1073815419
Short name T277
Test name
Test status
Simulation time 2006779201 ps
CPU time 25.98 seconds
Started Apr 16 12:24:04 PM PDT 24
Finished Apr 16 12:24:32 PM PDT 24
Peak memory 196912 kb
Host smart-6719cf97-ddce-43eb-9c6c-efbfb92905d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073815419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1073815419
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.599449413
Short name T22
Test name
Test status
Simulation time 87001643 ps
CPU time 0.92 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:34 PM PDT 24
Peak memory 196356 kb
Host smart-20f70c36-cd15-43fa-b358-f6c3db9d28ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599449413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.599449413
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3015333788
Short name T127
Test name
Test status
Simulation time 33404197 ps
CPU time 0.9 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195976 kb
Host smart-516b943f-39c1-4950-a0cc-1e0ae502c6bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015333788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3015333788
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3083181068
Short name T466
Test name
Test status
Simulation time 50832009 ps
CPU time 1.9 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 198012 kb
Host smart-3800b9f1-54e4-4341-af42-0f213873e5ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083181068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3083181068
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.900939516
Short name T351
Test name
Test status
Simulation time 77830161 ps
CPU time 1.77 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 197024 kb
Host smart-d35a2adf-2cf2-47e5-8a39-736363e6d3a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900939516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
900939516
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2680554591
Short name T527
Test name
Test status
Simulation time 123826834 ps
CPU time 1.03 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 196040 kb
Host smart-3065913d-face-417d-aaae-c480bbbff754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680554591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2680554591
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4184653412
Short name T250
Test name
Test status
Simulation time 24794506 ps
CPU time 0.7 seconds
Started Apr 16 12:23:25 PM PDT 24
Finished Apr 16 12:23:27 PM PDT 24
Peak memory 195284 kb
Host smart-764ad3f7-3956-4391-abf8-636ac2f7a8f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184653412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4184653412
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1811941510
Short name T143
Test name
Test status
Simulation time 275664584 ps
CPU time 3.77 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 197964 kb
Host smart-75011ef8-4f64-47f0-afba-3b31a1887a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811941510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1811941510
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2153517444
Short name T416
Test name
Test status
Simulation time 110085453 ps
CPU time 1.46 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 196760 kb
Host smart-34b8a34b-b0c5-48ac-8a03-cfdf7563bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153517444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2153517444
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.339917809
Short name T631
Test name
Test status
Simulation time 44518428 ps
CPU time 1.23 seconds
Started Apr 16 12:23:30 PM PDT 24
Finished Apr 16 12:23:32 PM PDT 24
Peak memory 196480 kb
Host smart-cd6435aa-1fe3-4de9-81f1-c4a2ab357a21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339917809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.339917809
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3694739396
Short name T566
Test name
Test status
Simulation time 7976016879 ps
CPU time 97.39 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:25:15 PM PDT 24
Peak memory 198036 kb
Host smart-7449eddb-fa53-4b93-ae78-c9044bd6c3a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694739396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3694739396
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1076557378
Short name T577
Test name
Test status
Simulation time 40746521 ps
CPU time 0.59 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 194608 kb
Host smart-2de08406-b3da-49be-a721-d3a780daecc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076557378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1076557378
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.535201800
Short name T600
Test name
Test status
Simulation time 38950010 ps
CPU time 0.58 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 193984 kb
Host smart-f2374a15-58bd-42ec-b7fa-ef9367936121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535201800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.535201800
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.866182487
Short name T710
Test name
Test status
Simulation time 1889722329 ps
CPU time 20.55 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 196876 kb
Host smart-b56cab55-bb31-4ea9-989b-b5a96c2e3a5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866182487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.866182487
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1777854264
Short name T296
Test name
Test status
Simulation time 129453696 ps
CPU time 0.7 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 194596 kb
Host smart-41e7c856-25ca-4d4c-8673-d1e741d914db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777854264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1777854264
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.111766352
Short name T655
Test name
Test status
Simulation time 147300357 ps
CPU time 0.85 seconds
Started Apr 16 12:23:23 PM PDT 24
Finished Apr 16 12:23:25 PM PDT 24
Peak memory 196076 kb
Host smart-e141241a-c5d5-44e8-b305-67085860b72b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111766352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.111766352
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.994715720
Short name T537
Test name
Test status
Simulation time 185202780 ps
CPU time 1.23 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 196420 kb
Host smart-a1e12499-6aae-4421-948e-964a5f77c53b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994715720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
994715720
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3176271847
Short name T414
Test name
Test status
Simulation time 176574524 ps
CPU time 0.97 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 196604 kb
Host smart-a764e4aa-cac6-4196-a62e-13761d4771a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176271847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3176271847
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3624640758
Short name T449
Test name
Test status
Simulation time 244503677 ps
CPU time 1.05 seconds
Started Apr 16 12:23:57 PM PDT 24
Finished Apr 16 12:24:00 PM PDT 24
Peak memory 196136 kb
Host smart-c7d26d01-4087-4ef0-bede-68e9093268ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624640758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3624640758
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4265131105
Short name T634
Test name
Test status
Simulation time 464882323 ps
CPU time 5.08 seconds
Started Apr 16 12:23:30 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 198148 kb
Host smart-82d75b69-ce8b-472a-be43-34011005da59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265131105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4265131105
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3229944506
Short name T383
Test name
Test status
Simulation time 88488040 ps
CPU time 0.79 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:33 PM PDT 24
Peak memory 195208 kb
Host smart-7f56fab7-627f-4057-b195-87f47129ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229944506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3229944506
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2829688466
Short name T698
Test name
Test status
Simulation time 27252493 ps
CPU time 0.86 seconds
Started Apr 16 12:23:28 PM PDT 24
Finished Apr 16 12:23:30 PM PDT 24
Peak memory 195888 kb
Host smart-fa682fc5-b9b4-491c-82b0-f37b327078c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829688466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2829688466
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3056598998
Short name T345
Test name
Test status
Simulation time 18801063785 ps
CPU time 123.85 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:25:46 PM PDT 24
Peak memory 198188 kb
Host smart-7d5984fd-eb6b-4ded-8bb7-bc784a29cef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056598998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3056598998
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2646497893
Short name T697
Test name
Test status
Simulation time 23839504 ps
CPU time 0.61 seconds
Started Apr 16 12:23:39 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 194188 kb
Host smart-b6df84c8-eda8-40e9-9666-68013bc4f8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646497893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2646497893
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.149893203
Short name T280
Test name
Test status
Simulation time 22178969 ps
CPU time 0.75 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:38 PM PDT 24
Peak memory 195192 kb
Host smart-16106067-b839-45a7-94c4-15123173b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149893203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.149893203
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1875434289
Short name T140
Test name
Test status
Simulation time 2616509437 ps
CPU time 24.54 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:24:00 PM PDT 24
Peak memory 198012 kb
Host smart-efad1310-700d-4de9-8fc6-9bbe715ef3cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875434289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1875434289
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2124076603
Short name T650
Test name
Test status
Simulation time 76867810 ps
CPU time 0.72 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195848 kb
Host smart-d3873dc8-13e1-475b-99f8-a1a65a29bef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124076603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2124076603
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3402273878
Short name T401
Test name
Test status
Simulation time 99004374 ps
CPU time 1.27 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 196824 kb
Host smart-324fa414-0659-44b9-9051-e0048ad9b3a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402273878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3402273878
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.995815305
Short name T23
Test name
Test status
Simulation time 24415320 ps
CPU time 0.99 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 196004 kb
Host smart-21a7860a-a6e2-475b-8d67-5cbd9000ff55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995815305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.995815305
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3308403189
Short name T353
Test name
Test status
Simulation time 171083397 ps
CPU time 2.49 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 197984 kb
Host smart-a5e54a4c-057b-40bd-9aa1-e323ce6f24e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308403189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3308403189
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3790557429
Short name T386
Test name
Test status
Simulation time 65056706 ps
CPU time 0.65 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:35 PM PDT 24
Peak memory 194340 kb
Host smart-8ce58d37-1f65-4761-9402-7a70b6f615a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790557429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3790557429
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2556651135
Short name T694
Test name
Test status
Simulation time 107313300 ps
CPU time 1.16 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 196916 kb
Host smart-5486a6be-a921-49b9-94af-d61273055467
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556651135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2556651135
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4214523738
Short name T360
Test name
Test status
Simulation time 68740551 ps
CPU time 1.67 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:42 PM PDT 24
Peak memory 197916 kb
Host smart-3c27fafb-6f05-4071-aee8-31d64195726e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214523738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4214523738
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.678661547
Short name T186
Test name
Test status
Simulation time 30638957 ps
CPU time 0.75 seconds
Started Apr 16 12:23:40 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 195408 kb
Host smart-2f5fae78-d540-4948-a5eb-f4e173f3ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678661547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.678661547
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3709386795
Short name T132
Test name
Test status
Simulation time 60379773 ps
CPU time 1.15 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:23:36 PM PDT 24
Peak memory 195916 kb
Host smart-0942ea95-373b-4c0b-a32b-8bef279cb61b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709386795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3709386795
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.392770596
Short name T419
Test name
Test status
Simulation time 52746874521 ps
CPU time 154.96 seconds
Started Apr 16 12:23:32 PM PDT 24
Finished Apr 16 12:26:09 PM PDT 24
Peak memory 198224 kb
Host smart-c816a494-7a6a-4063-a386-41baf3064e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392770596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.392770596
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2435841348
Short name T111
Test name
Test status
Simulation time 21800014 ps
CPU time 0.56 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 194048 kb
Host smart-91424fa6-d99d-45d2-8aeb-f41cdd055d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435841348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2435841348
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1558615278
Short name T107
Test name
Test status
Simulation time 136587878 ps
CPU time 0.75 seconds
Started Apr 16 12:23:40 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 195972 kb
Host smart-00c042d4-9954-414d-bf05-0c654777dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558615278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1558615278
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.30919895
Short name T548
Test name
Test status
Simulation time 1598411707 ps
CPU time 19.16 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 196420 kb
Host smart-d557609c-c963-4518-ad4b-974487724add
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30919895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress
.30919895
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2858061483
Short name T20
Test name
Test status
Simulation time 224448592 ps
CPU time 0.83 seconds
Started Apr 16 12:23:30 PM PDT 24
Finished Apr 16 12:23:32 PM PDT 24
Peak memory 195996 kb
Host smart-28b133c4-10e2-41e5-8309-5f0c6a2bcf98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858061483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2858061483
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2954335662
Short name T570
Test name
Test status
Simulation time 403985977 ps
CPU time 1.21 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 196844 kb
Host smart-f05d2ac3-0573-42d9-ab76-3e2557b60c85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954335662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2954335662
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.172599877
Short name T102
Test name
Test status
Simulation time 80996945 ps
CPU time 1.29 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 196332 kb
Host smart-53ddea52-39e9-4e72-a0ed-6b9263a723be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172599877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.172599877
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3291911504
Short name T311
Test name
Test status
Simulation time 129367052 ps
CPU time 0.95 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 195608 kb
Host smart-185a9313-2887-455e-bf88-4972d90da9ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291911504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3291911504
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1545471783
Short name T622
Test name
Test status
Simulation time 32089227 ps
CPU time 1 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:23:33 PM PDT 24
Peak memory 196084 kb
Host smart-f84a1bea-62f6-4afc-bbe2-3520bb0067f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545471783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1545471783
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1782241495
Short name T679
Test name
Test status
Simulation time 31414724 ps
CPU time 0.88 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 196756 kb
Host smart-ce4f1f17-5959-411a-8257-c501ecff4bd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782241495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1782241495
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3874805060
Short name T422
Test name
Test status
Simulation time 5499903501 ps
CPU time 4.48 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 198144 kb
Host smart-bf07110f-fb80-4a75-b1f6-22a2042fb0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874805060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3874805060
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1712562022
Short name T392
Test name
Test status
Simulation time 310401317 ps
CPU time 1.25 seconds
Started Apr 16 12:23:39 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 196824 kb
Host smart-fdbd550c-bff9-40d3-b9ba-95caeb335ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712562022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1712562022
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1986910213
Short name T27
Test name
Test status
Simulation time 334112168 ps
CPU time 0.88 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195212 kb
Host smart-64a03c80-de99-4efa-a634-87f1b151c25e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986910213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1986910213
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2219676447
Short name T607
Test name
Test status
Simulation time 348210457483 ps
CPU time 215.23 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:27:15 PM PDT 24
Peak memory 198236 kb
Host smart-ff25dfbf-5181-4d3c-bd41-710d380c6c72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219676447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2219676447
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.837034572
Short name T67
Test name
Test status
Simulation time 1091226652421 ps
CPU time 2346.52 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 01:02:43 PM PDT 24
Peak memory 198224 kb
Host smart-bccb6ade-ddbe-4e2b-bb30-304fa76ea681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=837034572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.837034572
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2905015367
Short name T220
Test name
Test status
Simulation time 28659355 ps
CPU time 0.55 seconds
Started Apr 16 12:22:53 PM PDT 24
Finished Apr 16 12:22:58 PM PDT 24
Peak memory 193972 kb
Host smart-ccab9d03-a7c0-4a97-b45c-71b63f88e558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905015367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2905015367
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2794645404
Short name T463
Test name
Test status
Simulation time 20831496 ps
CPU time 0.61 seconds
Started Apr 16 12:22:21 PM PDT 24
Finished Apr 16 12:22:23 PM PDT 24
Peak memory 194068 kb
Host smart-868758ae-6f12-42fc-822f-36c6869b763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794645404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2794645404
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3189803556
Short name T16
Test name
Test status
Simulation time 724753081 ps
CPU time 6.78 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:14 PM PDT 24
Peak memory 195612 kb
Host smart-4d867d02-fff9-4c82-990e-7873f5f057da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189803556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3189803556
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3287618646
Short name T33
Test name
Test status
Simulation time 21442102 ps
CPU time 0.65 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:22:33 PM PDT 24
Peak memory 195356 kb
Host smart-bdc11274-7257-4491-ab59-a57d65bdabee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287618646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3287618646
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3462922277
Short name T528
Test name
Test status
Simulation time 229965890 ps
CPU time 0.94 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 195884 kb
Host smart-a2e742c4-8951-4c43-8cab-e3cdd27976f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462922277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3462922277
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.668925775
Short name T618
Test name
Test status
Simulation time 86350898 ps
CPU time 3.63 seconds
Started Apr 16 12:22:22 PM PDT 24
Finished Apr 16 12:22:27 PM PDT 24
Peak memory 198228 kb
Host smart-6a45cdd6-2fe9-44c1-8e3e-8f14913d48bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668925775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.668925775
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3175705716
Short name T246
Test name
Test status
Simulation time 531489564 ps
CPU time 2.3 seconds
Started Apr 16 12:22:52 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 197192 kb
Host smart-c15ab622-2677-4f83-ae47-4d24e3f35813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175705716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3175705716
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.748046514
Short name T236
Test name
Test status
Simulation time 206521263 ps
CPU time 0.97 seconds
Started Apr 16 12:22:26 PM PDT 24
Finished Apr 16 12:22:29 PM PDT 24
Peak memory 196780 kb
Host smart-d2814ab5-89ea-4086-ba88-f5d55f640990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748046514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.748046514
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2135867990
Short name T63
Test name
Test status
Simulation time 34593950 ps
CPU time 0.8 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:32 PM PDT 24
Peak memory 196604 kb
Host smart-99ba8a3e-c6dc-46e4-8e0f-dba3ed4189d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135867990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2135867990
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3747060806
Short name T455
Test name
Test status
Simulation time 219036668 ps
CPU time 1.75 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 198032 kb
Host smart-b3010d2f-4b62-4115-8ddd-531012333cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747060806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3747060806
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.1329561156
Short name T123
Test name
Test status
Simulation time 123576348 ps
CPU time 1.24 seconds
Started Apr 16 12:22:27 PM PDT 24
Finished Apr 16 12:22:30 PM PDT 24
Peak memory 196536 kb
Host smart-d70842b2-821d-4133-8a67-84127151dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329561156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1329561156
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.597545501
Short name T447
Test name
Test status
Simulation time 76088907 ps
CPU time 0.94 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:23:00 PM PDT 24
Peak memory 196452 kb
Host smart-017bfef5-8096-4f32-b46b-445120b5f5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597545501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.597545501
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.754840870
Short name T695
Test name
Test status
Simulation time 11574546567 ps
CPU time 24.86 seconds
Started Apr 16 12:22:26 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 198136 kb
Host smart-5da366de-2e97-4954-adcb-063493cee0cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754840870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.754840870
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1842069525
Short name T448
Test name
Test status
Simulation time 43885019 ps
CPU time 0.55 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 194080 kb
Host smart-0bc09ef8-ab6a-4deb-b335-532ac194967c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842069525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1842069525
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1056062038
Short name T294
Test name
Test status
Simulation time 234125345 ps
CPU time 0.87 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 197012 kb
Host smart-32106fc2-8ca5-4c7d-92d3-0b0ae510c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056062038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1056062038
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2241357239
Short name T307
Test name
Test status
Simulation time 351222693 ps
CPU time 12.49 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 195528 kb
Host smart-b9c9bc34-b4cb-47a0-ae48-1f31732a02a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241357239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2241357239
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.360971772
Short name T547
Test name
Test status
Simulation time 111154139 ps
CPU time 0.8 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 195852 kb
Host smart-9df14e08-ac8e-4984-938e-29ad8a41bcdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360971772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.360971772
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2676318591
Short name T678
Test name
Test status
Simulation time 170110591 ps
CPU time 1.12 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 196156 kb
Host smart-e94fd644-c928-4484-b784-c420f7af6527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676318591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2676318591
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3509950113
Short name T146
Test name
Test status
Simulation time 147872526 ps
CPU time 2.86 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 198144 kb
Host smart-e36490ff-3c30-4070-892a-537a1ee1b272
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509950113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3509950113
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1038390686
Short name T192
Test name
Test status
Simulation time 209914426 ps
CPU time 1.16 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 196684 kb
Host smart-0d10b68c-23dc-4b54-82a4-19146da8049d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038390686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1038390686
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2974583103
Short name T333
Test name
Test status
Simulation time 19322197 ps
CPU time 0.7 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195248 kb
Host smart-c912cbb1-0ae9-4c22-8b80-debd8d031755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974583103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2974583103
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2816282187
Short name T707
Test name
Test status
Simulation time 30447266 ps
CPU time 1.05 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 196252 kb
Host smart-07b0ebd5-033e-4438-8f71-5d9aedb2010b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816282187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2816282187
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1192723213
Short name T558
Test name
Test status
Simulation time 208114920 ps
CPU time 1.61 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 198056 kb
Host smart-31413863-869f-4abe-b9e5-f368ecc41084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192723213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1192723213
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1146441150
Short name T40
Test name
Test status
Simulation time 327550583 ps
CPU time 0.99 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 196352 kb
Host smart-4e5c9823-87af-4656-b630-6226fd6ea0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146441150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1146441150
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.45645916
Short name T372
Test name
Test status
Simulation time 444958424 ps
CPU time 1.05 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 196396 kb
Host smart-abec6622-853e-4621-aed5-6272036e9e0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45645916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.45645916
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2906785175
Short name T612
Test name
Test status
Simulation time 17657259073 ps
CPU time 58.46 seconds
Started Apr 16 12:23:39 PM PDT 24
Finished Apr 16 12:24:40 PM PDT 24
Peak memory 198148 kb
Host smart-fed57e5c-fdf1-4bf2-9f58-2c263f6afde6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906785175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2906785175
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1922674359
Short name T648
Test name
Test status
Simulation time 257276891450 ps
CPU time 2427.13 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 01:04:07 PM PDT 24
Peak memory 198160 kb
Host smart-8fbd4539-90b4-4bff-bbec-a085ed0a3a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1922674359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1922674359
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1363368516
Short name T285
Test name
Test status
Simulation time 13265375 ps
CPU time 0.57 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 193984 kb
Host smart-c778fa1e-a228-4f6d-aea3-6d2f21479e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363368516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1363368516
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1890244439
Short name T12
Test name
Test status
Simulation time 45836200 ps
CPU time 0.84 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 196472 kb
Host smart-1b148fd5-3e15-4e83-83c9-f8189b7eb249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890244439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1890244439
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1219611552
Short name T425
Test name
Test status
Simulation time 659475054 ps
CPU time 5.06 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 196104 kb
Host smart-a86aca32-20a6-42b1-80ae-1d38b3922b60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219611552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1219611552
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3812558373
Short name T302
Test name
Test status
Simulation time 41955686 ps
CPU time 0.73 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195844 kb
Host smart-15d00895-0600-4363-bdde-5298941ea049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812558373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3812558373
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4186183783
Short name T437
Test name
Test status
Simulation time 100363394 ps
CPU time 1.44 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 197016 kb
Host smart-baa8df0d-5295-4392-8583-fddd0e85d7cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186183783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4186183783
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.490267816
Short name T428
Test name
Test status
Simulation time 79242834 ps
CPU time 3.01 seconds
Started Apr 16 12:23:34 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 198024 kb
Host smart-524e4506-173f-4b0a-bdf1-5d259b78c751
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490267816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.490267816
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2169937347
Short name T617
Test name
Test status
Simulation time 353561591 ps
CPU time 1.3 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 196132 kb
Host smart-98224125-2886-4ad0-bab6-4603189281cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169937347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2169937347
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.4257866275
Short name T216
Test name
Test status
Simulation time 13878006 ps
CPU time 0.66 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 194972 kb
Host smart-08eb3fdb-141e-4a8b-9460-0693dd280871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257866275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.4257866275
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3577932306
Short name T271
Test name
Test status
Simulation time 50334585 ps
CPU time 1 seconds
Started Apr 16 12:23:35 PM PDT 24
Finished Apr 16 12:23:39 PM PDT 24
Peak memory 196032 kb
Host smart-bad258cb-5067-4c63-842e-3192aa7d1752
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577932306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3577932306
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2632397831
Short name T426
Test name
Test status
Simulation time 227066008 ps
CPU time 2.54 seconds
Started Apr 16 12:23:58 PM PDT 24
Finished Apr 16 12:24:02 PM PDT 24
Peak memory 197908 kb
Host smart-cf8a3768-7565-4ed9-8889-bb00e95c70ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632397831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2632397831
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2968762364
Short name T182
Test name
Test status
Simulation time 365975514 ps
CPU time 1.33 seconds
Started Apr 16 12:23:48 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 196756 kb
Host smart-82deeda2-073b-454c-bf10-35811c0d229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968762364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2968762364
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.694651000
Short name T512
Test name
Test status
Simulation time 289583981 ps
CPU time 1.25 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 197144 kb
Host smart-d0217d0b-616b-478f-9a6e-9e80594cb6c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694651000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.694651000
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2545737258
Short name T499
Test name
Test status
Simulation time 36200217383 ps
CPU time 117.59 seconds
Started Apr 16 12:23:31 PM PDT 24
Finished Apr 16 12:25:36 PM PDT 24
Peak memory 198276 kb
Host smart-ee4ecc6e-83a5-4b29-9cb1-bf6fa306feed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545737258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2545737258
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2195432146
Short name T539
Test name
Test status
Simulation time 79815873608 ps
CPU time 1639.92 seconds
Started Apr 16 12:23:39 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 198120 kb
Host smart-20852869-4306-4adc-91c6-d29ed09f0762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2195432146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2195432146
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2875051904
Short name T234
Test name
Test status
Simulation time 29327189 ps
CPU time 0.54 seconds
Started Apr 16 12:23:49 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 194688 kb
Host smart-1b5c3995-0918-42da-a26b-8d0b4d742cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875051904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2875051904
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2176262325
Short name T252
Test name
Test status
Simulation time 48411103 ps
CPU time 0.63 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 194076 kb
Host smart-ac9723c7-440f-4b48-bbd3-5f6afbff1bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176262325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2176262325
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3271205030
Short name T555
Test name
Test status
Simulation time 1608760136 ps
CPU time 23.68 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:24:10 PM PDT 24
Peak memory 196692 kb
Host smart-13a4b50d-c561-42f4-95f9-d9cad0b5760b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271205030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3271205030
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4268085943
Short name T594
Test name
Test status
Simulation time 201747822 ps
CPU time 0.85 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:58 PM PDT 24
Peak memory 195772 kb
Host smart-b61cb2be-c9a8-40aa-a421-f4637e76c4c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268085943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4268085943
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3109094493
Short name T497
Test name
Test status
Simulation time 49478925 ps
CPU time 1.29 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:03 PM PDT 24
Peak memory 197396 kb
Host smart-9c318202-c442-46b9-9e70-020d8a226baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109094493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3109094493
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1039494833
Short name T134
Test name
Test status
Simulation time 79415216 ps
CPU time 2.86 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 198156 kb
Host smart-8c28a242-3e3c-4d69-bdd4-8cc6bb8a75be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039494833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1039494833
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4221591680
Short name T257
Test name
Test status
Simulation time 67705993 ps
CPU time 1.47 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:46 PM PDT 24
Peak memory 196124 kb
Host smart-64aa65fd-cebe-49f7-8321-5242c4dc040e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221591680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4221591680
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3960149316
Short name T61
Test name
Test status
Simulation time 54340835 ps
CPU time 0.71 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 195396 kb
Host smart-59c7e9e4-2ffd-4e7a-b135-49d7a953f702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960149316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3960149316
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3512446829
Short name T645
Test name
Test status
Simulation time 107553606 ps
CPU time 0.66 seconds
Started Apr 16 12:23:48 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 194448 kb
Host smart-a98424c8-c66d-4f56-91f8-7209331432c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512446829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3512446829
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.80815596
Short name T560
Test name
Test status
Simulation time 840100914 ps
CPU time 2.51 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:23:46 PM PDT 24
Peak memory 197900 kb
Host smart-060656bc-f11a-4d5c-a43a-ee6d69af5f93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80815596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.80815596
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3074653131
Short name T531
Test name
Test status
Simulation time 103772667 ps
CPU time 1.06 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 196672 kb
Host smart-c69fc6b4-22b4-49d7-a7c9-68d2768a0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074653131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3074653131
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2212580101
Short name T423
Test name
Test status
Simulation time 130656942 ps
CPU time 1.06 seconds
Started Apr 16 12:23:36 PM PDT 24
Finished Apr 16 12:23:40 PM PDT 24
Peak memory 195840 kb
Host smart-3fc70014-8c12-43cf-a29e-3b3cf17e2ba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212580101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2212580101
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3886089555
Short name T670
Test name
Test status
Simulation time 17438762794 ps
CPU time 62.41 seconds
Started Apr 16 12:23:48 PM PDT 24
Finished Apr 16 12:24:53 PM PDT 24
Peak memory 198356 kb
Host smart-28b53dd0-c791-4dce-84ec-b084ae769115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886089555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3886089555
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2685721201
Short name T168
Test name
Test status
Simulation time 11745510 ps
CPU time 0.58 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:57 PM PDT 24
Peak memory 193836 kb
Host smart-b8526228-8f88-4022-8ddf-57b5fb69c8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685721201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2685721201
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2600108830
Short name T487
Test name
Test status
Simulation time 82179366 ps
CPU time 0.89 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 196616 kb
Host smart-f5e977b3-3658-4b53-a9eb-8911c960e1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600108830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2600108830
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.386740420
Short name T683
Test name
Test status
Simulation time 1843696108 ps
CPU time 23.79 seconds
Started Apr 16 12:23:49 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 198084 kb
Host smart-68ad9657-a3a6-4f84-b128-1a173cf022d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386740420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.386740420
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1098810565
Short name T59
Test name
Test status
Simulation time 1607494968 ps
CPU time 1.06 seconds
Started Apr 16 12:23:40 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 196420 kb
Host smart-b656ba01-b581-41f8-a434-b3da18db9157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098810565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1098810565
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3471327682
Short name T488
Test name
Test status
Simulation time 374063611 ps
CPU time 1.01 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 195888 kb
Host smart-b290ce09-c4f4-4216-90bf-181bca5be9da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471327682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3471327682
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2639472433
Short name T262
Test name
Test status
Simulation time 211965784 ps
CPU time 3.2 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:23:59 PM PDT 24
Peak memory 198144 kb
Host smart-eb063237-a5cb-4774-b8fd-26acd4600600
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639472433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2639472433
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.364978379
Short name T567
Test name
Test status
Simulation time 132637343 ps
CPU time 2.14 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 197312 kb
Host smart-458b69f9-2eb4-4169-8b70-3052ec0a7c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364978379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
364978379
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1749601527
Short name T339
Test name
Test status
Simulation time 157605926 ps
CPU time 1.15 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:50 PM PDT 24
Peak memory 196664 kb
Host smart-8ea42b26-906f-4d39-bedd-27f3354147c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749601527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1749601527
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4143389724
Short name T627
Test name
Test status
Simulation time 47230391 ps
CPU time 0.95 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:58 PM PDT 24
Peak memory 196672 kb
Host smart-5b25a6fe-f6c6-4b90-9afe-7e1bf7bad795
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143389724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4143389724
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3578854912
Short name T4
Test name
Test status
Simulation time 531631311 ps
CPU time 5.97 seconds
Started Apr 16 12:23:56 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 198040 kb
Host smart-c08edc03-1e81-4f01-bb9a-8c60c0fe0701
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578854912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3578854912
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.322652633
Short name T183
Test name
Test status
Simulation time 69805196 ps
CPU time 1.34 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 196796 kb
Host smart-d5f617e0-b608-4b75-a602-0797417b8476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322652633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.322652633
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.183551872
Short name T103
Test name
Test status
Simulation time 66161134 ps
CPU time 1.21 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 196712 kb
Host smart-bb94fb74-5188-4ca1-b6cc-0b2a0ab68221
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183551872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.183551872
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2407635609
Short name T517
Test name
Test status
Simulation time 3908799959 ps
CPU time 53.79 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:24:41 PM PDT 24
Peak memory 198228 kb
Host smart-b0aebd4f-a352-4282-bc72-0fb6ac1a6d15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407635609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2407635609
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3636685879
Short name T68
Test name
Test status
Simulation time 246346590095 ps
CPU time 651.14 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:34:55 PM PDT 24
Peak memory 198132 kb
Host smart-2e89da5c-2961-40ae-aef1-06340b4f7699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3636685879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3636685879
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2986623772
Short name T222
Test name
Test status
Simulation time 12647641 ps
CPU time 0.57 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 194008 kb
Host smart-865728e6-8adc-4714-8644-e57681251747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986623772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2986623772
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3904359904
Short name T137
Test name
Test status
Simulation time 90804042 ps
CPU time 0.61 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 194912 kb
Host smart-7ed902a2-db3f-4be2-9907-e410c3c6a9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904359904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3904359904
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.980941491
Short name T602
Test name
Test status
Simulation time 3643313745 ps
CPU time 8.83 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 196924 kb
Host smart-eff22054-5122-4737-b7af-b82fa6359a91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980941491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.980941491
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1344683089
Short name T212
Test name
Test status
Simulation time 79908734 ps
CPU time 0.96 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 196704 kb
Host smart-ce4c8951-589d-4ff7-98db-d81af7d43b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344683089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1344683089
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3273280605
Short name T166
Test name
Test status
Simulation time 31411996 ps
CPU time 0.89 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 196272 kb
Host smart-ffa16ec9-8c42-43b4-8954-e79795d7be08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273280605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3273280605
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4256688819
Short name T19
Test name
Test status
Simulation time 310730160 ps
CPU time 3.15 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 198240 kb
Host smart-801f1020-fa58-4928-8a4e-3189daad589c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256688819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4256688819
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2842800276
Short name T283
Test name
Test status
Simulation time 283876389 ps
CPU time 1.62 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 196852 kb
Host smart-3ef1fd60-9ba1-4f46-a1f5-2301a71ecd99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842800276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2842800276
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2721955778
Short name T538
Test name
Test status
Simulation time 66821637 ps
CPU time 1.14 seconds
Started Apr 16 12:23:37 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 195984 kb
Host smart-ffc1d56d-1418-4891-9747-58345c731c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721955778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2721955778
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.949671267
Short name T225
Test name
Test status
Simulation time 135231972 ps
CPU time 1.21 seconds
Started Apr 16 12:23:41 PM PDT 24
Finished Apr 16 12:23:44 PM PDT 24
Peak memory 197244 kb
Host smart-dd07c175-58f9-4fc5-ac10-600bc1b057ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949671267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.949671267
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.357506649
Short name T461
Test name
Test status
Simulation time 390129218 ps
CPU time 4.2 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 198088 kb
Host smart-2355fe40-2825-4a44-84f8-ebd83f6e87bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357506649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.357506649
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.599414222
Short name T205
Test name
Test status
Simulation time 227880772 ps
CPU time 1.01 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 196220 kb
Host smart-9c80a5c7-fe1b-4f4d-92a1-d3f8eef44678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599414222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.599414222
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2040982239
Short name T17
Test name
Test status
Simulation time 125238844 ps
CPU time 1.07 seconds
Started Apr 16 12:23:58 PM PDT 24
Finished Apr 16 12:24:01 PM PDT 24
Peak memory 195564 kb
Host smart-9bc31693-3593-48bd-a019-f6bc8c7ba2ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040982239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2040982239
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2730662460
Short name T115
Test name
Test status
Simulation time 15839313723 ps
CPU time 205.78 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:27:10 PM PDT 24
Peak memory 198192 kb
Host smart-3fbc79a3-9d9c-4329-9433-e40c86ead177
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730662460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2730662460
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1940702442
Short name T36
Test name
Test status
Simulation time 30423428087 ps
CPU time 999.09 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:40:27 PM PDT 24
Peak memory 198172 kb
Host smart-aca25204-3860-4eb2-9787-b671deb1b176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1940702442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1940702442
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1937722304
Short name T162
Test name
Test status
Simulation time 47013236 ps
CPU time 0.55 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:46 PM PDT 24
Peak memory 193892 kb
Host smart-9289608a-0d3e-4e4e-a0e6-189d5d9ae0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937722304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1937722304
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.382358520
Short name T584
Test name
Test status
Simulation time 148617235 ps
CPU time 0.67 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 195172 kb
Host smart-3637da90-4338-4ee7-8feb-5923fe01c5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382358520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.382358520
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.4244062954
Short name T340
Test name
Test status
Simulation time 134171619 ps
CPU time 4.02 seconds
Started Apr 16 12:23:52 PM PDT 24
Finished Apr 16 12:23:59 PM PDT 24
Peak memory 195496 kb
Host smart-9c1d8d55-00f3-41a3-a8c8-26acfa59c76d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244062954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.4244062954
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3217085092
Short name T639
Test name
Test status
Simulation time 316294311 ps
CPU time 0.9 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 197628 kb
Host smart-39c9ffa6-4669-4858-a06f-d8595d9f9336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217085092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3217085092
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1090148334
Short name T197
Test name
Test status
Simulation time 150629743 ps
CPU time 0.71 seconds
Started Apr 16 12:23:52 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 195628 kb
Host smart-e5fd0292-de9f-41c5-93d3-11befa67b2b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090148334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1090148334
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2474153266
Short name T114
Test name
Test status
Simulation time 49775072 ps
CPU time 1.16 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 196904 kb
Host smart-dce9e563-4d7a-4d45-be11-bb17589af8a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474153266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2474153266
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2682995782
Short name T172
Test name
Test status
Simulation time 269170895 ps
CPU time 2.31 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 198012 kb
Host smart-832e521a-41d1-41a3-b254-afa05eaad3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682995782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2682995782
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1636920529
Short name T381
Test name
Test status
Simulation time 70588358 ps
CPU time 1.09 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:58 PM PDT 24
Peak memory 196068 kb
Host smart-70187ac9-7a8d-4048-ad60-88542bd5ce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636920529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1636920529
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.342636431
Short name T402
Test name
Test status
Simulation time 67068003 ps
CPU time 0.84 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 197216 kb
Host smart-193039d2-05aa-4c61-8df6-aa331e68a72a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342636431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.342636431
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1235655350
Short name T337
Test name
Test status
Simulation time 3965552268 ps
CPU time 4.55 seconds
Started Apr 16 12:23:48 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 198152 kb
Host smart-5a0aea85-c054-44a1-be48-ccd37c44e1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235655350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1235655350
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3757753107
Short name T210
Test name
Test status
Simulation time 384484913 ps
CPU time 0.97 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:41 PM PDT 24
Peak memory 195616 kb
Host smart-932b0a06-48c0-45dd-9dfe-f8831db7830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757753107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3757753107
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4183491661
Short name T689
Test name
Test status
Simulation time 179189736 ps
CPU time 0.94 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 196340 kb
Host smart-d3277d20-5a2d-4c7a-ab19-0a527d236572
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183491661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4183491661
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2852950240
Short name T410
Test name
Test status
Simulation time 43878249610 ps
CPU time 74.9 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:25:12 PM PDT 24
Peak memory 198048 kb
Host smart-b6a49cb8-0c27-4e38-9dc3-c04a1f2b2e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852950240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2852950240
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2923004163
Short name T661
Test name
Test status
Simulation time 18332600 ps
CPU time 0.58 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 193860 kb
Host smart-e3d6b097-a3bd-4432-a9ce-13e642097de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923004163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2923004163
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1906076353
Short name T319
Test name
Test status
Simulation time 189882715 ps
CPU time 0.82 seconds
Started Apr 16 12:23:40 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 196332 kb
Host smart-1538058f-9bc9-4d35-a74e-a112b7ecdb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906076353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1906076353
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3456492112
Short name T226
Test name
Test status
Simulation time 926837572 ps
CPU time 7.29 seconds
Started Apr 16 12:23:57 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 197964 kb
Host smart-016ee8c1-f547-410b-8c90-686e7d12a938
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456492112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3456492112
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3416831214
Short name T157
Test name
Test status
Simulation time 242298823 ps
CPU time 0.92 seconds
Started Apr 16 12:23:49 PM PDT 24
Finished Apr 16 12:23:53 PM PDT 24
Peak memory 197624 kb
Host smart-33078b96-9df2-4249-b30c-0367a6eb9b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416831214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3416831214
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1755510357
Short name T691
Test name
Test status
Simulation time 296339890 ps
CPU time 1.1 seconds
Started Apr 16 12:23:42 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 196028 kb
Host smart-62f7b226-7752-433f-baf1-26beb11fd544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755510357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1755510357
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1898045156
Short name T190
Test name
Test status
Simulation time 180162029 ps
CPU time 3.45 seconds
Started Apr 16 12:23:58 PM PDT 24
Finished Apr 16 12:24:03 PM PDT 24
Peak memory 198192 kb
Host smart-db5a5a9a-5197-4d36-9761-f2406e1a2583
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898045156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1898045156
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.398584335
Short name T368
Test name
Test status
Simulation time 179793704 ps
CPU time 2.71 seconds
Started Apr 16 12:23:49 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 198076 kb
Host smart-b6b6d1ad-42c2-4cbd-92de-47d9eb77ec54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398584335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
398584335
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1606629820
Short name T571
Test name
Test status
Simulation time 65923086 ps
CPU time 0.78 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 195640 kb
Host smart-3d7d4bf5-1004-4387-a58b-45579c287cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606629820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1606629820
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2756321089
Short name T221
Test name
Test status
Simulation time 30132512 ps
CPU time 0.7 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 195544 kb
Host smart-4a1078e1-9d67-4169-aa15-ce50d4c57879
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756321089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2756321089
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3053514136
Short name T579
Test name
Test status
Simulation time 110413597 ps
CPU time 1.35 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:23:48 PM PDT 24
Peak memory 198000 kb
Host smart-140e7abf-0c3e-4896-8923-981fd8392a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053514136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3053514136
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.30897742
Short name T211
Test name
Test status
Simulation time 160353079 ps
CPU time 1.14 seconds
Started Apr 16 12:23:41 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 195744 kb
Host smart-45beec7b-566f-4bc0-a0fd-78059f6be912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30897742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.30897742
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.968986882
Short name T155
Test name
Test status
Simulation time 65092700 ps
CPU time 1.17 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 195872 kb
Host smart-766b3d66-66bc-4118-a4c1-fe5625921cff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968986882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.968986882
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3156074874
Short name T475
Test name
Test status
Simulation time 4290367883 ps
CPU time 101.33 seconds
Started Apr 16 12:23:44 PM PDT 24
Finished Apr 16 12:25:28 PM PDT 24
Peak memory 198236 kb
Host smart-5f3e7a9b-8fd3-4adb-91cf-1c1aed725ac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156074874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3156074874
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2732789035
Short name T601
Test name
Test status
Simulation time 39322380 ps
CPU time 0.57 seconds
Started Apr 16 12:23:41 PM PDT 24
Finished Apr 16 12:23:43 PM PDT 24
Peak memory 195712 kb
Host smart-d3e71bf4-4fb0-465b-9ca1-6f49ca6895b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732789035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2732789035
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.455659208
Short name T511
Test name
Test status
Simulation time 241497883 ps
CPU time 0.68 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 194128 kb
Host smart-bf9b448b-cec6-46be-94d5-8b04de2aa889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455659208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.455659208
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.425555251
Short name T681
Test name
Test status
Simulation time 143096032 ps
CPU time 5.19 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:46 PM PDT 24
Peak memory 196880 kb
Host smart-7bda1435-e986-48cf-83c2-fb7919c65e6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425555251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.425555251
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2088802187
Short name T559
Test name
Test status
Simulation time 50025479 ps
CPU time 0.78 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 196024 kb
Host smart-246b64fd-0936-49b7-983f-8d37d0cefe18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088802187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2088802187
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3680973448
Short name T330
Test name
Test status
Simulation time 34969624 ps
CPU time 0.99 seconds
Started Apr 16 12:23:43 PM PDT 24
Finished Apr 16 12:23:46 PM PDT 24
Peak memory 196176 kb
Host smart-1ec64a9b-2fa4-4f9f-bb16-02e680b21e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680973448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3680973448
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3472594978
Short name T201
Test name
Test status
Simulation time 223469947 ps
CPU time 1.77 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 198152 kb
Host smart-22ea65ca-3f63-42b5-a880-ee9e65fe24e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472594978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3472594978
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1888400528
Short name T676
Test name
Test status
Simulation time 84640114 ps
CPU time 1.67 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 196020 kb
Host smart-a5b77208-4190-496f-9cc6-b952ac2b7383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888400528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1888400528
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2888143189
Short name T643
Test name
Test status
Simulation time 151080076 ps
CPU time 1.04 seconds
Started Apr 16 12:23:52 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 196124 kb
Host smart-b1fb37ab-0186-426e-95b0-cebe75c1783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888143189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2888143189
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1664827567
Short name T554
Test name
Test status
Simulation time 218238011 ps
CPU time 1.11 seconds
Started Apr 16 12:23:49 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 198196 kb
Host smart-dcc3bc43-6d2d-4441-8745-4a73bf5bf38f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664827567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1664827567
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1684582609
Short name T569
Test name
Test status
Simulation time 240021024 ps
CPU time 1.68 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 198088 kb
Host smart-3c6f3bd3-ce2a-4e5e-8e11-6e78ee9402b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684582609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1684582609
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.342655836
Short name T327
Test name
Test status
Simulation time 335378615 ps
CPU time 1.27 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:23:57 PM PDT 24
Peak memory 195508 kb
Host smart-aca225fe-b741-4da8-b9f2-0cee3ce6ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342655836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.342655836
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2580649240
Short name T299
Test name
Test status
Simulation time 80777442 ps
CPU time 1.4 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 198140 kb
Host smart-4c7fba32-1dac-424f-8cd7-53d72b856127
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580649240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2580649240
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3319558097
Short name T7
Test name
Test status
Simulation time 22488343640 ps
CPU time 62.18 seconds
Started Apr 16 12:23:40 PM PDT 24
Finished Apr 16 12:24:45 PM PDT 24
Peak memory 198040 kb
Host smart-d5cebf60-c1a6-405a-8a36-1ee33eb7d184
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319558097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3319558097
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2046655510
Short name T28
Test name
Test status
Simulation time 33627873 ps
CPU time 0.62 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 193892 kb
Host smart-a4ea3c3c-7437-4b87-badd-7d4b35febab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046655510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2046655510
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.3790838026
Short name T432
Test name
Test status
Simulation time 25546118 ps
CPU time 0.74 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:08 PM PDT 24
Peak memory 195436 kb
Host smart-cabdf09d-ca5f-4ef1-aee0-080263bda7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790838026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.3790838026
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.733442635
Short name T371
Test name
Test status
Simulation time 355604800 ps
CPU time 4.17 seconds
Started Apr 16 12:23:57 PM PDT 24
Finished Apr 16 12:24:03 PM PDT 24
Peak memory 195816 kb
Host smart-84493041-04c9-4915-a40e-aa957de9b522
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733442635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.733442635
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.361459518
Short name T705
Test name
Test status
Simulation time 184278394 ps
CPU time 0.89 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 197372 kb
Host smart-1d89f5dc-af6c-4ca3-a0d4-323bf3bc60b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361459518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.361459518
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2432540238
Short name T120
Test name
Test status
Simulation time 599378863 ps
CPU time 1.15 seconds
Started Apr 16 12:23:52 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 196624 kb
Host smart-d2a2e904-562e-47ef-8c5b-9e641958da96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432540238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2432540238
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3692721031
Short name T507
Test name
Test status
Simulation time 74285347 ps
CPU time 2.62 seconds
Started Apr 16 12:23:57 PM PDT 24
Finished Apr 16 12:24:01 PM PDT 24
Peak memory 198048 kb
Host smart-77faf71c-c646-4242-9f1c-6a53dc27c27b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692721031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3692721031
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.50615055
Short name T534
Test name
Test status
Simulation time 158450251 ps
CPU time 2.85 seconds
Started Apr 16 12:23:59 PM PDT 24
Finished Apr 16 12:24:03 PM PDT 24
Peak memory 198100 kb
Host smart-3bd5c26a-1d17-42ca-b63a-6b75dd881287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50615055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.50615055
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1413134443
Short name T663
Test name
Test status
Simulation time 33211411 ps
CPU time 1.16 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:58 PM PDT 24
Peak memory 195968 kb
Host smart-a804f958-d058-4587-98de-6e222191c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413134443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1413134443
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1961026672
Short name T568
Test name
Test status
Simulation time 53811814 ps
CPU time 1.14 seconds
Started Apr 16 12:24:01 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 196040 kb
Host smart-96fc86bd-63f9-4686-a40d-d4880e44ea04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961026672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1961026672
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3142063514
Short name T503
Test name
Test status
Simulation time 189033317 ps
CPU time 1.17 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 198160 kb
Host smart-9fba1219-0cde-4f2b-a78c-ce2a9fc7e99e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142063514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3142063514
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1323950727
Short name T358
Test name
Test status
Simulation time 155810480 ps
CPU time 1.29 seconds
Started Apr 16 12:23:51 PM PDT 24
Finished Apr 16 12:23:55 PM PDT 24
Peak memory 198128 kb
Host smart-c62228d7-a48e-4ec8-bcac-07667e8ba8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323950727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1323950727
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.728028932
Short name T413
Test name
Test status
Simulation time 103454158 ps
CPU time 0.9 seconds
Started Apr 16 12:24:01 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 196520 kb
Host smart-57e2a07e-e512-42be-8881-6794da4ac30f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728028932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.728028932
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2896507073
Short name T164
Test name
Test status
Simulation time 13658240652 ps
CPU time 167.68 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:26:58 PM PDT 24
Peak memory 198156 kb
Host smart-9e767304-11db-422d-b95b-3523344942cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896507073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2896507073
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1437653069
Short name T66
Test name
Test status
Simulation time 111857728979 ps
CPU time 1456.98 seconds
Started Apr 16 12:24:04 PM PDT 24
Finished Apr 16 12:48:23 PM PDT 24
Peak memory 198176 kb
Host smart-8a237e9f-5597-4c0d-b912-1a4c42eb9aa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1437653069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1437653069
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.4188114577
Short name T256
Test name
Test status
Simulation time 28857079 ps
CPU time 0.54 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:02 PM PDT 24
Peak memory 193920 kb
Host smart-f079343c-301a-4cbd-bff2-05b3f144406a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188114577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.4188114577
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3990153685
Short name T641
Test name
Test status
Simulation time 15430066 ps
CPU time 0.62 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:08 PM PDT 24
Peak memory 194624 kb
Host smart-078e39c4-25d5-40e4-81fb-eb05356b3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990153685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3990153685
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3232543638
Short name T616
Test name
Test status
Simulation time 216723521 ps
CPU time 10.89 seconds
Started Apr 16 12:24:01 PM PDT 24
Finished Apr 16 12:24:14 PM PDT 24
Peak memory 196268 kb
Host smart-101a685a-818f-448c-b9e0-f0ec70f504d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232543638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3232543638
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3900807054
Short name T620
Test name
Test status
Simulation time 80733796 ps
CPU time 0.97 seconds
Started Apr 16 12:24:04 PM PDT 24
Finished Apr 16 12:24:08 PM PDT 24
Peak memory 197212 kb
Host smart-2758fc63-f6dc-4315-ac92-f763401b6db1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900807054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3900807054
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.676885261
Short name T336
Test name
Test status
Simulation time 107753217 ps
CPU time 0.84 seconds
Started Apr 16 12:24:01 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 196472 kb
Host smart-85d25948-57ec-46f1-8934-bc5b1931f343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676885261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.676885261
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1672398535
Short name T275
Test name
Test status
Simulation time 141455497 ps
CPU time 1.6 seconds
Started Apr 16 12:23:57 PM PDT 24
Finished Apr 16 12:24:00 PM PDT 24
Peak memory 196700 kb
Host smart-a602c4ac-fe9c-4e70-9391-2023ec0bd3a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672398535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1672398535
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.562775407
Short name T213
Test name
Test status
Simulation time 495201205 ps
CPU time 3.41 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:24:07 PM PDT 24
Peak memory 198020 kb
Host smart-a3b1e80d-bbe6-4fbc-aa71-3f37d4deaac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562775407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
562775407
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.582048667
Short name T227
Test name
Test status
Simulation time 191646128 ps
CPU time 1.1 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:20 PM PDT 24
Peak memory 196524 kb
Host smart-9f7ac9d1-8d71-496c-b01d-cf7ac0d1e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582048667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.582048667
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.890790170
Short name T451
Test name
Test status
Simulation time 35243637 ps
CPU time 0.89 seconds
Started Apr 16 12:24:16 PM PDT 24
Finished Apr 16 12:24:20 PM PDT 24
Peak memory 197376 kb
Host smart-6c65ad37-fe57-4a4f-9226-7f60c7b89bb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890790170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.890790170
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2971963278
Short name T171
Test name
Test status
Simulation time 742806809 ps
CPU time 5.96 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:20 PM PDT 24
Peak memory 198028 kb
Host smart-c016f332-3c1e-4387-bc00-9c1897ba085e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971963278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2971963278
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.235914710
Short name T288
Test name
Test status
Simulation time 321537713 ps
CPU time 1.3 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 197084 kb
Host smart-1321ec81-4f30-41ba-b8e0-975dbf123847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235914710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.235914710
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2771048313
Short name T308
Test name
Test status
Simulation time 125628946 ps
CPU time 1.14 seconds
Started Apr 16 12:24:01 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 195764 kb
Host smart-2bf24b38-b853-4344-9335-749e8c193279
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771048313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2771048313
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.686619021
Short name T680
Test name
Test status
Simulation time 31449180448 ps
CPU time 90.85 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:25:27 PM PDT 24
Peak memory 198240 kb
Host smart-ce16f900-b21d-481c-b54d-f074a506a66f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686619021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.686619021
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.135903751
Short name T668
Test name
Test status
Simulation time 12215188 ps
CPU time 0.56 seconds
Started Apr 16 12:23:45 PM PDT 24
Finished Apr 16 12:23:49 PM PDT 24
Peak memory 193820 kb
Host smart-9370dedb-7cfd-414d-8b50-2714571b988d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135903751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.135903751
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1491240245
Short name T379
Test name
Test status
Simulation time 134533125 ps
CPU time 0.87 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:32 PM PDT 24
Peak memory 196620 kb
Host smart-b69c3ff3-0d80-4aab-af3b-671a2e93dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491240245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1491240245
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4045996523
Short name T477
Test name
Test status
Simulation time 530437062 ps
CPU time 25.48 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:56 PM PDT 24
Peak memory 197952 kb
Host smart-1e5c85b7-8b49-4cdf-bfc7-03c4e0310179
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045996523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4045996523
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3056498182
Short name T591
Test name
Test status
Simulation time 72033251 ps
CPU time 0.59 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:32 PM PDT 24
Peak memory 195148 kb
Host smart-db3716f7-0a2d-4f17-a37f-3681ee6897af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056498182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3056498182
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.913734266
Short name T535
Test name
Test status
Simulation time 124985294 ps
CPU time 1.02 seconds
Started Apr 16 12:22:28 PM PDT 24
Finished Apr 16 12:22:30 PM PDT 24
Peak memory 196512 kb
Host smart-8df18aa5-9c95-4bbd-88ea-116784b211a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913734266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.913734266
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3339990619
Short name T11
Test name
Test status
Simulation time 86041209 ps
CPU time 3.34 seconds
Started Apr 16 12:22:26 PM PDT 24
Finished Apr 16 12:22:31 PM PDT 24
Peak memory 198180 kb
Host smart-6d82adca-73cc-4a44-83a6-2a4d2ba81487
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339990619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3339990619
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1863689316
Short name T267
Test name
Test status
Simulation time 186829676 ps
CPU time 1.78 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:33 PM PDT 24
Peak memory 195940 kb
Host smart-833b161b-bd8a-4fef-8c0b-9f4a6121e188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863689316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1863689316
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.782643208
Short name T699
Test name
Test status
Simulation time 81470273 ps
CPU time 1.16 seconds
Started Apr 16 12:22:25 PM PDT 24
Finished Apr 16 12:22:28 PM PDT 24
Peak memory 197168 kb
Host smart-a0c79fbe-5597-403d-b71b-4b5b742b0789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782643208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.782643208
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2860840827
Short name T440
Test name
Test status
Simulation time 66847435 ps
CPU time 1.19 seconds
Started Apr 16 12:22:24 PM PDT 24
Finished Apr 16 12:22:27 PM PDT 24
Peak memory 197264 kb
Host smart-8799f72b-282e-4306-9139-447874b3f610
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860840827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2860840827
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3718732524
Short name T255
Test name
Test status
Simulation time 123709912 ps
CPU time 5.49 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:22:56 PM PDT 24
Peak memory 198076 kb
Host smart-98f97faa-d809-4b0c-8255-4795b0b0369a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718732524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3718732524
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1892829444
Short name T42
Test name
Test status
Simulation time 423929802 ps
CPU time 0.92 seconds
Started Apr 16 12:22:54 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 214708 kb
Host smart-4f2b7a64-fbc5-42c8-8912-5907ceaa0433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892829444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1892829444
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3131565136
Short name T673
Test name
Test status
Simulation time 100740254 ps
CPU time 1.29 seconds
Started Apr 16 12:22:28 PM PDT 24
Finished Apr 16 12:22:30 PM PDT 24
Peak memory 196728 kb
Host smart-f68b6811-d78b-42e4-b20d-467a0258335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131565136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3131565136
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3345055374
Short name T297
Test name
Test status
Simulation time 77465045 ps
CPU time 1.19 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 196180 kb
Host smart-0e8a6330-5f08-4563-970f-769f065318b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345055374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3345055374
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1095970593
Short name T431
Test name
Test status
Simulation time 28308575894 ps
CPU time 30.13 seconds
Started Apr 16 12:23:15 PM PDT 24
Finished Apr 16 12:23:47 PM PDT 24
Peak memory 198168 kb
Host smart-3fe0496d-fc99-4b75-ba33-1406bc36ee79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095970593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1095970593
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3434112104
Short name T491
Test name
Test status
Simulation time 18811774052 ps
CPU time 182.01 seconds
Started Apr 16 12:22:25 PM PDT 24
Finished Apr 16 12:25:29 PM PDT 24
Peak memory 198228 kb
Host smart-0c9bdf99-5a59-4a88-8488-d1bef1d77b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3434112104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3434112104
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.35401082
Short name T637
Test name
Test status
Simulation time 35195385 ps
CPU time 0.57 seconds
Started Apr 16 12:24:18 PM PDT 24
Finished Apr 16 12:24:22 PM PDT 24
Peak memory 194584 kb
Host smart-3b3b141a-0213-40a6-a033-63320f674da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35401082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.35401082
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.93782886
Short name T178
Test name
Test status
Simulation time 72203972 ps
CPU time 0.67 seconds
Started Apr 16 12:24:03 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 193836 kb
Host smart-119b7b0a-102e-4b51-bf3c-4c395216a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93782886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.93782886
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.422159349
Short name T504
Test name
Test status
Simulation time 958360835 ps
CPU time 7.62 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:19 PM PDT 24
Peak memory 196496 kb
Host smart-60079468-faf0-4b9e-af0f-696478d52019
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422159349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.422159349
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3837419500
Short name T406
Test name
Test status
Simulation time 712443580 ps
CPU time 0.89 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 196328 kb
Host smart-bb14c89f-6ad5-4464-a4a4-1a8fe53a68b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837419500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3837419500
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.676634932
Short name T245
Test name
Test status
Simulation time 167039321 ps
CPU time 1.24 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:10 PM PDT 24
Peak memory 196712 kb
Host smart-f0e348b6-dd2f-4942-a5bc-399681e0cb26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676634932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.676634932
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.795105844
Short name T325
Test name
Test status
Simulation time 96031250 ps
CPU time 2.07 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 198052 kb
Host smart-3dbb682d-74f5-47ce-83f6-fcd9544e0c7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795105844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.795105844
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2482723325
Short name T632
Test name
Test status
Simulation time 171042814 ps
CPU time 3.12 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 198044 kb
Host smart-a4d9e5c5-b963-472d-9b51-5e36ba550736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482723325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2482723325
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.555838354
Short name T180
Test name
Test status
Simulation time 228185138 ps
CPU time 1.2 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:24:14 PM PDT 24
Peak memory 196008 kb
Host smart-20e858c2-39df-40a6-b8aa-233488530f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555838354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.555838354
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1976173837
Short name T514
Test name
Test status
Simulation time 50972765 ps
CPU time 1.05 seconds
Started Apr 16 12:23:59 PM PDT 24
Finished Apr 16 12:24:01 PM PDT 24
Peak memory 196104 kb
Host smart-af8b9ac9-c685-4922-b5b8-15e933fd9da3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976173837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1976173837
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2319269026
Short name T5
Test name
Test status
Simulation time 665189624 ps
CPU time 4.6 seconds
Started Apr 16 12:23:58 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 197940 kb
Host smart-83dddb18-e224-4d73-9aa1-33fead9f2a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319269026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2319269026
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2044275521
Short name T198
Test name
Test status
Simulation time 42581127 ps
CPU time 1.14 seconds
Started Apr 16 12:24:02 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 196240 kb
Host smart-0b2bcb57-2546-489b-91cc-3fc0cafcf909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044275521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2044275521
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.414752377
Short name T574
Test name
Test status
Simulation time 172999925 ps
CPU time 1.32 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:02 PM PDT 24
Peak memory 196924 kb
Host smart-eefbc291-d834-47bd-9604-92ff8722929e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414752377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.414752377
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3198373300
Short name T377
Test name
Test status
Simulation time 88609948179 ps
CPU time 164.57 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:26:52 PM PDT 24
Peak memory 198244 kb
Host smart-bba95679-575d-4b9a-92ca-1b7f84d54752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198373300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3198373300
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2913950785
Short name T209
Test name
Test status
Simulation time 35815255 ps
CPU time 0.59 seconds
Started Apr 16 12:24:26 PM PDT 24
Finished Apr 16 12:24:31 PM PDT 24
Peak memory 194208 kb
Host smart-8fffb1e6-c376-4d13-a785-cddca8c9369e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913950785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2913950785
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.327022164
Short name T141
Test name
Test status
Simulation time 383601455 ps
CPU time 0.84 seconds
Started Apr 16 12:24:13 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 195408 kb
Host smart-ad820cbc-0c35-4dfc-b8d8-e449dc9a1222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327022164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.327022164
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1372035829
Short name T526
Test name
Test status
Simulation time 264679226 ps
CPU time 8.01 seconds
Started Apr 16 12:23:53 PM PDT 24
Finished Apr 16 12:24:04 PM PDT 24
Peak memory 196352 kb
Host smart-604b9016-cf29-4912-8286-e82a7737fe63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372035829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1372035829
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.991265471
Short name T471
Test name
Test status
Simulation time 30203956 ps
CPU time 0.65 seconds
Started Apr 16 12:24:11 PM PDT 24
Finished Apr 16 12:24:13 PM PDT 24
Peak memory 194472 kb
Host smart-813d9369-0c5a-4b25-b054-0dee406c0f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991265471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.991265471
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1789410481
Short name T495
Test name
Test status
Simulation time 100073149 ps
CPU time 0.89 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 196616 kb
Host smart-cd4a1e90-4b71-4962-9688-c63c1de7099b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789410481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1789410481
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2449355882
Short name T484
Test name
Test status
Simulation time 456039699 ps
CPU time 1.38 seconds
Started Apr 16 12:23:50 PM PDT 24
Finished Apr 16 12:23:54 PM PDT 24
Peak memory 197080 kb
Host smart-d71b2ed3-a593-4b5f-9810-af835ac4b268
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449355882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2449355882
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2155058036
Short name T230
Test name
Test status
Simulation time 79189989 ps
CPU time 1.83 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:10 PM PDT 24
Peak memory 196812 kb
Host smart-7f2ac95e-b10f-40d5-8715-6497f8913e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155058036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2155058036
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1160874786
Short name T303
Test name
Test status
Simulation time 122375119 ps
CPU time 1.2 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 197144 kb
Host smart-b1377dc5-e12b-4931-8023-0976fc6b4ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160874786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1160874786
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.100601441
Short name T474
Test name
Test status
Simulation time 252317616 ps
CPU time 0.92 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 195992 kb
Host smart-8674f479-6366-4578-81c2-4324bd38dc31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100601441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.100601441
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3295781420
Short name T585
Test name
Test status
Simulation time 1000005722 ps
CPU time 3.66 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:13 PM PDT 24
Peak memory 197908 kb
Host smart-6a7134cd-04f1-4286-90cd-03999e0a2845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295781420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3295781420
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.795335674
Short name T206
Test name
Test status
Simulation time 23792310 ps
CPU time 0.83 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:02 PM PDT 24
Peak memory 195928 kb
Host smart-6a6fe6ae-112f-456b-8f3e-53d81c33a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795335674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.795335674
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3771167078
Short name T459
Test name
Test status
Simulation time 72347427 ps
CPU time 1.31 seconds
Started Apr 16 12:23:55 PM PDT 24
Finished Apr 16 12:23:58 PM PDT 24
Peak memory 196968 kb
Host smart-ad99888c-e374-437c-ac68-bb22afedc531
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771167078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3771167078
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2495103658
Short name T110
Test name
Test status
Simulation time 29867982033 ps
CPU time 183.93 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:27:14 PM PDT 24
Peak memory 198200 kb
Host smart-b9b06b65-d851-4dcc-bb3b-26b093a585a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495103658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2495103658
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2813579083
Short name T15
Test name
Test status
Simulation time 39091391 ps
CPU time 0.55 seconds
Started Apr 16 12:24:33 PM PDT 24
Finished Apr 16 12:24:36 PM PDT 24
Peak memory 194816 kb
Host smart-22879a3a-10a3-4d33-8704-25238caeaf18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813579083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2813579083
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4180134317
Short name T546
Test name
Test status
Simulation time 53338672 ps
CPU time 0.77 seconds
Started Apr 16 12:24:32 PM PDT 24
Finished Apr 16 12:24:36 PM PDT 24
Peak memory 195348 kb
Host smart-4175136b-facb-412c-b6d5-3bb8469f3e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180134317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4180134317
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2094557566
Short name T530
Test name
Test status
Simulation time 644730537 ps
CPU time 20.62 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:23 PM PDT 24
Peak memory 196712 kb
Host smart-fed2b69a-3020-4095-8d81-0edcc40462d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094557566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2094557566
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3165994334
Short name T524
Test name
Test status
Simulation time 51727002 ps
CPU time 0.86 seconds
Started Apr 16 12:24:32 PM PDT 24
Finished Apr 16 12:24:36 PM PDT 24
Peak memory 196888 kb
Host smart-0a5457e2-2a40-41c4-9aae-3e9bd1733b1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165994334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3165994334
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1953208766
Short name T467
Test name
Test status
Simulation time 64374307 ps
CPU time 1.1 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:03 PM PDT 24
Peak memory 195712 kb
Host smart-df1612bf-a071-4228-ac53-85fda957a5c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953208766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1953208766
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3365489776
Short name T469
Test name
Test status
Simulation time 557903926 ps
CPU time 2.97 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:24:15 PM PDT 24
Peak memory 198156 kb
Host smart-379348ba-d96a-4886-bb7b-15d908f01012
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365489776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3365489776
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.513649762
Short name T165
Test name
Test status
Simulation time 146654822 ps
CPU time 1.13 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:24:14 PM PDT 24
Peak memory 195612 kb
Host smart-c30b803f-3231-4f4b-8b25-6b019c1cfca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513649762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
513649762
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2757617428
Short name T202
Test name
Test status
Simulation time 87635117 ps
CPU time 1.01 seconds
Started Apr 16 12:24:33 PM PDT 24
Finished Apr 16 12:24:41 PM PDT 24
Peak memory 195884 kb
Host smart-dcf28ef1-3fb1-42fb-addd-617e52844254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757617428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2757617428
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2354200293
Short name T456
Test name
Test status
Simulation time 195480254 ps
CPU time 1.02 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 195960 kb
Host smart-dcca34a7-080c-4007-a9fc-bc63435d451d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354200293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2354200293
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3288668110
Short name T145
Test name
Test status
Simulation time 207701847 ps
CPU time 3.35 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:14 PM PDT 24
Peak memory 198004 kb
Host smart-e03bb43b-91cf-4aec-9a53-161d2a4240ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288668110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3288668110
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.4081461680
Short name T57
Test name
Test status
Simulation time 100610201 ps
CPU time 1.12 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:24:13 PM PDT 24
Peak memory 196508 kb
Host smart-b7f2cf3c-054e-4199-98d5-1934a4727d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081461680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.4081461680
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3407200139
Short name T529
Test name
Test status
Simulation time 140184476 ps
CPU time 1.05 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 195876 kb
Host smart-805a5cf4-9adc-4d90-97b3-0f3a61c0c93a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407200139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3407200139
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3157440558
Short name T261
Test name
Test status
Simulation time 10145824004 ps
CPU time 139.34 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:26:29 PM PDT 24
Peak memory 198288 kb
Host smart-0bbd6011-d781-448a-932d-73d872e14ce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157440558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3157440558
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3643561436
Short name T69
Test name
Test status
Simulation time 81108176542 ps
CPU time 755.87 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:36:45 PM PDT 24
Peak memory 198160 kb
Host smart-e8ba3060-41b7-43f0-a841-cd1368f9a5f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3643561436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3643561436
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2190624986
Short name T24
Test name
Test status
Simulation time 57486205 ps
CPU time 0.57 seconds
Started Apr 16 12:24:04 PM PDT 24
Finished Apr 16 12:24:07 PM PDT 24
Peak memory 193996 kb
Host smart-de321ad6-a4cd-4a17-abf8-60fe392f075e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190624986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2190624986
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3656607844
Short name T331
Test name
Test status
Simulation time 36700303 ps
CPU time 0.89 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:08 PM PDT 24
Peak memory 196596 kb
Host smart-b39c5260-1692-4456-8016-ca6f9b3009e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656607844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3656607844
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.180970619
Short name T476
Test name
Test status
Simulation time 2014209912 ps
CPU time 24.89 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:31 PM PDT 24
Peak memory 193364 kb
Host smart-18816249-9486-45a5-a5fe-4b662d1ea55a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180970619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.180970619
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.808326499
Short name T281
Test name
Test status
Simulation time 163458598 ps
CPU time 0.84 seconds
Started Apr 16 12:24:03 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 196388 kb
Host smart-02bef70b-5b43-4eff-a2c2-f1ce2f35c312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808326499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.808326499
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2560831499
Short name T251
Test name
Test status
Simulation time 82757656 ps
CPU time 3.26 seconds
Started Apr 16 12:24:00 PM PDT 24
Finished Apr 16 12:24:05 PM PDT 24
Peak memory 198264 kb
Host smart-43b0cc7f-118c-4549-b574-3a6b0ab65c50
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560831499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2560831499
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.580878683
Short name T654
Test name
Test status
Simulation time 95476130 ps
CPU time 1.21 seconds
Started Apr 16 12:24:13 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 195572 kb
Host smart-61857d72-c28a-4034-8064-51d198b18658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580878683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
580878683
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3268283972
Short name T335
Test name
Test status
Simulation time 21001931 ps
CPU time 0.69 seconds
Started Apr 16 12:24:11 PM PDT 24
Finished Apr 16 12:24:14 PM PDT 24
Peak memory 195092 kb
Host smart-d6dfe535-8ce9-454c-8fa9-75b7f778bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268283972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3268283972
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.537013690
Short name T373
Test name
Test status
Simulation time 59781762 ps
CPU time 0.86 seconds
Started Apr 16 12:25:20 PM PDT 24
Finished Apr 16 12:25:25 PM PDT 24
Peak memory 197144 kb
Host smart-ae7907a2-4816-4897-a643-6aa3df7a5c12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537013690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.537013690
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2448927318
Short name T10
Test name
Test status
Simulation time 2040800509 ps
CPU time 4.03 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 198092 kb
Host smart-8df4e5b4-9b86-4ae5-9734-55d7a1ebd205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448927318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2448927318
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1287579787
Short name T128
Test name
Test status
Simulation time 51319333 ps
CPU time 1.34 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:08 PM PDT 24
Peak memory 195480 kb
Host smart-048b8cf1-58de-49a4-b7f5-7f9f2bb627f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287579787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1287579787
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.697500666
Short name T179
Test name
Test status
Simulation time 372817623 ps
CPU time 1.05 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:07 PM PDT 24
Peak memory 193348 kb
Host smart-4abdadff-be3c-410a-8ba8-2ddd2a47205c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697500666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.697500666
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2763966508
Short name T481
Test name
Test status
Simulation time 2545566802 ps
CPU time 17.2 seconds
Started Apr 16 12:25:03 PM PDT 24
Finished Apr 16 12:25:24 PM PDT 24
Peak memory 197684 kb
Host smart-dd453fbd-034b-4dba-8a11-25166ca13ff0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763966508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2763966508
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3228349443
Short name T364
Test name
Test status
Simulation time 35020643 ps
CPU time 0.6 seconds
Started Apr 16 12:24:16 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 193952 kb
Host smart-64774aab-228c-437b-8641-079226171852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228349443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3228349443
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3318976918
Short name T606
Test name
Test status
Simulation time 189639625 ps
CPU time 0.86 seconds
Started Apr 16 12:24:03 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 195504 kb
Host smart-5c183428-8637-4dfc-907e-7e12c722f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318976918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3318976918
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3254686605
Short name T181
Test name
Test status
Simulation time 617031097 ps
CPU time 19.4 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:28 PM PDT 24
Peak memory 197952 kb
Host smart-59b80f40-635d-4402-9ae6-e9e25922f2ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254686605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3254686605
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1501159567
Short name T525
Test name
Test status
Simulation time 128010761 ps
CPU time 1 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:07 PM PDT 24
Peak memory 194464 kb
Host smart-a57f3183-a7c3-482d-8d46-5ef75c6faeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501159567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1501159567
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2345838167
Short name T551
Test name
Test status
Simulation time 110475618 ps
CPU time 1.06 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 196112 kb
Host smart-efc0a3f4-61a7-46f3-b1a5-22e5c784dbf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345838167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2345838167
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3041160598
Short name T664
Test name
Test status
Simulation time 152969373 ps
CPU time 3.06 seconds
Started Apr 16 12:24:19 PM PDT 24
Finished Apr 16 12:24:25 PM PDT 24
Peak memory 198040 kb
Host smart-c0e8051d-5b4e-4e6f-94c1-48bed44b37ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041160598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3041160598
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1417531844
Short name T315
Test name
Test status
Simulation time 340024659 ps
CPU time 1.99 seconds
Started Apr 16 12:24:03 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 197000 kb
Host smart-6528a31e-dd73-44a8-a0e1-33f39ee8e61b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417531844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1417531844
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4036396577
Short name T108
Test name
Test status
Simulation time 27240645 ps
CPU time 1.03 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:10 PM PDT 24
Peak memory 196612 kb
Host smart-6361f0a1-bed7-4386-b928-46f04fc78247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036396577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4036396577
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4279398900
Short name T62
Test name
Test status
Simulation time 14181930 ps
CPU time 0.61 seconds
Started Apr 16 12:24:03 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 194152 kb
Host smart-60acc597-f84f-4967-8973-29677c0e4996
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279398900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4279398900
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2723556264
Short name T400
Test name
Test status
Simulation time 519363993 ps
CPU time 5.81 seconds
Started Apr 16 12:23:59 PM PDT 24
Finished Apr 16 12:24:06 PM PDT 24
Peak memory 198016 kb
Host smart-61bb3433-ea5d-4b5f-b546-2aded13a9b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723556264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2723556264
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1026436187
Short name T148
Test name
Test status
Simulation time 33751637 ps
CPU time 1.07 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:07 PM PDT 24
Peak memory 193948 kb
Host smart-5179cfcc-e708-4fc8-8143-53e5495dd7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026436187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1026436187
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1272237454
Short name T610
Test name
Test status
Simulation time 769984362 ps
CPU time 0.89 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 196024 kb
Host smart-52d902a9-f8b6-443b-977c-869cf6f6fda4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272237454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1272237454
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1044926327
Short name T532
Test name
Test status
Simulation time 19082266979 ps
CPU time 77.18 seconds
Started Apr 16 12:24:12 PM PDT 24
Finished Apr 16 12:25:30 PM PDT 24
Peak memory 198548 kb
Host smart-e71958bd-580b-4ab2-911b-1a92a61fa7ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044926327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1044926327
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2239905005
Short name T217
Test name
Test status
Simulation time 62653182 ps
CPU time 0.58 seconds
Started Apr 16 12:24:11 PM PDT 24
Finished Apr 16 12:24:13 PM PDT 24
Peak memory 194884 kb
Host smart-fe8dceff-404b-413c-b7ef-3144fd6795d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239905005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2239905005
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1593535375
Short name T453
Test name
Test status
Simulation time 88672858 ps
CPU time 0.82 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 196240 kb
Host smart-8d7ab941-ea8f-4397-ac42-df2bd0cdfa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593535375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1593535375
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3017660222
Short name T589
Test name
Test status
Simulation time 122137171 ps
CPU time 6.26 seconds
Started Apr 16 12:25:00 PM PDT 24
Finished Apr 16 12:25:08 PM PDT 24
Peak memory 195628 kb
Host smart-f768f33a-b4a4-4002-85d8-11941e04c206
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017660222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3017660222
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3868948830
Short name T18
Test name
Test status
Simulation time 67152317 ps
CPU time 0.91 seconds
Started Apr 16 12:25:20 PM PDT 24
Finished Apr 16 12:25:25 PM PDT 24
Peak memory 197748 kb
Host smart-fa6cf21e-d31d-41a0-a726-a5fb87586c73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868948830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3868948830
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4184530174
Short name T436
Test name
Test status
Simulation time 68822884 ps
CPU time 1.15 seconds
Started Apr 16 12:25:21 PM PDT 24
Finished Apr 16 12:25:27 PM PDT 24
Peak memory 195648 kb
Host smart-3ff28820-2d23-4ffc-be33-a8b50a658692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184530174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4184530174
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1312716706
Short name T328
Test name
Test status
Simulation time 1038028109 ps
CPU time 2.57 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 196656 kb
Host smart-2fa4758d-7471-4169-913b-6c89a207ea7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312716706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1312716706
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1037747608
Short name T208
Test name
Test status
Simulation time 50920455 ps
CPU time 1.01 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 195656 kb
Host smart-70fc9465-bd77-491f-9d9c-22927621d5a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037747608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1037747608
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1879502357
Short name T326
Test name
Test status
Simulation time 141362471 ps
CPU time 0.94 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:07 PM PDT 24
Peak memory 193092 kb
Host smart-b0f26f66-2496-49f5-9c53-ec8cf57aca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879502357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1879502357
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3653655429
Short name T380
Test name
Test status
Simulation time 112775717 ps
CPU time 1.34 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 197144 kb
Host smart-35619ae7-e0aa-40c0-b248-d5bb8937de66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653655429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3653655429
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.103634754
Short name T258
Test name
Test status
Simulation time 185313433 ps
CPU time 2.31 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:19 PM PDT 24
Peak memory 198064 kb
Host smart-5110981d-33ea-498c-8b82-6d76435bfda6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103634754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.103634754
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.802966767
Short name T136
Test name
Test status
Simulation time 241261725 ps
CPU time 1.15 seconds
Started Apr 16 12:25:27 PM PDT 24
Finished Apr 16 12:25:34 PM PDT 24
Peak memory 194860 kb
Host smart-782ac1b6-8e6b-44b0-b237-b0adc7e42786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802966767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.802966767
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.224038486
Short name T669
Test name
Test status
Simulation time 64621965 ps
CPU time 1.03 seconds
Started Apr 16 12:25:02 PM PDT 24
Finished Apr 16 12:25:07 PM PDT 24
Peak memory 193412 kb
Host smart-812b13c3-7b48-4d5f-be89-916f847b7ea0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224038486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.224038486
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.53458417
Short name T323
Test name
Test status
Simulation time 8393019854 ps
CPU time 117.78 seconds
Started Apr 16 12:23:54 PM PDT 24
Finished Apr 16 12:25:54 PM PDT 24
Peak memory 198160 kb
Host smart-f26bd2de-0414-48b6-88a6-2b613aa867fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53458417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gp
io_stress_all.53458417
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3888107248
Short name T268
Test name
Test status
Simulation time 41643461 ps
CPU time 0.59 seconds
Started Apr 16 12:24:39 PM PDT 24
Finished Apr 16 12:24:42 PM PDT 24
Peak memory 194564 kb
Host smart-aeaeea14-cf3d-495f-8276-40853dac7cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888107248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3888107248
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4257882003
Short name T289
Test name
Test status
Simulation time 54161782 ps
CPU time 0.6 seconds
Started Apr 16 12:24:35 PM PDT 24
Finished Apr 16 12:24:38 PM PDT 24
Peak memory 194660 kb
Host smart-c238adf5-e69b-4973-9bb3-b81ede97bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257882003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4257882003
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3361903258
Short name T393
Test name
Test status
Simulation time 1131994104 ps
CPU time 18.79 seconds
Started Apr 16 12:24:11 PM PDT 24
Finished Apr 16 12:24:32 PM PDT 24
Peak memory 198056 kb
Host smart-709c4aa7-e68f-4d52-adc6-bb4682f0d5f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361903258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3361903258
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2955827412
Short name T443
Test name
Test status
Simulation time 79701338 ps
CPU time 0.9 seconds
Started Apr 16 12:25:00 PM PDT 24
Finished Apr 16 12:25:04 PM PDT 24
Peak memory 196112 kb
Host smart-1b87cba1-ab8a-4c7c-95a6-fd0eb1fbd967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955827412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2955827412
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.596070378
Short name T623
Test name
Test status
Simulation time 68446999 ps
CPU time 0.82 seconds
Started Apr 16 12:24:34 PM PDT 24
Finished Apr 16 12:24:38 PM PDT 24
Peak memory 195636 kb
Host smart-f6e04362-7149-434c-b465-1b045022121f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596070378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.596070378
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3981962843
Short name T203
Test name
Test status
Simulation time 70805541 ps
CPU time 0.95 seconds
Started Apr 16 12:24:52 PM PDT 24
Finished Apr 16 12:24:55 PM PDT 24
Peak memory 197060 kb
Host smart-aaac7c33-2e4e-4b29-a0bd-1e490a1c0785
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981962843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3981962843
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3766541869
Short name T60
Test name
Test status
Simulation time 176195030 ps
CPU time 3.16 seconds
Started Apr 16 12:24:13 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 198068 kb
Host smart-9a64a987-abac-41dc-8a71-38b0344157e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766541869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3766541869
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2044318423
Short name T662
Test name
Test status
Simulation time 101485004 ps
CPU time 1.08 seconds
Started Apr 16 12:24:19 PM PDT 24
Finished Apr 16 12:24:23 PM PDT 24
Peak memory 196872 kb
Host smart-b69f4c13-a4d5-4ffb-b83d-c3be1133f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044318423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2044318423
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1191961156
Short name T596
Test name
Test status
Simulation time 60842481 ps
CPU time 1.08 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:21 PM PDT 24
Peak memory 195956 kb
Host smart-a1b36eb5-34b8-4106-94cd-483be47c22e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191961156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1191961156
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1485615446
Short name T513
Test name
Test status
Simulation time 1216616012 ps
CPU time 4.12 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:24 PM PDT 24
Peak memory 198080 kb
Host smart-249dc3b7-869f-4a9c-a6f3-310861bdf4b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485615446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1485615446
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2671614150
Short name T204
Test name
Test status
Simulation time 126065822 ps
CPU time 1.11 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 195628 kb
Host smart-7b4d5673-cf8b-419d-9af0-4ae3517963a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671614150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2671614150
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.529636195
Short name T361
Test name
Test status
Simulation time 39580016 ps
CPU time 1 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 195508 kb
Host smart-6cba9dd8-7e37-4303-8976-3a7085194e42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529636195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.529636195
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1130076559
Short name T113
Test name
Test status
Simulation time 52044100525 ps
CPU time 177.53 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:27:13 PM PDT 24
Peak memory 198100 kb
Host smart-784cfa3b-04eb-45ce-b49a-dc217ac2c396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130076559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1130076559
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.990555132
Short name T147
Test name
Test status
Simulation time 115452270 ps
CPU time 0.55 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:10 PM PDT 24
Peak memory 192848 kb
Host smart-4e73d027-0972-42fc-9042-4514457b8667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990555132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.990555132
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1741763624
Short name T501
Test name
Test status
Simulation time 61281713 ps
CPU time 0.79 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 195076 kb
Host smart-86a7f187-ecfd-4e0f-b4c2-d925a96aad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741763624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1741763624
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1871191430
Short name T595
Test name
Test status
Simulation time 4997814365 ps
CPU time 26.88 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:43 PM PDT 24
Peak memory 197028 kb
Host smart-b798a22e-f175-4fc1-9c39-6791784ff9b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871191430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1871191430
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3410157079
Short name T243
Test name
Test status
Simulation time 88307869 ps
CPU time 0.63 seconds
Started Apr 16 12:24:33 PM PDT 24
Finished Apr 16 12:24:36 PM PDT 24
Peak memory 195448 kb
Host smart-76718b68-a1f5-409b-ada4-462d8b6448a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410157079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3410157079
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.4211225242
Short name T536
Test name
Test status
Simulation time 262586066 ps
CPU time 0.88 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:24:13 PM PDT 24
Peak memory 196724 kb
Host smart-35b79623-2c2d-4655-979b-3e6e53196853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211225242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.4211225242
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1170006825
Short name T378
Test name
Test status
Simulation time 147859953 ps
CPU time 2.82 seconds
Started Apr 16 12:24:11 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 198136 kb
Host smart-fb93a648-3a5f-4c54-9a86-c8ee352017fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170006825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1170006825
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1637109883
Short name T502
Test name
Test status
Simulation time 134176599 ps
CPU time 2.5 seconds
Started Apr 16 12:24:20 PM PDT 24
Finished Apr 16 12:24:31 PM PDT 24
Peak memory 197084 kb
Host smart-6bed94a8-58a4-41bb-8343-bb1e17b92f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637109883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1637109883
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2982864103
Short name T613
Test name
Test status
Simulation time 64269513 ps
CPU time 1.33 seconds
Started Apr 16 12:24:51 PM PDT 24
Finished Apr 16 12:24:53 PM PDT 24
Peak memory 197008 kb
Host smart-0ec003f6-aed7-4309-a83b-6909fe7e519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982864103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2982864103
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1900954226
Short name T667
Test name
Test status
Simulation time 249338081 ps
CPU time 1.17 seconds
Started Apr 16 12:24:05 PM PDT 24
Finished Apr 16 12:24:09 PM PDT 24
Peak memory 195848 kb
Host smart-9dab3fd3-05d3-4e3c-b002-945ff40c1757
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900954226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1900954226
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1972575151
Short name T332
Test name
Test status
Simulation time 93464051 ps
CPU time 4.12 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:24 PM PDT 24
Peak memory 198088 kb
Host smart-27b8db43-b0f8-41da-9254-acf981d5f567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972575151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1972575151
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.303097713
Short name T626
Test name
Test status
Simulation time 208937962 ps
CPU time 1.02 seconds
Started Apr 16 12:24:43 PM PDT 24
Finished Apr 16 12:24:45 PM PDT 24
Peak memory 195664 kb
Host smart-e0af9e3c-25c8-4e13-b0a2-06fbbcd0ec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303097713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.303097713
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1590383201
Short name T464
Test name
Test status
Simulation time 49279824 ps
CPU time 0.93 seconds
Started Apr 16 12:24:40 PM PDT 24
Finished Apr 16 12:24:43 PM PDT 24
Peak memory 197116 kb
Host smart-43b26100-65b0-4905-aab0-b18f9b2b1ecc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590383201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1590383201
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2672181131
Short name T583
Test name
Test status
Simulation time 12510832969 ps
CPU time 152.98 seconds
Started Apr 16 12:24:37 PM PDT 24
Finished Apr 16 12:27:13 PM PDT 24
Peak memory 198076 kb
Host smart-d10430f4-16fc-4159-a213-b72ab651ff19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672181131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2672181131
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2538661255
Short name T415
Test name
Test status
Simulation time 75344805 ps
CPU time 0.57 seconds
Started Apr 16 12:24:20 PM PDT 24
Finished Apr 16 12:24:25 PM PDT 24
Peak memory 193964 kb
Host smart-0a0c19c0-b729-4e19-9f44-fa72bcfdf0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538661255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2538661255
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3246382196
Short name T14
Test name
Test status
Simulation time 22230097 ps
CPU time 0.75 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 195992 kb
Host smart-787e304e-5ce7-4509-92b2-bf1a957fc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246382196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3246382196
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2550952608
Short name T138
Test name
Test status
Simulation time 535796876 ps
CPU time 5.09 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:21 PM PDT 24
Peak memory 197080 kb
Host smart-2de15cff-0273-4653-876f-11c31ce46575
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550952608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2550952608
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.475645330
Short name T427
Test name
Test status
Simulation time 134529918 ps
CPU time 0.89 seconds
Started Apr 16 12:24:22 PM PDT 24
Finished Apr 16 12:24:27 PM PDT 24
Peak memory 197044 kb
Host smart-16290661-e4e4-4766-afc4-8ec805cc1c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475645330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.475645330
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3546330840
Short name T109
Test name
Test status
Simulation time 78151705 ps
CPU time 1.35 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:19 PM PDT 24
Peak memory 196804 kb
Host smart-fa63e94c-cfe3-4abe-90f5-de55f28d806b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546330840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3546330840
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2872298068
Short name T188
Test name
Test status
Simulation time 66325539 ps
CPU time 2.48 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:22 PM PDT 24
Peak memory 196520 kb
Host smart-6863f7d3-1998-4c42-8dd9-7ceef364730d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872298068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2872298068
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2820693119
Short name T229
Test name
Test status
Simulation time 221936056 ps
CPU time 1.43 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 196600 kb
Host smart-db37063f-4b13-431c-8821-b60b1b5e84a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820693119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2820693119
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.190871987
Short name T279
Test name
Test status
Simulation time 486246775 ps
CPU time 1.26 seconds
Started Apr 16 12:24:13 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 197996 kb
Host smart-8040f67c-a5b1-4903-8624-76518022a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190871987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.190871987
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2481409540
Short name T228
Test name
Test status
Simulation time 54239902 ps
CPU time 0.82 seconds
Started Apr 16 12:24:19 PM PDT 24
Finished Apr 16 12:24:23 PM PDT 24
Peak memory 197392 kb
Host smart-21d8d4e1-4c2c-4abb-881b-dd6777ce7351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481409540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2481409540
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3065814678
Short name T684
Test name
Test status
Simulation time 156014932 ps
CPU time 3.62 seconds
Started Apr 16 12:24:06 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 197988 kb
Host smart-a9063519-01e5-42a1-9fa0-57c7b9f49118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065814678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3065814678
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1717986384
Short name T369
Test name
Test status
Simulation time 65600832 ps
CPU time 1.07 seconds
Started Apr 16 12:24:15 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 195676 kb
Host smart-8b66faf9-177b-41a0-9463-959b42cd15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717986384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1717986384
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2397558475
Short name T561
Test name
Test status
Simulation time 56420587 ps
CPU time 1.18 seconds
Started Apr 16 12:24:08 PM PDT 24
Finished Apr 16 12:24:11 PM PDT 24
Peak memory 195640 kb
Host smart-954b3d5f-31f7-4c84-9464-51c56c4438a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397558475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2397558475
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1135252748
Short name T139
Test name
Test status
Simulation time 4542533828 ps
CPU time 33.41 seconds
Started Apr 16 12:24:20 PM PDT 24
Finished Apr 16 12:24:56 PM PDT 24
Peak memory 198112 kb
Host smart-f60228e1-e518-43e4-a5e1-9005f5de5e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135252748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1135252748
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2039245318
Short name T633
Test name
Test status
Simulation time 14475801 ps
CPU time 0.58 seconds
Started Apr 16 12:26:08 PM PDT 24
Finished Apr 16 12:26:11 PM PDT 24
Peak memory 194048 kb
Host smart-2dce2fe7-53e2-494d-aa47-fa308122b371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039245318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2039245318
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.4099466008
Short name T450
Test name
Test status
Simulation time 60317535 ps
CPU time 0.73 seconds
Started Apr 16 12:24:21 PM PDT 24
Finished Apr 16 12:24:26 PM PDT 24
Peak memory 195264 kb
Host smart-8397478f-881a-42f6-ad7a-957a6494c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099466008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.4099466008
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3260781554
Short name T552
Test name
Test status
Simulation time 344813552 ps
CPU time 7.33 seconds
Started Apr 16 12:24:23 PM PDT 24
Finished Apr 16 12:24:34 PM PDT 24
Peak memory 196828 kb
Host smart-8827b949-1806-43ae-aa05-88dee63a1d8d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260781554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3260781554
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3449163193
Short name T496
Test name
Test status
Simulation time 26311253 ps
CPU time 0.69 seconds
Started Apr 16 12:24:20 PM PDT 24
Finished Apr 16 12:24:24 PM PDT 24
Peak memory 195340 kb
Host smart-e5be7aea-553c-4f62-910f-eadd8d780694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449163193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3449163193
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1830848086
Short name T237
Test name
Test status
Simulation time 86205885 ps
CPU time 1.3 seconds
Started Apr 16 12:24:17 PM PDT 24
Finished Apr 16 12:24:22 PM PDT 24
Peak memory 197980 kb
Host smart-0ac8ac64-8fda-4aab-a5fb-333bdf6b817f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830848086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1830848086
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3627293988
Short name T508
Test name
Test status
Simulation time 134188003 ps
CPU time 2.8 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:18 PM PDT 24
Peak memory 198028 kb
Host smart-60dbf660-215d-4051-9d5c-fc5a65ec278e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627293988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3627293988
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.123213024
Short name T424
Test name
Test status
Simulation time 1409730359 ps
CPU time 3.07 seconds
Started Apr 16 12:24:24 PM PDT 24
Finished Apr 16 12:24:31 PM PDT 24
Peak memory 195924 kb
Host smart-828a2ba4-1879-46e2-a6e2-ac7e535d14bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123213024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
123213024
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4230844986
Short name T619
Test name
Test status
Simulation time 134386217 ps
CPU time 1.27 seconds
Started Apr 16 12:24:13 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 197152 kb
Host smart-e69548b0-f7c2-4fbe-be4d-6da408c7aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230844986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4230844986
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.583258215
Short name T582
Test name
Test status
Simulation time 62906406 ps
CPU time 1.21 seconds
Started Apr 16 12:24:14 PM PDT 24
Finished Apr 16 12:24:17 PM PDT 24
Peak memory 198016 kb
Host smart-69f67d0c-0595-4ff5-8026-bfe06297e364
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583258215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.583258215
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1985466103
Short name T644
Test name
Test status
Simulation time 1105414531 ps
CPU time 6.33 seconds
Started Apr 16 12:24:07 PM PDT 24
Finished Apr 16 12:24:16 PM PDT 24
Peak memory 198160 kb
Host smart-75fd6046-f55a-41c9-8810-a26f62f9d045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985466103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1985466103
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1258237433
Short name T354
Test name
Test status
Simulation time 49555338 ps
CPU time 0.92 seconds
Started Apr 16 12:24:19 PM PDT 24
Finished Apr 16 12:24:23 PM PDT 24
Peak memory 195572 kb
Host smart-cac12c77-e75e-42f6-b43d-863c61d25f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258237433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1258237433
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.423187963
Short name T151
Test name
Test status
Simulation time 359087101 ps
CPU time 1.39 seconds
Started Apr 16 12:24:09 PM PDT 24
Finished Apr 16 12:24:12 PM PDT 24
Peak memory 196768 kb
Host smart-ceebbfba-c190-4711-8ba2-26cc944dc30b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423187963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.423187963
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3946581428
Short name T295
Test name
Test status
Simulation time 18677718777 ps
CPU time 121.13 seconds
Started Apr 16 12:24:10 PM PDT 24
Finished Apr 16 12:26:13 PM PDT 24
Peak memory 198232 kb
Host smart-8aac4ea3-93d1-48bb-adf1-ca85de13cd6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946581428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3946581428
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.219758239
Short name T104
Test name
Test status
Simulation time 33733469 ps
CPU time 0.6 seconds
Started Apr 16 12:22:33 PM PDT 24
Finished Apr 16 12:22:38 PM PDT 24
Peak memory 194580 kb
Host smart-6e9ce35b-8f4d-4ee8-8093-91513e4c415d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219758239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.219758239
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3730026706
Short name T509
Test name
Test status
Simulation time 57363839 ps
CPU time 0.8 seconds
Started Apr 16 12:22:33 PM PDT 24
Finished Apr 16 12:22:38 PM PDT 24
Peak memory 195968 kb
Host smart-97656fb8-07d0-4628-8972-05a5a794dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730026706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3730026706
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3715732281
Short name T472
Test name
Test status
Simulation time 194689286 ps
CPU time 5.1 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:44 PM PDT 24
Peak memory 196712 kb
Host smart-5f49d0c8-fd70-4511-a678-1038fceef980
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715732281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3715732281
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.243935744
Short name T403
Test name
Test status
Simulation time 187428488 ps
CPU time 0.69 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:46 PM PDT 24
Peak memory 194856 kb
Host smart-4c743747-9e3b-44e7-abe7-22b5858d7872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243935744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.243935744
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1493519893
Short name T636
Test name
Test status
Simulation time 26567169 ps
CPU time 0.82 seconds
Started Apr 16 12:22:27 PM PDT 24
Finished Apr 16 12:22:29 PM PDT 24
Peak memory 196600 kb
Host smart-7ffc0202-d30c-4f3d-a71f-32755a8bcb75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493519893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1493519893
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2432710299
Short name T473
Test name
Test status
Simulation time 53245177 ps
CPU time 1.99 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 196036 kb
Host smart-49d11083-85dc-48dc-8881-6f88f03bc0f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432710299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2432710299
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3392626378
Short name T468
Test name
Test status
Simulation time 235700887 ps
CPU time 1.65 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 195704 kb
Host smart-916d1484-69f2-4aa7-9038-cf15b081969a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392626378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3392626378
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1805267666
Short name T385
Test name
Test status
Simulation time 235513574 ps
CPU time 1.16 seconds
Started Apr 16 12:22:26 PM PDT 24
Finished Apr 16 12:22:29 PM PDT 24
Peak memory 195768 kb
Host smart-7c76c56d-cc2b-4439-9814-154e6602331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805267666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1805267666
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3868664618
Short name T646
Test name
Test status
Simulation time 75005577 ps
CPU time 0.88 seconds
Started Apr 16 12:22:21 PM PDT 24
Finished Apr 16 12:22:23 PM PDT 24
Peak memory 196180 kb
Host smart-d09f7807-6d8b-422c-9537-e6a1fd3bac58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868664618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3868664618
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3978235662
Short name T270
Test name
Test status
Simulation time 1134415048 ps
CPU time 3.58 seconds
Started Apr 16 12:22:32 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 197952 kb
Host smart-465fb118-b376-43ee-bef4-31a35c55a975
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978235662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3978235662
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1862471084
Short name T701
Test name
Test status
Simulation time 229966867 ps
CPU time 1.03 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:22:33 PM PDT 24
Peak memory 195488 kb
Host smart-0cf7c8ec-6c29-4cc1-9936-3e75ddeb6869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862471084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1862471084
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2525470820
Short name T588
Test name
Test status
Simulation time 53194175 ps
CPU time 1.4 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:22:32 PM PDT 24
Peak memory 198000 kb
Host smart-fa356026-c320-45b8-a71d-de3727f723ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525470820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2525470820
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.733434886
Short name T576
Test name
Test status
Simulation time 46341223915 ps
CPU time 125.12 seconds
Started Apr 16 12:23:47 PM PDT 24
Finished Apr 16 12:25:55 PM PDT 24
Peak memory 197728 kb
Host smart-75c67727-0a1d-41ff-8637-198becc8f1d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733434886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.733434886
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1262185867
Short name T64
Test name
Test status
Simulation time 531959943485 ps
CPU time 1770.26 seconds
Started Apr 16 12:22:29 PM PDT 24
Finished Apr 16 12:52:02 PM PDT 24
Peak memory 198352 kb
Host smart-a768511f-d99c-443f-811b-5ab2293c7c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1262185867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1262185867
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.520023135
Short name T611
Test name
Test status
Simulation time 36242392 ps
CPU time 0.6 seconds
Started Apr 16 12:22:33 PM PDT 24
Finished Apr 16 12:22:38 PM PDT 24
Peak memory 194584 kb
Host smart-a30c1b70-44b8-4570-a947-c6025321f725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520023135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.520023135
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2185161800
Short name T382
Test name
Test status
Simulation time 126471568 ps
CPU time 0.84 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:50 PM PDT 24
Peak memory 195512 kb
Host smart-65f79c4e-6f2d-403a-b548-4d409bde29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185161800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2185161800
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2950501327
Short name T480
Test name
Test status
Simulation time 5837848355 ps
CPU time 19.82 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 196976 kb
Host smart-faff3fed-c02c-4d7c-94e8-9906085a6f64
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950501327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2950501327
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1468530651
Short name T465
Test name
Test status
Simulation time 127591510 ps
CPU time 0.87 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 197116 kb
Host smart-b5ca0f7d-cb4e-4d16-8194-b6c1e8ede727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468530651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1468530651
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.239024503
Short name T593
Test name
Test status
Simulation time 79002551 ps
CPU time 1.26 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 197164 kb
Host smart-c8893c90-bdb8-41d7-8910-ee68808806d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239024503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.239024503
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1436657622
Short name T388
Test name
Test status
Simulation time 273159675 ps
CPU time 2.03 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:52 PM PDT 24
Peak memory 197548 kb
Host smart-3a951d3c-678a-4118-beca-98eb77e0d95a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436657622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1436657622
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1596332099
Short name T126
Test name
Test status
Simulation time 128114609 ps
CPU time 1.71 seconds
Started Apr 16 12:22:36 PM PDT 24
Finished Apr 16 12:22:42 PM PDT 24
Peak memory 196228 kb
Host smart-09d9f8a8-d31b-482d-b32e-5471c72fa451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596332099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1596332099
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.560434952
Short name T347
Test name
Test status
Simulation time 28328766 ps
CPU time 0.7 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:50 PM PDT 24
Peak memory 193684 kb
Host smart-7d7fd485-eca4-49b9-8b14-ebbafa5c062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560434952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.560434952
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4236479732
Short name T117
Test name
Test status
Simulation time 98501989 ps
CPU time 0.78 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:43 PM PDT 24
Peak memory 196552 kb
Host smart-c1765d59-d791-4759-bada-b1533dc15e57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236479732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4236479732
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1557348092
Short name T170
Test name
Test status
Simulation time 352543078 ps
CPU time 3.74 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:22:36 PM PDT 24
Peak memory 197996 kb
Host smart-8ab58433-c9e2-443d-87f5-4fcc1d19390c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557348092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1557348092
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2095657468
Short name T274
Test name
Test status
Simulation time 72388996 ps
CPU time 1.29 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:40 PM PDT 24
Peak memory 196584 kb
Host smart-e3d6c69f-e03a-48e8-ad1f-f5051bd627d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095657468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2095657468
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4099071539
Short name T269
Test name
Test status
Simulation time 52999972 ps
CPU time 1.09 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:22:33 PM PDT 24
Peak memory 195608 kb
Host smart-f8abc9d9-47db-4f78-b962-184092ca51ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099071539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4099071539
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3163094045
Short name T442
Test name
Test status
Simulation time 2747273637 ps
CPU time 63.79 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:23:45 PM PDT 24
Peak memory 198092 kb
Host smart-7a1895e0-3191-4f0a-a17c-2b64eec1b0c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163094045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3163094045
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.162650576
Short name T65
Test name
Test status
Simulation time 79769197553 ps
CPU time 1405.3 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:46:03 PM PDT 24
Peak memory 198100 kb
Host smart-7e1e92af-3e10-43ef-a420-2f6f097221ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=162650576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.162650576
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1242527674
Short name T565
Test name
Test status
Simulation time 11453992 ps
CPU time 0.55 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 193960 kb
Host smart-acee03a5-c091-4e64-9ab0-1705b6922bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242527674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1242527674
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4151849223
Short name T640
Test name
Test status
Simulation time 23654988 ps
CPU time 0.75 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 195288 kb
Host smart-808738bc-527a-4a14-9990-e98c4106e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151849223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4151849223
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1995589570
Short name T318
Test name
Test status
Simulation time 161842264 ps
CPU time 7.45 seconds
Started Apr 16 12:22:30 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 198088 kb
Host smart-e15192a2-01e4-4b68-9e9f-0f9ec4f1c6dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995589570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1995589570
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3082740279
Short name T398
Test name
Test status
Simulation time 63226849 ps
CPU time 0.82 seconds
Started Apr 16 12:23:38 PM PDT 24
Finished Apr 16 12:23:42 PM PDT 24
Peak memory 195964 kb
Host smart-f995d1dc-801c-4636-afd8-0814a3a8545a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082740279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3082740279
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2187443649
Short name T266
Test name
Test status
Simulation time 283012144 ps
CPU time 1.26 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:40 PM PDT 24
Peak memory 196756 kb
Host smart-03f397c0-d526-478d-a8df-6d03644464b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187443649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2187443649
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3864685056
Short name T341
Test name
Test status
Simulation time 35003849 ps
CPU time 1.38 seconds
Started Apr 16 12:22:31 PM PDT 24
Finished Apr 16 12:22:35 PM PDT 24
Peak memory 197828 kb
Host smart-0752485b-e7d6-471d-9cf7-f770949106d1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864685056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3864685056
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1743260897
Short name T125
Test name
Test status
Simulation time 129591933 ps
CPU time 2.83 seconds
Started Apr 16 12:22:32 PM PDT 24
Finished Apr 16 12:22:37 PM PDT 24
Peak memory 198148 kb
Host smart-11588991-8262-46bc-b9fc-e70ee4d21b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743260897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1743260897
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2124509292
Short name T533
Test name
Test status
Simulation time 45741801 ps
CPU time 1.02 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 195608 kb
Host smart-3827f003-2250-4a4b-b70d-39699ac93176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124509292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2124509292
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2144712244
Short name T301
Test name
Test status
Simulation time 124313906 ps
CPU time 1.31 seconds
Started Apr 16 12:23:46 PM PDT 24
Finished Apr 16 12:23:51 PM PDT 24
Peak memory 196280 kb
Host smart-f5dd5fbd-183b-450a-941e-7150506d6f4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144712244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2144712244
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3602129620
Short name T541
Test name
Test status
Simulation time 338824319 ps
CPU time 5.26 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 198136 kb
Host smart-d09d4662-2301-4ad6-a2f7-accf7e8533a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602129620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3602129620
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.6729393
Short name T521
Test name
Test status
Simulation time 1236073040 ps
CPU time 1.21 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:43 PM PDT 24
Peak memory 195908 kb
Host smart-8483e2a7-7d1a-46c0-9cd4-9deaf8ee60b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6729393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.6729393
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.352350079
Short name T259
Test name
Test status
Simulation time 182285298 ps
CPU time 1.39 seconds
Started Apr 16 12:22:32 PM PDT 24
Finished Apr 16 12:22:36 PM PDT 24
Peak memory 196948 kb
Host smart-cc2168ac-7e74-4341-ac6b-ebd172c8373a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352350079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.352350079
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.575888765
Short name T154
Test name
Test status
Simulation time 48200218778 ps
CPU time 184.02 seconds
Started Apr 16 12:23:06 PM PDT 24
Finished Apr 16 12:26:12 PM PDT 24
Peak memory 198176 kb
Host smart-3655c3de-2fba-4673-87db-33e980340962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575888765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.575888765
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.716593169
Short name T248
Test name
Test status
Simulation time 14602137 ps
CPU time 0.56 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:45 PM PDT 24
Peak memory 192744 kb
Host smart-9443f79b-2518-405a-93e8-6ebd0c3b3064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716593169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.716593169
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.295445726
Short name T652
Test name
Test status
Simulation time 29069063 ps
CPU time 0.74 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:42 PM PDT 24
Peak memory 195248 kb
Host smart-ef6f2df9-9467-49b4-8e6f-47b28f572242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295445726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.295445726
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1393351777
Short name T247
Test name
Test status
Simulation time 7586058297 ps
CPU time 22.01 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:23:13 PM PDT 24
Peak memory 195984 kb
Host smart-6fde17c5-cad6-4542-8339-862599f69449
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393351777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1393351777
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1327827549
Short name T44
Test name
Test status
Simulation time 68042680 ps
CPU time 0.7 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:43 PM PDT 24
Peak memory 194772 kb
Host smart-edffbfa3-6c16-4e01-b1cf-03f74c270c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327827549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1327827549
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1055949361
Short name T149
Test name
Test status
Simulation time 43185378 ps
CPU time 0.9 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:43 PM PDT 24
Peak memory 196600 kb
Host smart-ac7dfced-93aa-4628-84d8-24d2498efbf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055949361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1055949361
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.631469031
Short name T439
Test name
Test status
Simulation time 152392960 ps
CPU time 2.88 seconds
Started Apr 16 12:22:35 PM PDT 24
Finished Apr 16 12:22:43 PM PDT 24
Peak memory 198252 kb
Host smart-0d66020f-be4f-4df3-b009-d417796216e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631469031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.631469031
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2497113628
Short name T253
Test name
Test status
Simulation time 556126686 ps
CPU time 2.99 seconds
Started Apr 16 12:22:36 PM PDT 24
Finished Apr 16 12:22:44 PM PDT 24
Peak memory 197060 kb
Host smart-6f2ddb2a-273e-4d84-bca1-583d454c5d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497113628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2497113628
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2667420033
Short name T142
Test name
Test status
Simulation time 133958902 ps
CPU time 0.91 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:39 PM PDT 24
Peak memory 195900 kb
Host smart-f9a9b519-2d69-4b64-aa16-87a3b86f29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667420033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2667420033
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1460432021
Short name T624
Test name
Test status
Simulation time 50493984 ps
CPU time 0.88 seconds
Started Apr 16 12:22:34 PM PDT 24
Finished Apr 16 12:22:38 PM PDT 24
Peak memory 196476 kb
Host smart-6e3b5f02-4118-4a7c-81cc-199d66c08300
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460432021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1460432021
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2587747880
Short name T194
Test name
Test status
Simulation time 48269826 ps
CPU time 2.09 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:47 PM PDT 24
Peak memory 197980 kb
Host smart-d63ba179-e5da-4eef-a9bb-1745bf101f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587747880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2587747880
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.21323240
Short name T173
Test name
Test status
Simulation time 184831454 ps
CPU time 0.98 seconds
Started Apr 16 12:22:37 PM PDT 24
Finished Apr 16 12:22:44 PM PDT 24
Peak memory 195588 kb
Host smart-81ae7ed6-2c94-45c5-a6b1-b595640f0682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21323240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.21323240
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.225542013
Short name T454
Test name
Test status
Simulation time 350214753 ps
CPU time 1.23 seconds
Started Apr 16 12:23:05 PM PDT 24
Finished Apr 16 12:23:08 PM PDT 24
Peak memory 195700 kb
Host smart-418f0f43-703e-43ae-98f0-3974e4627f7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225542013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.225542013
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.296189153
Short name T244
Test name
Test status
Simulation time 8493012326 ps
CPU time 90.85 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:24:21 PM PDT 24
Peak memory 198268 kb
Host smart-0dc58bf5-093f-4c61-8dd8-018bd2c35166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296189153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.296189153
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2837464924
Short name T122
Test name
Test status
Simulation time 12982853 ps
CPU time 0.56 seconds
Started Apr 16 12:22:55 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 193868 kb
Host smart-c4080d70-ce5e-4fff-af7f-33702ff2d4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837464924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2837464924
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1186073667
Short name T207
Test name
Test status
Simulation time 145588426 ps
CPU time 0.87 seconds
Started Apr 16 12:23:52 PM PDT 24
Finished Apr 16 12:23:56 PM PDT 24
Peak memory 196328 kb
Host smart-aa95cd11-fc37-4ff7-9322-bef475898eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186073667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1186073667
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2717885148
Short name T359
Test name
Test status
Simulation time 1065910097 ps
CPU time 10.91 seconds
Started Apr 16 12:22:45 PM PDT 24
Finished Apr 16 12:23:02 PM PDT 24
Peak memory 198092 kb
Host smart-89eccd3a-540c-4344-ab17-ffc56e1d0d58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717885148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2717885148
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1108226748
Short name T706
Test name
Test status
Simulation time 52880366 ps
CPU time 0.77 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 195864 kb
Host smart-875436da-bb32-41ca-ba39-dff6517394ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108226748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1108226748
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.291869509
Short name T300
Test name
Test status
Simulation time 106827904 ps
CPU time 0.84 seconds
Started Apr 16 12:22:40 PM PDT 24
Finished Apr 16 12:22:46 PM PDT 24
Peak memory 195904 kb
Host smart-5740ffe2-3989-456b-86c5-84105572d612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291869509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.291869509
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4171273500
Short name T390
Test name
Test status
Simulation time 131913917 ps
CPU time 2.64 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:52 PM PDT 24
Peak memory 198068 kb
Host smart-a32f2187-ff35-4cc3-bf19-c8f5378ceea2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171273500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4171273500
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2530148296
Short name T635
Test name
Test status
Simulation time 172295901 ps
CPU time 1.37 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:51 PM PDT 24
Peak memory 196852 kb
Host smart-170a3a40-b8f5-4b7c-b08d-a11b01b9ac36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530148296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2530148296
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.149993980
Short name T375
Test name
Test status
Simulation time 117883456 ps
CPU time 1.11 seconds
Started Apr 16 12:22:39 PM PDT 24
Finished Apr 16 12:22:46 PM PDT 24
Peak memory 195848 kb
Host smart-934c4c06-1a8f-433d-bc5f-a209b1ee5162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149993980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.149993980
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.172382012
Short name T101
Test name
Test status
Simulation time 17752049 ps
CPU time 0.68 seconds
Started Apr 16 12:22:38 PM PDT 24
Finished Apr 16 12:22:45 PM PDT 24
Peak memory 195476 kb
Host smart-bc41c5c8-3f76-455b-8de1-b280aa17268d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172382012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.172382012
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.679674171
Short name T540
Test name
Test status
Simulation time 236253435 ps
CPU time 5.24 seconds
Started Apr 16 12:22:51 PM PDT 24
Finished Apr 16 12:23:01 PM PDT 24
Peak memory 198120 kb
Host smart-f4a35f97-2947-450d-b0d2-5f24fa1203c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679674171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.679674171
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3485152702
Short name T545
Test name
Test status
Simulation time 110761605 ps
CPU time 0.93 seconds
Started Apr 16 12:23:33 PM PDT 24
Finished Apr 16 12:23:37 PM PDT 24
Peak memory 195808 kb
Host smart-89b485b1-badd-4d25-9227-23960bfda34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485152702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3485152702
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2486182814
Short name T338
Test name
Test status
Simulation time 136073798 ps
CPU time 1.18 seconds
Started Apr 16 12:23:16 PM PDT 24
Finished Apr 16 12:23:18 PM PDT 24
Peak memory 195884 kb
Host smart-4247870c-e68e-4cd9-80fd-61c3eb88b726
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486182814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2486182814
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2518775843
Short name T657
Test name
Test status
Simulation time 27174148091 ps
CPU time 98.7 seconds
Started Apr 16 12:23:02 PM PDT 24
Finished Apr 16 12:24:43 PM PDT 24
Peak memory 198152 kb
Host smart-524d2c4e-77a9-4654-a2e5-5cbdad7002ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518775843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2518775843
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.4199760109
Short name T494
Test name
Test status
Simulation time 75202436383 ps
CPU time 530 seconds
Started Apr 16 12:22:49 PM PDT 24
Finished Apr 16 12:31:44 PM PDT 24
Peak memory 198192 kb
Host smart-47712e3c-83ee-47cd-9b11-09f813ea5f4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4199760109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.4199760109
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2371771139
Short name T863
Test name
Test status
Simulation time 126902337 ps
CPU time 0.94 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 194132 kb
Host smart-0d54f5ff-683c-40af-a60b-1824373cc88b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2371771139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2371771139
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.506977554
Short name T931
Test name
Test status
Simulation time 216964929 ps
CPU time 1.06 seconds
Started Apr 16 12:21:41 PM PDT 24
Finished Apr 16 12:21:44 PM PDT 24
Peak memory 189668 kb
Host smart-32bf3b37-3c79-4e15-a840-7b1071340b7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506977554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.506977554
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4282196929
Short name T921
Test name
Test status
Simulation time 534021242 ps
CPU time 1.06 seconds
Started Apr 16 12:18:38 PM PDT 24
Finished Apr 16 12:18:40 PM PDT 24
Peak memory 196032 kb
Host smart-df3c9b00-ffe7-4331-b8b8-be3298bc22b1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4282196929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4282196929
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2977361669
Short name T865
Test name
Test status
Simulation time 26784313 ps
CPU time 0.98 seconds
Started Apr 16 12:20:47 PM PDT 24
Finished Apr 16 12:20:49 PM PDT 24
Peak memory 188872 kb
Host smart-3c4e78f4-fbfd-4212-821e-90a2a391af46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977361669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2977361669
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.955504652
Short name T929
Test name
Test status
Simulation time 608893309 ps
CPU time 1.2 seconds
Started Apr 16 12:18:46 PM PDT 24
Finished Apr 16 12:18:48 PM PDT 24
Peak memory 191332 kb
Host smart-24c61925-a611-4952-8446-4f9d111d19a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=955504652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.955504652
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1782821144
Short name T897
Test name
Test status
Simulation time 47087582 ps
CPU time 1.07 seconds
Started Apr 16 12:19:41 PM PDT 24
Finished Apr 16 12:19:43 PM PDT 24
Peak memory 191372 kb
Host smart-0f166e92-ac27-4490-86b3-91c58aff1739
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782821144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1782821144
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2211415728
Short name T857
Test name
Test status
Simulation time 55029901 ps
CPU time 1.11 seconds
Started Apr 16 12:21:16 PM PDT 24
Finished Apr 16 12:21:18 PM PDT 24
Peak memory 195236 kb
Host smart-fda96b2b-832b-42f5-a15e-4a81a85c7edb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2211415728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2211415728
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4097644928
Short name T878
Test name
Test status
Simulation time 165693815 ps
CPU time 1.09 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:01 PM PDT 24
Peak memory 196992 kb
Host smart-aab918c0-9737-4c9b-8251-ff82d539efd9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097644928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4097644928
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1395979549
Short name T928
Test name
Test status
Simulation time 677127613 ps
CPU time 1.04 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 191216 kb
Host smart-330ed561-222f-46dd-91c4-6fe5beb71cf6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1395979549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1395979549
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3160999321
Short name T923
Test name
Test status
Simulation time 41523755 ps
CPU time 0.96 seconds
Started Apr 16 12:21:04 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 191248 kb
Host smart-f7299b2e-9d61-4240-9fda-063fc3362d1b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160999321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3160999321
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1610780028
Short name T856
Test name
Test status
Simulation time 121703408 ps
CPU time 1.18 seconds
Started Apr 16 12:19:20 PM PDT 24
Finished Apr 16 12:19:22 PM PDT 24
Peak memory 191412 kb
Host smart-b8e45413-7012-4213-9802-1c6355900939
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1610780028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1610780028
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162097780
Short name T933
Test name
Test status
Simulation time 125924155 ps
CPU time 0.72 seconds
Started Apr 16 12:23:24 PM PDT 24
Finished Apr 16 12:23:25 PM PDT 24
Peak memory 191096 kb
Host smart-d534577c-1393-442c-8ebb-f44f052bc5f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162097780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3162097780
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.968171743
Short name T896
Test name
Test status
Simulation time 61726975 ps
CPU time 0.98 seconds
Started Apr 16 12:21:11 PM PDT 24
Finished Apr 16 12:21:13 PM PDT 24
Peak memory 190296 kb
Host smart-e38fa11e-5c2f-4baa-9d6b-f9dc7a597dc7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=968171743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.968171743
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2354468692
Short name T932
Test name
Test status
Simulation time 88955321 ps
CPU time 1.54 seconds
Started Apr 16 12:19:14 PM PDT 24
Finished Apr 16 12:19:16 PM PDT 24
Peak memory 191772 kb
Host smart-f893ed5b-aad7-458d-83ac-8030127754f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354468692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2354468692
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1980578972
Short name T922
Test name
Test status
Simulation time 216319139 ps
CPU time 1.37 seconds
Started Apr 16 12:18:38 PM PDT 24
Finished Apr 16 12:18:41 PM PDT 24
Peak memory 196076 kb
Host smart-82d9db4e-dddb-45a7-a8c4-2172c51fdb1d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1980578972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1980578972
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2849733279
Short name T920
Test name
Test status
Simulation time 187085735 ps
CPU time 1.15 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 191092 kb
Host smart-5573331e-a76d-460e-b3b9-fd2db01e8023
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849733279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2849733279
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1407114717
Short name T859
Test name
Test status
Simulation time 45103217 ps
CPU time 1.15 seconds
Started Apr 16 12:19:20 PM PDT 24
Finished Apr 16 12:19:21 PM PDT 24
Peak memory 191380 kb
Host smart-f3cfb7d1-f9cd-4e0e-bd7a-2fffa5760967
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1407114717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1407114717
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3839334956
Short name T869
Test name
Test status
Simulation time 919486699 ps
CPU time 1.26 seconds
Started Apr 16 12:21:47 PM PDT 24
Finished Apr 16 12:21:51 PM PDT 24
Peak memory 191308 kb
Host smart-1aba054f-1e4c-40cb-8826-878d33e37eb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839334956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3839334956
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1175240361
Short name T888
Test name
Test status
Simulation time 32284008 ps
CPU time 0.9 seconds
Started Apr 16 12:19:40 PM PDT 24
Finished Apr 16 12:19:42 PM PDT 24
Peak memory 191320 kb
Host smart-3de2ab36-9a8d-45cc-ad6e-bc4dc648e0ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1175240361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1175240361
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2938210488
Short name T891
Test name
Test status
Simulation time 165480646 ps
CPU time 1.05 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:05 PM PDT 24
Peak memory 189780 kb
Host smart-c4e482df-b52c-4742-8159-45ea22cb8758
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938210488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2938210488
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.750733710
Short name T909
Test name
Test status
Simulation time 50357920 ps
CPU time 0.9 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195744 kb
Host smart-8b3a59e6-ba07-4c99-93b1-243ea30813c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=750733710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.750733710
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2548111047
Short name T926
Test name
Test status
Simulation time 136792798 ps
CPU time 1.24 seconds
Started Apr 16 12:21:48 PM PDT 24
Finished Apr 16 12:21:52 PM PDT 24
Peak memory 191380 kb
Host smart-2bc003a3-0bb5-4e78-b738-8fbd3b2ebb3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548111047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2548111047
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3036980024
Short name T936
Test name
Test status
Simulation time 49774380 ps
CPU time 0.84 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 189140 kb
Host smart-eae36d55-baf8-4e2c-9673-f76075611fe9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3036980024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3036980024
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3104824389
Short name T910
Test name
Test status
Simulation time 198736971 ps
CPU time 0.99 seconds
Started Apr 16 12:21:13 PM PDT 24
Finished Apr 16 12:21:16 PM PDT 24
Peak memory 191348 kb
Host smart-e2bd9f01-3a5d-4b92-9aca-5bc5db6d5d10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104824389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3104824389
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2210305074
Short name T893
Test name
Test status
Simulation time 83370085 ps
CPU time 1.5 seconds
Started Apr 16 12:19:20 PM PDT 24
Finished Apr 16 12:19:22 PM PDT 24
Peak memory 191376 kb
Host smart-43dfa011-fc9f-44a1-b446-d5480e1d4035
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2210305074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2210305074
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4138907681
Short name T904
Test name
Test status
Simulation time 37302807 ps
CPU time 0.89 seconds
Started Apr 16 12:19:17 PM PDT 24
Finished Apr 16 12:19:18 PM PDT 24
Peak memory 195988 kb
Host smart-7305e410-d97c-4f1b-a41d-552b8ae99bd2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138907681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4138907681
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.986144721
Short name T894
Test name
Test status
Simulation time 893891470 ps
CPU time 1 seconds
Started Apr 16 12:19:30 PM PDT 24
Finished Apr 16 12:19:32 PM PDT 24
Peak memory 191488 kb
Host smart-daf54464-ebd0-4602-99aa-6a6fad1344d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=986144721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.986144721
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4237028709
Short name T908
Test name
Test status
Simulation time 153169169 ps
CPU time 1.17 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 190896 kb
Host smart-3ff4b50d-c0ec-49c3-9b0e-56fb0e5ffd78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237028709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4237028709
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.4075902316
Short name T880
Test name
Test status
Simulation time 235032893 ps
CPU time 1.05 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 196024 kb
Host smart-33080261-e869-42fc-b1e2-291c34f58a4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4075902316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.4075902316
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3596923450
Short name T853
Test name
Test status
Simulation time 275201362 ps
CPU time 1.22 seconds
Started Apr 16 12:21:03 PM PDT 24
Finished Apr 16 12:21:05 PM PDT 24
Peak memory 190448 kb
Host smart-52c29557-5b5b-4de6-844a-de0f55372a09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596923450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3596923450
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4064501522
Short name T877
Test name
Test status
Simulation time 285855695 ps
CPU time 1.33 seconds
Started Apr 16 12:21:31 PM PDT 24
Finished Apr 16 12:21:34 PM PDT 24
Peak memory 191360 kb
Host smart-a8589f07-b2dc-4ff0-bff6-61b29b959a80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4064501522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4064501522
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3743581312
Short name T913
Test name
Test status
Simulation time 91565485 ps
CPU time 0.8 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195532 kb
Host smart-48f87fa8-b86c-4afb-99dd-726fcda3e599
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743581312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3743581312
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3654772786
Short name T917
Test name
Test status
Simulation time 169687486 ps
CPU time 1.25 seconds
Started Apr 16 12:20:56 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 189820 kb
Host smart-ba1895bd-5ed9-437c-be8d-8ae98a89f863
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3654772786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3654772786
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.692941781
Short name T860
Test name
Test status
Simulation time 364024295 ps
CPU time 1.03 seconds
Started Apr 16 12:21:04 PM PDT 24
Finished Apr 16 12:21:06 PM PDT 24
Peak memory 191200 kb
Host smart-bf60a150-ca2a-4cd9-b239-a466d6b9029a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692941781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.692941781
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2625103294
Short name T918
Test name
Test status
Simulation time 559321093 ps
CPU time 1.08 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 190984 kb
Host smart-dc2531cf-d106-4392-821b-313c3f65e19e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2625103294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2625103294
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1104455697
Short name T841
Test name
Test status
Simulation time 333077007 ps
CPU time 1.27 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 191248 kb
Host smart-f9887899-08f1-4cb6-ac9f-6293f57c5091
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104455697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1104455697
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3513762216
Short name T868
Test name
Test status
Simulation time 114057651 ps
CPU time 1.03 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:05 PM PDT 24
Peak memory 189472 kb
Host smart-1b6f14be-b153-46d3-8763-1f86b192c36d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3513762216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3513762216
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4227312260
Short name T930
Test name
Test status
Simulation time 129324802 ps
CPU time 0.93 seconds
Started Apr 16 12:17:49 PM PDT 24
Finished Apr 16 12:17:50 PM PDT 24
Peak memory 191372 kb
Host smart-3737e46c-3292-47b5-ac31-2eec28e9797f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227312260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4227312260
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3760021739
Short name T898
Test name
Test status
Simulation time 167924110 ps
CPU time 1.37 seconds
Started Apr 16 12:20:58 PM PDT 24
Finished Apr 16 12:21:01 PM PDT 24
Peak memory 191108 kb
Host smart-efd63d4a-208b-4ef6-8459-e70f1e5291e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3760021739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3760021739
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3232873702
Short name T839
Test name
Test status
Simulation time 89905836 ps
CPU time 0.79 seconds
Started Apr 16 12:20:52 PM PDT 24
Finished Apr 16 12:20:54 PM PDT 24
Peak memory 191156 kb
Host smart-6da7a550-6a37-4c5d-bcb7-825a09a30ebd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232873702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3232873702
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3320354458
Short name T938
Test name
Test status
Simulation time 218762645 ps
CPU time 0.9 seconds
Started Apr 16 12:21:34 PM PDT 24
Finished Apr 16 12:21:36 PM PDT 24
Peak memory 197824 kb
Host smart-192bfd75-da64-435e-85cd-828e31092ed1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3320354458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3320354458
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3681170528
Short name T861
Test name
Test status
Simulation time 332007694 ps
CPU time 1.22 seconds
Started Apr 16 12:21:57 PM PDT 24
Finished Apr 16 12:22:00 PM PDT 24
Peak memory 191428 kb
Host smart-ed217340-9afe-4220-bca5-8cae142c9967
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681170528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3681170528
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1249948393
Short name T850
Test name
Test status
Simulation time 88160934 ps
CPU time 1.2 seconds
Started Apr 16 12:20:48 PM PDT 24
Finished Apr 16 12:20:50 PM PDT 24
Peak memory 197380 kb
Host smart-baac9ec2-b762-4395-8998-acaa64febf75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1249948393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1249948393
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.121581521
Short name T899
Test name
Test status
Simulation time 72140543 ps
CPU time 1.14 seconds
Started Apr 16 12:21:52 PM PDT 24
Finished Apr 16 12:21:56 PM PDT 24
Peak memory 191352 kb
Host smart-f4bb275c-46bf-4f75-9c99-fffe9805884d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121581521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.121581521
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3453970451
Short name T864
Test name
Test status
Simulation time 65145340 ps
CPU time 1.24 seconds
Started Apr 16 12:20:56 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 189312 kb
Host smart-4e3bfc91-bccc-4d5c-b590-5a310c6ee0f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3453970451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3453970451
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865735875
Short name T916
Test name
Test status
Simulation time 690235410 ps
CPU time 1.08 seconds
Started Apr 16 12:21:52 PM PDT 24
Finished Apr 16 12:21:56 PM PDT 24
Peak memory 191360 kb
Host smart-7831c9dc-7d4f-4ebe-801d-309ad02b8717
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865735875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3865735875
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1969568845
Short name T875
Test name
Test status
Simulation time 130736415 ps
CPU time 1.04 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 191056 kb
Host smart-eebacd77-f016-4fea-9229-0bad99489cbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1969568845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1969568845
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545944327
Short name T924
Test name
Test status
Simulation time 183904129 ps
CPU time 1.38 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:10 PM PDT 24
Peak memory 196868 kb
Host smart-19da0aa1-80d3-49bd-8d7e-a26256728d9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545944327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3545944327
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1962578706
Short name T885
Test name
Test status
Simulation time 78896893 ps
CPU time 0.67 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:48 PM PDT 24
Peak memory 191240 kb
Host smart-e6305745-2741-418d-8b82-842d43c7c67b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1962578706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1962578706
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1552680179
Short name T876
Test name
Test status
Simulation time 29186409 ps
CPU time 0.93 seconds
Started Apr 16 12:21:34 PM PDT 24
Finished Apr 16 12:21:36 PM PDT 24
Peak memory 191444 kb
Host smart-3c84bc10-7f51-497c-b6b0-16d795794b55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552680179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1552680179
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1386967004
Short name T927
Test name
Test status
Simulation time 196892012 ps
CPU time 1.09 seconds
Started Apr 16 12:19:18 PM PDT 24
Finished Apr 16 12:19:20 PM PDT 24
Peak memory 197412 kb
Host smart-a74d0458-0b7b-403f-b5a4-7a5a7c05be34
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1386967004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1386967004
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.142434210
Short name T849
Test name
Test status
Simulation time 43011759 ps
CPU time 0.94 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 190976 kb
Host smart-321f321c-3644-4a8c-a5bb-8e4e825d3fce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142434210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.142434210
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.506085837
Short name T934
Test name
Test status
Simulation time 77857718 ps
CPU time 1.17 seconds
Started Apr 16 12:21:57 PM PDT 24
Finished Apr 16 12:22:00 PM PDT 24
Peak memory 191436 kb
Host smart-ede5e9ac-07ec-4c87-a36a-796a61cd2fd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=506085837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.506085837
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.342025631
Short name T874
Test name
Test status
Simulation time 98255071 ps
CPU time 1.36 seconds
Started Apr 16 12:22:41 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 190236 kb
Host smart-12438fe1-3f86-468d-8297-dc17bcc3646f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342025631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.342025631
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1144592295
Short name T862
Test name
Test status
Simulation time 262147440 ps
CPU time 0.82 seconds
Started Apr 16 12:18:11 PM PDT 24
Finished Apr 16 12:18:12 PM PDT 24
Peak memory 195784 kb
Host smart-7aa46a2c-e579-48ce-8a14-29ab691b11b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1144592295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1144592295
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1734376607
Short name T882
Test name
Test status
Simulation time 278200380 ps
CPU time 1.4 seconds
Started Apr 16 12:18:11 PM PDT 24
Finished Apr 16 12:18:14 PM PDT 24
Peak memory 191268 kb
Host smart-f1f8c6ee-d002-41ad-a573-af3797e65d25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734376607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1734376607
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2429855041
Short name T935
Test name
Test status
Simulation time 321615713 ps
CPU time 1.37 seconds
Started Apr 16 12:22:53 PM PDT 24
Finished Apr 16 12:22:59 PM PDT 24
Peak memory 191348 kb
Host smart-8e923266-4e84-4ecc-8152-ad547c1b665b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2429855041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2429855041
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.448936838
Short name T902
Test name
Test status
Simulation time 80931154 ps
CPU time 1.31 seconds
Started Apr 16 12:17:56 PM PDT 24
Finished Apr 16 12:17:58 PM PDT 24
Peak memory 191372 kb
Host smart-c89778ab-f465-4639-aeab-c8f2d061e5f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448936838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.448936838
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.41492524
Short name T886
Test name
Test status
Simulation time 101269047 ps
CPU time 0.97 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195428 kb
Host smart-ac21ab75-7d0d-4343-a069-647a04347894
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=41492524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.41492524
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2894081747
Short name T848
Test name
Test status
Simulation time 1322380513 ps
CPU time 1.21 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 195988 kb
Host smart-00274ffa-cfea-4b1d-94f4-e4bc7d91512d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894081747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2894081747
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2617528112
Short name T884
Test name
Test status
Simulation time 42229284 ps
CPU time 1.15 seconds
Started Apr 16 12:17:59 PM PDT 24
Finished Apr 16 12:18:00 PM PDT 24
Peak memory 196352 kb
Host smart-3e961b34-b19f-4c24-b747-f8ef41e11544
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2617528112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2617528112
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1619306710
Short name T903
Test name
Test status
Simulation time 285478104 ps
CPU time 1.5 seconds
Started Apr 16 12:18:37 PM PDT 24
Finished Apr 16 12:18:40 PM PDT 24
Peak memory 197668 kb
Host smart-2453a69c-1b83-4825-bb77-4dd1a63332bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619306710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1619306710
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3110354293
Short name T843
Test name
Test status
Simulation time 55779295 ps
CPU time 1.14 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:21:00 PM PDT 24
Peak memory 189420 kb
Host smart-e20ad999-4de7-4153-82a5-6afe6aa27a7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3110354293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3110354293
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1151806994
Short name T915
Test name
Test status
Simulation time 64536812 ps
CPU time 1.02 seconds
Started Apr 16 12:18:38 PM PDT 24
Finished Apr 16 12:18:41 PM PDT 24
Peak memory 197396 kb
Host smart-706e4856-8b84-472d-abdc-752cc87aab85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151806994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1151806994
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3157786344
Short name T905
Test name
Test status
Simulation time 96651925 ps
CPU time 0.87 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 195996 kb
Host smart-2c972d91-3e66-4a17-b8fd-8439b03a8b2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3157786344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3157786344
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.766999673
Short name T842
Test name
Test status
Simulation time 151444296 ps
CPU time 1.25 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:08 PM PDT 24
Peak memory 196968 kb
Host smart-67bbe65f-2a47-43a1-9050-aa348a5ff6c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766999673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.766999673
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3070920332
Short name T925
Test name
Test status
Simulation time 36169345 ps
CPU time 1.06 seconds
Started Apr 16 12:22:42 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 190948 kb
Host smart-62778dda-a745-460c-a07d-882159101357
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3070920332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3070920332
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2444464352
Short name T854
Test name
Test status
Simulation time 81696370 ps
CPU time 1.49 seconds
Started Apr 16 12:18:17 PM PDT 24
Finished Apr 16 12:18:19 PM PDT 24
Peak memory 197696 kb
Host smart-87fc39ae-7072-4733-9be0-e15160746535
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444464352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2444464352
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4060456323
Short name T879
Test name
Test status
Simulation time 76817311 ps
CPU time 0.82 seconds
Started Apr 16 12:18:53 PM PDT 24
Finished Apr 16 12:18:55 PM PDT 24
Peak memory 191312 kb
Host smart-b1da23ac-b0bc-4df2-903f-b210aa09814f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4060456323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4060456323
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.357719541
Short name T937
Test name
Test status
Simulation time 155746224 ps
CPU time 1.04 seconds
Started Apr 16 12:19:54 PM PDT 24
Finished Apr 16 12:19:56 PM PDT 24
Peak memory 191380 kb
Host smart-33e0b346-6e89-429b-a26b-53ebbbaa5ea0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357719541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.357719541
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4049732244
Short name T847
Test name
Test status
Simulation time 50951984 ps
CPU time 1.32 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:49 PM PDT 24
Peak memory 191132 kb
Host smart-467df1f0-7a32-449b-8e85-ee853f0e3516
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4049732244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4049732244
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2963182973
Short name T851
Test name
Test status
Simulation time 109740224 ps
CPU time 0.94 seconds
Started Apr 16 12:21:51 PM PDT 24
Finished Apr 16 12:21:55 PM PDT 24
Peak memory 196952 kb
Host smart-13680687-abc6-4297-8047-ca18c462167d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963182973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2963182973
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3169791190
Short name T911
Test name
Test status
Simulation time 64199431 ps
CPU time 1.21 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 191128 kb
Host smart-69365033-f6a5-42e9-9783-5e17685b09a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3169791190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3169791190
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1310427500
Short name T900
Test name
Test status
Simulation time 68263540 ps
CPU time 1.1 seconds
Started Apr 16 12:22:42 PM PDT 24
Finished Apr 16 12:22:49 PM PDT 24
Peak memory 189640 kb
Host smart-fbbab737-8761-4a7b-be94-3ca5469243e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310427500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1310427500
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1445681518
Short name T852
Test name
Test status
Simulation time 151633489 ps
CPU time 0.92 seconds
Started Apr 16 12:18:09 PM PDT 24
Finished Apr 16 12:18:11 PM PDT 24
Peak memory 197576 kb
Host smart-afa4ac09-af2b-4a5f-a9c7-d80baf46079d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1445681518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1445681518
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607553040
Short name T889
Test name
Test status
Simulation time 66295067 ps
CPU time 1.22 seconds
Started Apr 16 12:20:40 PM PDT 24
Finished Apr 16 12:20:42 PM PDT 24
Peak memory 191396 kb
Host smart-9858e168-4127-43f6-88c6-ca530e07ab0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607553040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1607553040
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1516250736
Short name T846
Test name
Test status
Simulation time 92519884 ps
CPU time 0.84 seconds
Started Apr 16 12:18:18 PM PDT 24
Finished Apr 16 12:18:20 PM PDT 24
Peak memory 191316 kb
Host smart-560b9e0b-7b86-473b-86e1-861a4079b911
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1516250736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1516250736
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.523503788
Short name T892
Test name
Test status
Simulation time 300953738 ps
CPU time 1.15 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 191160 kb
Host smart-8c07040f-6d8f-4083-a27e-fcdeca474dee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523503788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.523503788
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2242815505
Short name T870
Test name
Test status
Simulation time 244029465 ps
CPU time 1.11 seconds
Started Apr 16 12:22:43 PM PDT 24
Finished Apr 16 12:22:50 PM PDT 24
Peak memory 191112 kb
Host smart-bda61e8f-ce4c-4d44-b2cf-4ef0fc9055a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2242815505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2242815505
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459224723
Short name T872
Test name
Test status
Simulation time 134296478 ps
CPU time 1.01 seconds
Started Apr 16 12:21:50 PM PDT 24
Finished Apr 16 12:21:54 PM PDT 24
Peak memory 197444 kb
Host smart-c29a89f3-e28b-44d9-b34a-6fcb410d5e18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459224723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3459224723
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3861246472
Short name T895
Test name
Test status
Simulation time 175344679 ps
CPU time 1.02 seconds
Started Apr 16 12:21:43 PM PDT 24
Finished Apr 16 12:21:47 PM PDT 24
Peak memory 190388 kb
Host smart-b382a5ff-3cae-4794-8ad6-8f85f6dca4f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3861246472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3861246472
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3512508555
Short name T887
Test name
Test status
Simulation time 88239850 ps
CPU time 1.33 seconds
Started Apr 16 12:18:22 PM PDT 24
Finished Apr 16 12:18:24 PM PDT 24
Peak memory 191392 kb
Host smart-2eb7656f-8349-4c79-8485-14ecbc4ccf01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512508555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3512508555
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3955693803
Short name T890
Test name
Test status
Simulation time 37592938 ps
CPU time 1.11 seconds
Started Apr 16 12:18:20 PM PDT 24
Finished Apr 16 12:18:22 PM PDT 24
Peak memory 191328 kb
Host smart-c3951630-9c14-4c74-841a-b6ba9fb64007
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3955693803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3955693803
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2787768377
Short name T867
Test name
Test status
Simulation time 110394435 ps
CPU time 1.7 seconds
Started Apr 16 12:21:20 PM PDT 24
Finished Apr 16 12:21:23 PM PDT 24
Peak memory 190500 kb
Host smart-f43cef8e-7145-441c-b58e-cbe22fc911d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787768377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2787768377
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3426700871
Short name T906
Test name
Test status
Simulation time 161421431 ps
CPU time 1.01 seconds
Started Apr 16 12:21:20 PM PDT 24
Finished Apr 16 12:21:22 PM PDT 24
Peak memory 191028 kb
Host smart-4d74a3ee-ca3a-400d-9639-71ac9c3b105b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3426700871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3426700871
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.348413662
Short name T883
Test name
Test status
Simulation time 52312906 ps
CPU time 1.17 seconds
Started Apr 16 12:18:24 PM PDT 24
Finished Apr 16 12:18:26 PM PDT 24
Peak memory 191332 kb
Host smart-27a2f3e3-112a-41e2-96ea-cfc6523e2393
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348413662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.348413662
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1224507734
Short name T844
Test name
Test status
Simulation time 140668907 ps
CPU time 1.45 seconds
Started Apr 16 12:21:20 PM PDT 24
Finished Apr 16 12:21:23 PM PDT 24
Peak memory 190268 kb
Host smart-d3d18805-a516-4b6b-9bb9-ed6230a7c32d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1224507734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1224507734
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2000881525
Short name T840
Test name
Test status
Simulation time 211797126 ps
CPU time 1.32 seconds
Started Apr 16 12:21:01 PM PDT 24
Finished Apr 16 12:21:03 PM PDT 24
Peak memory 190396 kb
Host smart-9e7f9604-ac77-4a19-8320-a15e9a02b4ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000881525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2000881525
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1555273333
Short name T919
Test name
Test status
Simulation time 55020417 ps
CPU time 1.26 seconds
Started Apr 16 12:21:02 PM PDT 24
Finished Apr 16 12:21:04 PM PDT 24
Peak memory 197480 kb
Host smart-146b367e-fa32-4568-b8e3-8cc4c00effb3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1555273333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1555273333
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2942755170
Short name T855
Test name
Test status
Simulation time 303025719 ps
CPU time 1.33 seconds
Started Apr 16 12:18:32 PM PDT 24
Finished Apr 16 12:18:34 PM PDT 24
Peak memory 197684 kb
Host smart-db3922d5-f21a-454e-bac9-1007ce0b0aef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942755170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2942755170
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3826132320
Short name T907
Test name
Test status
Simulation time 53102208 ps
CPU time 1 seconds
Started Apr 16 12:21:05 PM PDT 24
Finished Apr 16 12:21:07 PM PDT 24
Peak memory 190920 kb
Host smart-3314bea8-5e52-4d17-805e-3dd6035f2dd5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3826132320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3826132320
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2225129313
Short name T881
Test name
Test status
Simulation time 137934749 ps
CPU time 1.1 seconds
Started Apr 16 12:21:06 PM PDT 24
Finished Apr 16 12:21:09 PM PDT 24
Peak memory 191040 kb
Host smart-15c4267e-b98a-44b5-8026-9a0b55ff185f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225129313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2225129313
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2088886399
Short name T871
Test name
Test status
Simulation time 81425538 ps
CPU time 1.5 seconds
Started Apr 16 12:17:55 PM PDT 24
Finished Apr 16 12:17:57 PM PDT 24
Peak memory 191384 kb
Host smart-75a8209f-c289-4823-9afa-336863a120a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2088886399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2088886399
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3211880359
Short name T914
Test name
Test status
Simulation time 64345191 ps
CPU time 1.09 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 190192 kb
Host smart-47c6a4a0-8814-40dd-9494-dfbb31a44191
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211880359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3211880359
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1569065829
Short name T845
Test name
Test status
Simulation time 237178148 ps
CPU time 0.94 seconds
Started Apr 16 12:21:47 PM PDT 24
Finished Apr 16 12:21:51 PM PDT 24
Peak memory 196136 kb
Host smart-57db8515-4738-4eaf-8f62-5bad9e14be15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1569065829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1569065829
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844871494
Short name T873
Test name
Test status
Simulation time 71972766 ps
CPU time 1.06 seconds
Started Apr 16 12:20:57 PM PDT 24
Finished Apr 16 12:20:59 PM PDT 24
Peak memory 197340 kb
Host smart-40033c34-4ade-434e-ad47-52504ba2a441
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844871494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3844871494
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2743461793
Short name T866
Test name
Test status
Simulation time 34661520 ps
CPU time 0.83 seconds
Started Apr 16 12:21:56 PM PDT 24
Finished Apr 16 12:21:58 PM PDT 24
Peak memory 191312 kb
Host smart-9d03b395-f1f7-45a5-8fb1-bff7fda401d5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2743461793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2743461793
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4186808326
Short name T901
Test name
Test status
Simulation time 39011805 ps
CPU time 0.92 seconds
Started Apr 16 12:21:56 PM PDT 24
Finished Apr 16 12:21:59 PM PDT 24
Peak memory 191344 kb
Host smart-c9809fe4-6cf9-4584-9e65-4ef2a39b7a78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186808326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4186808326
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1560062471
Short name T858
Test name
Test status
Simulation time 360567055 ps
CPU time 1.41 seconds
Started Apr 16 12:21:45 PM PDT 24
Finished Apr 16 12:21:49 PM PDT 24
Peak memory 189624 kb
Host smart-0ec45776-dfec-438a-94e7-d53517b08a75
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1560062471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1560062471
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2701391646
Short name T912
Test name
Test status
Simulation time 58625031 ps
CPU time 1.09 seconds
Started Apr 16 12:20:33 PM PDT 24
Finished Apr 16 12:20:34 PM PDT 24
Peak memory 191428 kb
Host smart-2db2d45c-43df-43f3-a59d-8cdb33bb4795
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701391646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2701391646
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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